arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * dtsi file for Hisilicon Hi6220 coresight
   4  *
   5  * Copyright (C) 2017 HiSilicon Ltd.
   6  *
   7  * Author: Pengcheng Li <lipengcheng8@huawei.com>
   8  *         Leo Yan <leo.yan@linaro.org>
   9  */
  10
  11 / {
  12         soc {
  13                 funnel@f6401000 {
  14                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
  15                         reg = <0 0xf6401000 0 0x1000>;
  16                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
  17                         clock-names = "apb_pclk";
  18
  19                         out-ports {
  20                                 port {
  21                                         soc_funnel_out: endpoint {
  22                                                 remote-endpoint =
  23                                                         <&etf_in>;
  24                                         };
  25                                 };
  26                         };
  27
  28                         in-ports {
  29                                 port {
  30                                         soc_funnel_in: endpoint {
  31                                                 remote-endpoint =
  32                                                         <&acpu_funnel_out>;
  33                                         };
  34                                 };
  35                         };
  36                 };
  37
  38                 etf@f6402000 {
  39                         compatible = "arm,coresight-tmc", "arm,primecell";
  40                         reg = <0 0xf6402000 0 0x1000>;
  41                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
  42                         clock-names = "apb_pclk";
  43
  44                         in-ports {
  45                                 port {
  46                                         etf_in: endpoint {
  47                                                 remote-endpoint =
  48                                                         <&soc_funnel_out>;
  49                                         };
  50                                 };
  51                         };
  52
  53                         out-ports {
  54                                 port {
  55                                         etf_out: endpoint {
  56                                                 remote-endpoint =
  57                                                         <&replicator_in>;
  58                                         };
  59                                 };
  60                         };
  61                 };
  62
  63                 replicator {
  64                         compatible = "arm,coresight-static-replicator";
  65                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
  66                         clock-names = "apb_pclk";
  67
  68                         in-ports {
  69                                 port {
  70                                         replicator_in: endpoint {
  71                                                 remote-endpoint =
  72                                                         <&etf_out>;
  73                                         };
  74                                 };
  75                         };
  76
  77                         out-ports {
  78                                 #address-cells = <1>;
  79                                 #size-cells = <0>;
  80
  81                                 port@0 {
  82                                         reg = <0>;
  83                                         replicator_out0: endpoint {
  84                                                 remote-endpoint =
  85                                                         <&etr_in>;
  86                                         };
  87                                 };
  88
  89                                 port@1 {
  90                                         reg = <1>;
  91                                         replicator_out1: endpoint {
  92                                                 remote-endpoint =
  93                                                         <&tpiu_in>;
  94                                         };
  95                                 };
  96                         };
  97                 };
  98
  99                 etr@f6404000 {
 100                         compatible = "arm,coresight-tmc", "arm,primecell";
 101                         reg = <0 0xf6404000 0 0x1000>;
 102                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 103                         clock-names = "apb_pclk";
 104
 105                         in-ports {
 106                                 port {
 107                                         etr_in: endpoint {
 108                                                 remote-endpoint =
 109                                                         <&replicator_out0>;
 110                                         };
 111                                 };
 112                         };
 113                 };
 114
 115                 tpiu@f6405000 {
 116                         compatible = "arm,coresight-tpiu", "arm,primecell";
 117                         reg = <0 0xf6405000 0 0x1000>;
 118                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 119                         clock-names = "apb_pclk";
 120
 121                         in-ports {
 122                                 port {
 123                                         tpiu_in: endpoint {
 124                                                 remote-endpoint =
 125                                                         <&replicator_out1>;
 126                                         };
 127                                 };
 128                         };
 129                 };
 130
 131                 funnel@f6501000 {
 132                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 133                         reg = <0 0xf6501000 0 0x1000>;
 134                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 135                         clock-names = "apb_pclk";
 136
 137                         out-ports {
 138                                 port {
 139                                         acpu_funnel_out: endpoint {
 140                                                 remote-endpoint =
 141                                                         <&soc_funnel_in>;
 142                                         };
 143                                 };
 144                         };
 145
 146                         in-ports {
 147                                 #address-cells = <1>;
 148                                 #size-cells = <0>;
 149
 150                                 port@0 {
 151                                         reg = <0>;
 152                                         acpu_funnel_in0: endpoint {
 153                                                 remote-endpoint =
 154                                                         <&etm0_out>;
 155                                         };
 156                                 };
 157
 158                                 port@1 {
 159                                         reg = <1>;
 160                                         acpu_funnel_in1: endpoint {
 161                                                 remote-endpoint =
 162                                                         <&etm1_out>;
 163                                         };
 164                                 };
 165
 166                                 port@2 {
 167                                         reg = <2>;
 168                                         acpu_funnel_in2: endpoint {
 169                                                 remote-endpoint =
 170                                                         <&etm2_out>;
 171                                         };
 172                                 };
 173
 174                                 port@3 {
 175                                         reg = <3>;
 176                                         acpu_funnel_in3: endpoint {
 177                                                 remote-endpoint =
 178                                                         <&etm3_out>;
 179                                         };
 180                                 };
 181
 182                                 port@4 {
 183                                         reg = <4>;
 184                                         acpu_funnel_in4: endpoint {
 185                                                 remote-endpoint =
 186                                                         <&etm4_out>;
 187                                         };
 188                                 };
 189
 190                                 port@5 {
 191                                         reg = <5>;
 192                                         acpu_funnel_in5: endpoint {
 193                                                 remote-endpoint =
 194                                                         <&etm5_out>;
 195                                         };
 196                                 };
 197
 198                                 port@6 {
 199                                         reg = <6>;
 200                                         acpu_funnel_in6: endpoint {
 201                                                 remote-endpoint =
 202                                                         <&etm6_out>;
 203                                         };
 204                                 };
 205
 206                                 port@7 {
 207                                         reg = <7>;
 208                                         acpu_funnel_in7: endpoint {
 209                                                 remote-endpoint =
 210                                                         <&etm7_out>;
 211                                         };
 212                                 };
 213                         };
 214                 };
 215
 216                 etm0: etm@f659c000 {
 217                         compatible = "arm,coresight-etm4x", "arm,primecell";
 218                         reg = <0 0xf659c000 0 0x1000>;
 219
 220                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 221                         clock-names = "apb_pclk";
 222
 223                         cpu = <&cpu0>;
 224
 225                         out-ports {
 226                                 port {
 227                                         etm0_out: endpoint {
 228                                                 remote-endpoint =
 229                                                         <&acpu_funnel_in0>;
 230                                         };
 231                                 };
 232                         };
 233                 };
 234
 235                 etm1: etm@f659d000 {
 236                         compatible = "arm,coresight-etm4x", "arm,primecell";
 237                         reg = <0 0xf659d000 0 0x1000>;
 238
 239                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 240                         clock-names = "apb_pclk";
 241
 242                         cpu = <&cpu1>;
 243
 244                         out-ports {
 245                                 port {
 246                                         etm1_out: endpoint {
 247                                                 remote-endpoint =
 248                                                         <&acpu_funnel_in1>;
 249                                         };
 250                                 };
 251                         };
 252                 };
 253
 254                 etm2: etm@f659e000 {
 255                         compatible = "arm,coresight-etm4x", "arm,primecell";
 256                         reg = <0 0xf659e000 0 0x1000>;
 257
 258                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 259                         clock-names = "apb_pclk";
 260
 261                         cpu = <&cpu2>;
 262
 263                         out-ports {
 264                                 port {
 265                                         etm2_out: endpoint {
 266                                                 remote-endpoint =
 267                                                         <&acpu_funnel_in2>;
 268                                         };
 269                                 };
 270                         };
 271                 };
 272
 273                 etm3: etm@f659f000 {
 274                         compatible = "arm,coresight-etm4x", "arm,primecell";
 275                         reg = <0 0xf659f000 0 0x1000>;
 276
 277                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 278                         clock-names = "apb_pclk";
 279
 280                         cpu = <&cpu3>;
 281
 282                         out-ports {
 283                                 port {
 284                                         etm3_out: endpoint {
 285                                                 remote-endpoint =
 286                                                         <&acpu_funnel_in3>;
 287                                         };
 288                                 };
 289                         };
 290                 };
 291
 292                 etm4: etm@f65dc000 {
 293                         compatible = "arm,coresight-etm4x", "arm,primecell";
 294                         reg = <0 0xf65dc000 0 0x1000>;
 295
 296                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 297                         clock-names = "apb_pclk";
 298
 299                         cpu = <&cpu4>;
 300
 301                         out-ports {
 302                                 port {
 303                                         etm4_out: endpoint {
 304                                                 remote-endpoint =
 305                                                         <&acpu_funnel_in4>;
 306                                         };
 307                                 };
 308                         };
 309                 };
 310
 311                 etm5: etm@f65dd000 {
 312                         compatible = "arm,coresight-etm4x", "arm,primecell";
 313                         reg = <0 0xf65dd000 0 0x1000>;
 314
 315                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 316                         clock-names = "apb_pclk";
 317
 318                         cpu = <&cpu5>;
 319
 320                         out-ports {
 321                                 port {
 322                                         etm5_out: endpoint {
 323                                                 remote-endpoint =
 324                                                         <&acpu_funnel_in5>;
 325                                         };
 326                                 };
 327                         };
 328                 };
 329
 330                 etm6: etm@f65de000 {
 331                         compatible = "arm,coresight-etm4x", "arm,primecell";
 332                         reg = <0 0xf65de000 0 0x1000>;
 333
 334                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 335                         clock-names = "apb_pclk";
 336
 337                         cpu = <&cpu6>;
 338
 339                         out-ports {
 340                                 port {
 341                                         etm6_out: endpoint {
 342                                                 remote-endpoint =
 343                                                         <&acpu_funnel_in6>;
 344                                         };
 345                                 };
 346                         };
 347                 };
 348
 349                 etm7: etm@f65df000 {
 350                         compatible = "arm,coresight-etm4x", "arm,primecell";
 351                         reg = <0 0xf65df000 0 0x1000>;
 352
 353                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 354                         clock-names = "apb_pclk";
 355
 356                         cpu = <&cpu7>;
 357
 358                         out-ports {
 359                                 port {
 360                                         etm7_out: endpoint {
 361                                                 remote-endpoint =
 362                                                         <&acpu_funnel_in7>;
 363                                         };
 364                                 };
 365                         };
 366                 };
 367
 368                 /* System CTIs */
 369                 /* CTI 0 - TMC and TPIU connections */
 370                 cti@f6403000 {
 371                         compatible = "arm,coresight-cti", "arm,primecell";
 372                         reg = <0 0xf6403000 0 0x1000>;
 373
 374                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 375                         clock-names = "apb_pclk";
 376                 };
 377
 378                 /* CTI - CPU-0 */
 379                 cti@f6598000 {
 380                         compatible = "arm,coresight-cti-v8-arch",
 381                                      "arm,coresight-cti", "arm,primecell";
 382                         reg = <0 0xf6598000 0 0x1000>;
 383
 384                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 385                         clock-names = "apb_pclk";
 386
 387                         cpu = <&cpu0>;
 388                         arm,cs-dev-assoc = <&etm0>;
 389                 };
 390
 391                 /* CTI - CPU-1 */
 392                 cti@f6599000 {
 393                         compatible = "arm,coresight-cti-v8-arch",
 394                                      "arm,coresight-cti", "arm,primecell";
 395                         reg = <0 0xf6599000 0 0x1000>;
 396
 397                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 398                         clock-names = "apb_pclk";
 399
 400                         cpu = <&cpu1>;
 401                         arm,cs-dev-assoc = <&etm1>;
 402                 };
 403
 404                 /* CTI - CPU-2 */
 405                 cti@f659a000 {
 406                         compatible = "arm,coresight-cti-v8-arch",
 407                                      "arm,coresight-cti", "arm,primecell";
 408                         reg = <0 0xf659a000 0 0x1000>;
 409
 410                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 411                         clock-names = "apb_pclk";
 412
 413                         cpu = <&cpu2>;
 414                         arm,cs-dev-assoc = <&etm2>;
 415                 };
 416
 417                 /* CTI - CPU-3 */
 418                 cti@f659b000 {
 419                         compatible = "arm,coresight-cti-v8-arch",
 420                                      "arm,coresight-cti", "arm,primecell";
 421                         reg = <0 0xf659b000 0 0x1000>;
 422
 423                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 424                         clock-names = "apb_pclk";
 425
 426                         cpu = <&cpu3>;
 427                         arm,cs-dev-assoc = <&etm3>;
 428                 };
 429
 430                 /* CTI - CPU-4 */
 431                 cti@f65d8000 {
 432                         compatible = "arm,coresight-cti-v8-arch",
 433                                      "arm,coresight-cti", "arm,primecell";
 434                         reg = <0 0xf65d8000 0 0x1000>;
 435
 436                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 437                         clock-names = "apb_pclk";
 438
 439                         cpu = <&cpu4>;
 440                         arm,cs-dev-assoc = <&etm4>;
 441                 };
 442
 443                 /* CTI - CPU-5 */
 444                 cti@f65d9000 {
 445                         compatible = "arm,coresight-cti-v8-arch",
 446                                      "arm,coresight-cti", "arm,primecell";
 447                         reg = <0 0xf65d9000 0 0x1000>;
 448
 449                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 450                         clock-names = "apb_pclk";
 451
 452                         cpu = <&cpu5>;
 453                         arm,cs-dev-assoc = <&etm5>;
 454                 };
 455
 456                 /* CTI - CPU-6 */
 457                 cti@f65da000 {
 458                         compatible = "arm,coresight-cti-v8-arch",
 459                                      "arm,coresight-cti", "arm,primecell";
 460                         reg = <0 0xf65da000 0 0x1000>;
 461
 462                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 463                         clock-names = "apb_pclk";
 464
 465                         cpu = <&cpu6>;
 466                         arm,cs-dev-assoc = <&etm6>;
 467                 };
 468
 469                 /* CTI - CPU-7 */
 470                 cti@f65db000 {
 471                         compatible = "arm,coresight-cti-v8-arch",
 472                                      "arm,coresight-cti", "arm,primecell";
 473                         reg = <0 0xf65db000 0 0x1000>;
 474
 475                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
 476                         clock-names = "apb_pclk";
 477
 478                         cpu = <&cpu7>;
 479                         arm,cs-dev-assoc = <&etm7>;
 480                 };
 481         };
 482 };