arch/arm64/boot/dts/freescale/imx8qm.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  *      Dong Aisheng <aisheng.dong@nxp.com>
   5  */
   6
   7 #include <dt-bindings/clock/imx8-lpcg.h>
   8 #include <dt-bindings/firmware/imx/rsrc.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
  12
  13 / {
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 mmc0 = &usdhc1;
  20                 mmc1 = &usdhc2;
  21                 mmc2 = &usdhc3;
  22                 serial0 = &lpuart0;
  23         };
  24
  25         cpus {
  26                 #address-cells = <2>;
  27                 #size-cells = <0>;
  28
  29                 cpu-map {
  30                         cluster0 {
  31                                 core0 {
  32                                         cpu = <&A53_0>;
  33                                 };
  34                                 core1 {
  35                                         cpu = <&A53_1>;
  36                                 };
  37                                 core2 {
  38                                         cpu = <&A53_2>;
  39                                 };
  40                                 core3 {
  41                                         cpu = <&A53_3>;
  42                                 };
  43                         };
  44
  45                         cluster1 {
  46                                 core0 {
  47                                         cpu = <&A72_0>;
  48                                 };
  49                                 core1 {
  50                                         cpu = <&A72_1>;
  51                                 };
  52                         };
  53                 };
  54
  55                 A53_0: cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53", "arm,armv8";
  58                         reg = <0x0 0x0>;
  59                         enable-method = "psci";
  60                         next-level-cache = <&A53_L2>;
  61                 };
  62
  63                 A53_1: cpu@1 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a53", "arm,armv8";
  66                         reg = <0x0 0x1>;
  67                         enable-method = "psci";
  68                         next-level-cache = <&A53_L2>;
  69                 };
  70
  71                 A53_2: cpu@2 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53", "arm,armv8";
  74                         reg = <0x0 0x2>;
  75                         enable-method = "psci";
  76                         next-level-cache = <&A53_L2>;
  77                 };
  78
  79                 A53_3: cpu@3 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x3>;
  83                         enable-method = "psci";
  84                         next-level-cache = <&A53_L2>;
  85                 };
  86
  87                 A72_0: cpu@100 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a72", "arm,armv8";
  90                         reg = <0x0 0x100>;
  91                         enable-method = "psci";
  92                         next-level-cache = <&A72_L2>;
  93                 };
  94
  95                 A72_1: cpu@101 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a72", "arm,armv8";
  98                         reg = <0x0 0x101>;
  99                         enable-method = "psci";
 100                         next-level-cache = <&A72_L2>;
 101                 };
 102
 103                 A53_L2: l2-cache0 {
 104                         compatible = "cache";
 105                 };
 106
 107                 A72_L2: l2-cache1 {
 108                         compatible = "cache";
 109                 };
 110         };
 111
 112         gic: interrupt-controller@51a00000 {
 113                 compatible = "arm,gic-v3";
 114                 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
 115                       <0x0 0x51b00000 0 0xC0000>, /* GICR */
 116                       <0x0 0x52000000 0 0x2000>,  /* GICC */
 117                       <0x0 0x52010000 0 0x1000>,  /* GICH */
 118                       <0x0 0x52020000 0 0x20000>; /* GICV */
 119                 #interrupt-cells = <3>;
 120                 interrupt-controller;
 121                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 122                 interrupt-parent = <&gic>;
 123         };
 124
 125         pmu {
 126                 compatible = "arm,armv8-pmuv3";
 127                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 128         };
 129
 130         psci {
 131                 compatible = "arm,psci-1.0";
 132                 method = "smc";
 133         };
 134
 135         timer {
 136                 compatible = "arm,armv8-timer";
 137                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 138                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 139                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 140                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 141         };
 142
 143         scu {
 144                 compatible = "fsl,imx-scu";
 145                 mbox-names = "tx0",
 146                              "rx0",
 147                              "gip3";
 148                 mboxes = <&lsio_mu1 0 0
 149                           &lsio_mu1 1 0
 150                           &lsio_mu1 3 3>;
 151
 152                 pd: imx8qx-pd {
 153                         compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
 154                         #power-domain-cells = <1>;
 155                 };
 156
 157                 clk: clock-controller {
 158                         compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
 159                         #clock-cells = <2>;
 160                 };
 161
 162                 iomuxc: pinctrl {
 163                         compatible = "fsl,imx8qm-iomuxc";
 164                 };
 165
 166         };
 167
 168         /* sorted in register address */
 169         #include "imx8-ss-img.dtsi"
 170         #include "imx8-ss-dma.dtsi"
 171         #include "imx8-ss-conn.dtsi"
 172         #include "imx8-ss-lsio.dtsi"
 173 };
 174
 175 #include "imx8qm-ss-img.dtsi"
 176 #include "imx8qm-ss-dma.dtsi"
 177 #include "imx8qm-ss-conn.dtsi"
 178 #include "imx8qm-ss-lsio.dtsi"