arch/arm64/boot/dts/freescale/imx8mq-evk.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "imx8mq.dtsi"
  10
  11 / {
  12         model = "NXP i.MX8MQ EVK";
  13         compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
  14
  15         chosen {
  16                 stdout-path = &uart1;
  17         };
  18
  19         memory@40000000 {
  20                 device_type = "memory";
  21                 reg = <0x00000000 0x40000000 0 0xc0000000>;
  22         };
  23
  24         pcie0_refclk: pcie0-refclk {
  25                 compatible = "fixed-clock";
  26                 #clock-cells = <0>;
  27                 clock-frequency = <100000000>;
  28         };
  29
  30         reg_usdhc2_vmmc: regulator-vsd-3v3 {
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&pinctrl_reg_usdhc2>;
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "VSD_3V3";
  35                 regulator-min-microvolt = <3300000>;
  36                 regulator-max-microvolt = <3300000>;
  37                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  38                 enable-active-high;
  39         };
  40
  41         buck2_reg: regulator-buck2 {
  42                 pinctrl-names = "default";
  43                 pinctrl-0 = <&pinctrl_buck2>;
  44                 compatible = "regulator-gpio";
  45                 regulator-name = "vdd_arm";
  46                 regulator-min-microvolt = <900000>;
  47                 regulator-max-microvolt = <1000000>;
  48                 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  49                 states = <1000000 0x0
  50                           900000 0x1>;
  51                 regulator-boot-on;
  52                 regulator-always-on;
  53         };
  54
  55         ir-receiver {
  56                 compatible = "gpio-ir-receiver";
  57                 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
  58                 pinctrl-names = "default";
  59                 pinctrl-0 = <&pinctrl_ir>;
  60                 linux,autosuspend-period = <125>;
  61         };
  62
  63         wm8524: audio-codec {
  64                 #sound-dai-cells = <0>;
  65                 compatible = "wlf,wm8524";
  66                 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
  67         };
  68
  69         sound-wm8524 {
  70                 compatible = "simple-audio-card";
  71                 simple-audio-card,name = "wm8524-audio";
  72                 simple-audio-card,format = "i2s";
  73                 simple-audio-card,frame-master = <&cpudai>;
  74                 simple-audio-card,bitclock-master = <&cpudai>;
  75                 simple-audio-card,widgets =
  76                         "Line", "Left Line Out Jack",
  77                         "Line", "Right Line Out Jack";
  78                 simple-audio-card,routing =
  79                         "Left Line Out Jack", "LINEVOUTL",
  80                         "Right Line Out Jack", "LINEVOUTR";
  81
  82                 cpudai: simple-audio-card,cpu {
  83                         sound-dai = <&sai2>;
  84                 };
  85
  86                 link_codec: simple-audio-card,codec {
  87                         sound-dai = <&wm8524>;
  88                         clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
  89                 };
  90         };
  91
  92         sound-spdif {
  93                 compatible = "fsl,imx-audio-spdif";
  94                 model = "imx-spdif";
  95                 spdif-controller = <&spdif1>;
  96                 spdif-out;
  97                 spdif-in;
  98         };
  99
 100         sound-hdmi-arc {
 101                 compatible = "fsl,imx-audio-spdif";
 102                 model = "imx-hdmi-arc";
 103                 spdif-controller = <&spdif2>;
 104                 spdif-in;
 105         };
 106 };
 107
 108 &A53_0 {
 109         cpu-supply = <&buck2_reg>;
 110 };
 111
 112 &A53_1 {
 113         cpu-supply = <&buck2_reg>;
 114 };
 115
 116 &A53_2 {
 117         cpu-supply = <&buck2_reg>;
 118 };
 119
 120 &A53_3 {
 121         cpu-supply = <&buck2_reg>;
 122 };
 123
 124 &ddrc {
 125         operating-points-v2 = <&ddrc_opp_table>;
 126
 127         ddrc_opp_table: opp-table {
 128                 compatible = "operating-points-v2";
 129
 130                 opp-25M {
 131                         opp-hz = /bits/ 64 <25000000>;
 132                 };
 133
 134                 opp-100M {
 135                         opp-hz = /bits/ 64 <100000000>;
 136                 };
 137
 138                 /*
 139                  * On imx8mq B0 PLL can't be bypassed so low bus is 166M
 140                  */
 141                 opp-166M {
 142                         opp-hz = /bits/ 64 <166935483>;
 143                 };
 144
 145                 opp-800M {
 146                         opp-hz = /bits/ 64 <800000000>;
 147                 };
 148         };
 149 };
 150
 151 &dphy {
 152         status = "okay";
 153 };
 154
 155 &fec1 {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_fec1>;
 158         phy-mode = "rgmii-id";
 159         phy-handle = <&ethphy0>;
 160         fsl,magic-packet;
 161         status = "okay";
 162
 163         mdio {
 164                 #address-cells = <1>;
 165                 #size-cells = <0>;
 166
 167                 ethphy0: ethernet-phy@0 {
 168                         compatible = "ethernet-phy-ieee802.3-c22";
 169                         reg = <0>;
 170                         reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 171                         reset-assert-us = <10000>;
 172                 };
 173         };
 174 };
 175
 176 &gpio5 {
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&pinctrl_wifi_reset>;
 179
 180         wl-reg-on-hog {
 181                 gpio-hog;
 182                 gpios = <29 GPIO_ACTIVE_HIGH>;
 183                 output-high;
 184         };
 185 };
 186
 187 &i2c1 {
 188         clock-frequency = <100000>;
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&pinctrl_i2c1>;
 191         status = "okay";
 192
 193         pmic@8 {
 194                 compatible = "fsl,pfuze100";
 195                 reg = <0x8>;
 196
 197                 regulators {
 198                         sw1a_reg: sw1ab {
 199                                 regulator-min-microvolt = <825000>;
 200                                 regulator-max-microvolt = <1100000>;
 201                         };
 202
 203                         sw1c_reg: sw1c {
 204                                 regulator-min-microvolt = <825000>;
 205                                 regulator-max-microvolt = <1100000>;
 206                         };
 207
 208                         sw2_reg: sw2 {
 209                                 regulator-min-microvolt = <1100000>;
 210                                 regulator-max-microvolt = <1100000>;
 211                                 regulator-always-on;
 212                         };
 213
 214                         sw3a_reg: sw3ab {
 215                                 regulator-min-microvolt = <825000>;
 216                                 regulator-max-microvolt = <1100000>;
 217                                 regulator-always-on;
 218                         };
 219
 220                         sw4_reg: sw4 {
 221                                 regulator-min-microvolt = <1800000>;
 222                                 regulator-max-microvolt = <1800000>;
 223                                 regulator-always-on;
 224                         };
 225
 226                         swbst_reg: swbst {
 227                                 regulator-min-microvolt = <5000000>;
 228                                 regulator-max-microvolt = <5150000>;
 229                         };
 230
 231                         snvs_reg: vsnvs {
 232                                 regulator-min-microvolt = <1000000>;
 233                                 regulator-max-microvolt = <3000000>;
 234                                 regulator-always-on;
 235                         };
 236
 237                         vref_reg: vrefddr {
 238                                 regulator-always-on;
 239                         };
 240
 241                         vgen1_reg: vgen1 {
 242                                 regulator-min-microvolt = <800000>;
 243                                 regulator-max-microvolt = <1550000>;
 244                         };
 245
 246                         vgen2_reg: vgen2 {
 247                                 regulator-min-microvolt = <850000>;
 248                                 regulator-max-microvolt = <975000>;
 249                                 regulator-always-on;
 250                         };
 251
 252                         vgen3_reg: vgen3 {
 253                                 regulator-min-microvolt = <1675000>;
 254                                 regulator-max-microvolt = <1975000>;
 255                                 regulator-always-on;
 256                         };
 257
 258                         vgen4_reg: vgen4 {
 259                                 regulator-min-microvolt = <1625000>;
 260                                 regulator-max-microvolt = <1875000>;
 261                                 regulator-always-on;
 262                         };
 263
 264                         vgen5_reg: vgen5 {
 265                                 regulator-min-microvolt = <3075000>;
 266                                 regulator-max-microvolt = <3625000>;
 267                                 regulator-always-on;
 268                         };
 269
 270                         vgen6_reg: vgen6 {
 271                                 regulator-min-microvolt = <1800000>;
 272                                 regulator-max-microvolt = <3300000>;
 273                         };
 274                 };
 275         };
 276 };
 277
 278 &lcdif {
 279         status = "okay";
 280 };
 281
 282 &mipi_dsi {
 283         #address-cells = <1>;
 284         #size-cells = <0>;
 285         status = "okay";
 286
 287         panel@0 {
 288                 pinctrl-0 = <&pinctrl_mipi_dsi>;
 289                 pinctrl-names = "default";
 290                 compatible = "raydium,rm67191";
 291                 reg = <0>;
 292                 reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
 293                 dsi-lanes = <4>;
 294
 295                 port {
 296                         panel_in: endpoint {
 297                                 remote-endpoint = <&mipi_dsi_out>;
 298                         };
 299                 };
 300         };
 301
 302         ports {
 303                 port@1 {
 304                         reg = <1>;
 305                         mipi_dsi_out: endpoint {
 306                                 remote-endpoint = <&panel_in>;
 307                         };
 308                 };
 309         };
 310 };
 311
 312 &pcie0 {
 313         pinctrl-names = "default";
 314         pinctrl-0 = <&pinctrl_pcie0>;
 315         reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
 316         clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
 317                  <&clk IMX8MQ_CLK_PCIE1_AUX>,
 318                  <&clk IMX8MQ_CLK_PCIE1_PHY>,
 319                  <&pcie0_refclk>;
 320         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
 321         vph-supply = <&vgen5_reg>;
 322         status = "okay";
 323 };
 324
 325 &pgc_gpu {
 326         power-supply = <&sw1a_reg>;
 327 };
 328
 329 &qspi0 {
 330         pinctrl-names = "default";
 331         pinctrl-0 = <&pinctrl_qspi>;
 332         status = "okay";
 333
 334         n25q256a: flash@0 {
 335                 reg = <0>;
 336                 #address-cells = <1>;
 337                 #size-cells = <1>;
 338                 compatible = "micron,n25q256a", "jedec,spi-nor";
 339                 spi-max-frequency = <29000000>;
 340         };
 341 };
 342
 343 &sai2 {
 344         pinctrl-names = "default";
 345         pinctrl-0 = <&pinctrl_sai2>;
 346         assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
 347         assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
 348         assigned-clock-rates = <0>, <24576000>;
 349         status = "okay";
 350 };
 351
 352 &snvs_pwrkey {
 353         status = "okay";
 354 };
 355
 356 &spdif1 {
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_spdif1>;
 359         assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
 360         assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
 361         assigned-clock-rates = <24576000>;
 362         status = "okay";
 363 };
 364
 365 &spdif2 {
 366         assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
 367         assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
 368         assigned-clock-rates = <24576000>;
 369         status = "okay";
 370 };
 371
 372 &uart1 {
 373         pinctrl-names = "default";
 374         pinctrl-0 = <&pinctrl_uart1>;
 375         status = "okay";
 376 };
 377
 378 &usb3_phy1 {
 379         status = "okay";
 380 };
 381
 382 &usb_dwc3_1 {
 383         dr_mode = "host";
 384         status = "okay";
 385 };
 386
 387 &usdhc1 {
 388         assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
 389         assigned-clock-rates = <400000000>;
 390         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 391         pinctrl-0 = <&pinctrl_usdhc1>;
 392         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 393         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 394         vqmmc-supply = <&sw4_reg>;
 395         bus-width = <8>;
 396         non-removable;
 397         no-sd;
 398         no-sdio;
 399         status = "okay";
 400 };
 401
 402 &usdhc2 {
 403         assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
 404         assigned-clock-rates = <200000000>;
 405         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 406         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 407         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 408         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 409         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 410         vmmc-supply = <&reg_usdhc2_vmmc>;
 411         status = "okay";
 412 };
 413
 414 &wdog1 {
 415         pinctrl-names = "default";
 416         pinctrl-0 = <&pinctrl_wdog>;
 417         fsl,ext-reset-output;
 418         status = "okay";
 419 };
 420
 421 &iomuxc {
 422         pinctrl_buck2: vddarmgrp {
 423                 fsl,pins = <
 424                         MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x19
 425                 >;
 426         };
 427
 428         pinctrl_fec1: fec1grp {
 429                 fsl,pins = <
 430                         MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 431                         MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
 432                         MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 433                         MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 434                         MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 435                         MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 436                         MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 437                         MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 438                         MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 439                         MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 440                         MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 441                         MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 442                         MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 443                         MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 444                         MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19
 445                 >;
 446         };
 447
 448         pinctrl_i2c1: i2c1grp {
 449                 fsl,pins = <
 450                         MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x4000007f
 451                         MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                  0x4000007f
 452                 >;
 453         };
 454
 455         pinctrl_ir: irgrp {
 456                 fsl,pins = <
 457                         MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12              0x4f
 458                 >;
 459         };
 460
 461         pinctrl_mipi_dsi: mipidsigrp {
 462                 fsl,pins = <
 463                         MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6              0x16
 464                 >;
 465         };
 466
 467         pinctrl_pcie0: pcie0grp {
 468                 fsl,pins = <
 469                         MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B            0x76
 470                         MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28               0x16
 471                 >;
 472         };
 473
 474         pinctrl_qspi: qspigrp {
 475                 fsl,pins = <
 476                         MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK       0x82
 477                         MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B    0x82
 478                         MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0   0x82
 479                         MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1   0x82
 480                         MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2   0x82
 481                         MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3   0x82
 482                 >;
 483         };
 484
 485         pinctrl_reg_usdhc2: regusdhc2gpiogrp {
 486                 fsl,pins = <
 487                         MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41
 488                 >;
 489         };
 490
 491         pinctrl_sai2: sai2grp {
 492                 fsl,pins = <
 493                         MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
 494                         MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
 495                         MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
 496                         MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
 497                         MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
 498                 >;
 499         };
 500
 501         pinctrl_spdif1: spdif1grp {
 502                 fsl,pins = <
 503                         MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT        0xd6
 504                         MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN         0xd6
 505                 >;
 506         };
 507
 508         pinctrl_uart1: uart1grp {
 509                 fsl,pins = <
 510                         MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49
 511                         MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x49
 512                 >;
 513         };
 514
 515         pinctrl_usdhc1: usdhc1grp {
 516                 fsl,pins = <
 517                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x83
 518                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc3
 519                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc3
 520                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc3
 521                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc3
 522                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc3
 523                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc3
 524                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc3
 525                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc3
 526                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc3
 527                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x83
 528                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 529                 >;
 530         };
 531
 532         pinctrl_usdhc1_100mhz: usdhc1-100grp {
 533                 fsl,pins = <
 534                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
 535                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
 536                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xcd
 537                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xcd
 538                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xcd
 539                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xcd
 540                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xcd
 541                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xcd
 542                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xcd
 543                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xcd
 544                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x8d
 545                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 546                 >;
 547         };
 548
 549         pinctrl_usdhc1_200mhz: usdhc1-200grp {
 550                 fsl,pins = <
 551                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
 552                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
 553                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xdf
 554                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xdf
 555                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xdf
 556                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xdf
 557                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xdf
 558                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xdf
 559                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xdf
 560                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xdf
 561                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x9f
 562                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 563                 >;
 564         };
 565
 566         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 567                 fsl,pins = <
 568                         MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12                0x41
 569                 >;
 570         };
 571
 572         pinctrl_usdhc2: usdhc2grp {
 573                 fsl,pins = <
 574                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x83
 575                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc3
 576                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc3
 577                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc3
 578                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc3
 579                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc3
 580                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 581                 >;
 582         };
 583
 584         pinctrl_usdhc2_100mhz: usdhc2-100grp {
 585                 fsl,pins = <
 586                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
 587                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
 588                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc5
 589                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc5
 590                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc5
 591                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc5
 592                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 593                 >;
 594         };
 595
 596         pinctrl_usdhc2_200mhz: usdhc2-200grp {
 597                 fsl,pins = <
 598                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
 599                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7
 600                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc7
 601                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc7
 602                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc7
 603                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc7
 604                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 605                 >;
 606         };
 607
 608         pinctrl_wdog: wdog1grp {
 609                 fsl,pins = <
 610                         MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 611                 >;
 612         };
 613
 614         pinctrl_wifi_reset: wifiresetgrp {
 615                 fsl,pins = <
 616                         MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29               0x16
 617                 >;
 618         };
 619 };