arch/arm64/boot/dts/freescale/imx8mp.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mp-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 #include "imx8mp-pinfunc.h"
  13
  14 / {
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 ethernet0 = &fec;
  21                 ethernet1 = &eqos;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 i2c0 = &i2c1;
  28                 i2c1 = &i2c2;
  29                 i2c2 = &i2c3;
  30                 i2c3 = &i2c4;
  31                 i2c4 = &i2c5;
  32                 i2c5 = &i2c6;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 spi0 = &flexspi;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 A53_0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         reg = <0x0>;
  51                         clock-latency = <61036>;
  52                         clocks = <&clk IMX8MP_CLK_ARM>;
  53                         enable-method = "psci";
  54                         next-level-cache = <&A53_L2>;
  55                         #cooling-cells = <2>;
  56                 };
  57
  58                 A53_1: cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53";
  61                         reg = <0x1>;
  62                         clock-latency = <61036>;
  63                         clocks = <&clk IMX8MP_CLK_ARM>;
  64                         enable-method = "psci";
  65                         next-level-cache = <&A53_L2>;
  66                         #cooling-cells = <2>;
  67                 };
  68
  69                 A53_2: cpu@2 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53";
  72                         reg = <0x2>;
  73                         clock-latency = <61036>;
  74                         clocks = <&clk IMX8MP_CLK_ARM>;
  75                         enable-method = "psci";
  76                         next-level-cache = <&A53_L2>;
  77                         #cooling-cells = <2>;
  78                 };
  79
  80                 A53_3: cpu@3 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53";
  83                         reg = <0x3>;
  84                         clock-latency = <61036>;
  85                         clocks = <&clk IMX8MP_CLK_ARM>;
  86                         enable-method = "psci";
  87                         next-level-cache = <&A53_L2>;
  88                         #cooling-cells = <2>;
  89                 };
  90
  91                 A53_L2: l2-cache0 {
  92                         compatible = "cache";
  93                 };
  94         };
  95
  96         osc_32k: clock-osc-32k {
  97                 compatible = "fixed-clock";
  98                 #clock-cells = <0>;
  99                 clock-frequency = <32768>;
 100                 clock-output-names = "osc_32k";
 101         };
 102
 103         osc_24m: clock-osc-24m {
 104                 compatible = "fixed-clock";
 105                 #clock-cells = <0>;
 106                 clock-frequency = <24000000>;
 107                 clock-output-names = "osc_24m";
 108         };
 109
 110         clk_ext1: clock-ext1 {
 111                 compatible = "fixed-clock";
 112                 #clock-cells = <0>;
 113                 clock-frequency = <133000000>;
 114                 clock-output-names = "clk_ext1";
 115         };
 116
 117         clk_ext2: clock-ext2 {
 118                 compatible = "fixed-clock";
 119                 #clock-cells = <0>;
 120                 clock-frequency = <133000000>;
 121                 clock-output-names = "clk_ext2";
 122         };
 123
 124         clk_ext3: clock-ext3 {
 125                 compatible = "fixed-clock";
 126                 #clock-cells = <0>;
 127                 clock-frequency = <133000000>;
 128                 clock-output-names = "clk_ext3";
 129         };
 130
 131         clk_ext4: clock-ext4 {
 132                 compatible = "fixed-clock";
 133                 #clock-cells = <0>;
 134                 clock-frequency= <133000000>;
 135                 clock-output-names = "clk_ext4";
 136         };
 137
 138         reserved-memory {
 139                 #address-cells = <2>;
 140                 #size-cells = <2>;
 141                 ranges;
 142
 143                 dsp_reserved: dsp@92400000 {
 144                         reg = <0 0x92400000 0 0x2000000>;
 145                         no-map;
 146                 };
 147         };
 148
 149         pmu {
 150                 compatible = "arm,cortex-a53-pmu";
 151                 interrupts = <GIC_PPI 7
 152                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 153         };
 154
 155         psci {
 156                 compatible = "arm,psci-1.0";
 157                 method = "smc";
 158         };
 159
 160         thermal-zones {
 161                 cpu-thermal {
 162                         polling-delay-passive = <250>;
 163                         polling-delay = <2000>;
 164                         thermal-sensors = <&tmu 0>;
 165                         trips {
 166                                 cpu_alert0: trip0 {
 167                                         temperature = <85000>;
 168                                         hysteresis = <2000>;
 169                                         type = "passive";
 170                                 };
 171
 172                                 cpu_crit0: trip1 {
 173                                         temperature = <95000>;
 174                                         hysteresis = <2000>;
 175                                         type = "critical";
 176                                 };
 177                         };
 178
 179                         cooling-maps {
 180                                 map0 {
 181                                         trip = <&cpu_alert0>;
 182                                         cooling-device =
 183                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 184                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 185                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 186                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 187                                 };
 188                         };
 189                 };
 190
 191                 soc-thermal {
 192                         polling-delay-passive = <250>;
 193                         polling-delay = <2000>;
 194                         thermal-sensors = <&tmu 1>;
 195                         trips {
 196                                 soc_alert0: trip0 {
 197                                         temperature = <85000>;
 198                                         hysteresis = <2000>;
 199                                         type = "passive";
 200                                 };
 201
 202                                 soc_crit0: trip1 {
 203                                         temperature = <95000>;
 204                                         hysteresis = <2000>;
 205                                         type = "critical";
 206                                 };
 207                         };
 208
 209                         cooling-maps {
 210                                 map0 {
 211                                         trip = <&soc_alert0>;
 212                                         cooling-device =
 213                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 214                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 215                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 216                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 217                                 };
 218                         };
 219                 };
 220         };
 221
 222         timer {
 223                 compatible = "arm,armv8-timer";
 224                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 225                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 226                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 227                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 228                 clock-frequency = <8000000>;
 229                 arm,no-tick-in-suspend;
 230         };
 231
 232         soc@0 {
 233                 compatible = "fsl,imx8mp-soc", "simple-bus";
 234                 #address-cells = <1>;
 235                 #size-cells = <1>;
 236                 ranges = <0x0 0x0 0x0 0x3e000000>;
 237                 nvmem-cells = <&imx8mp_uid>;
 238                 nvmem-cell-names = "soc_unique_id";
 239
 240                 aips1: bus@30000000 {
 241                         compatible = "fsl,aips-bus", "simple-bus";
 242                         reg = <0x30000000 0x400000>;
 243                         #address-cells = <1>;
 244                         #size-cells = <1>;
 245                         ranges;
 246
 247                         gpio1: gpio@30200000 {
 248                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 249                                 reg = <0x30200000 0x10000>;
 250                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 251                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 252                                 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
 253                                 gpio-controller;
 254                                 #gpio-cells = <2>;
 255                                 interrupt-controller;
 256                                 #interrupt-cells = <2>;
 257                                 gpio-ranges = <&iomuxc 0 5 30>;
 258                         };
 259
 260                         gpio2: gpio@30210000 {
 261                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 262                                 reg = <0x30210000 0x10000>;
 263                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 264                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 265                                 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
 266                                 gpio-controller;
 267                                 #gpio-cells = <2>;
 268                                 interrupt-controller;
 269                                 #interrupt-cells = <2>;
 270                                 gpio-ranges = <&iomuxc 0 35 21>;
 271                         };
 272
 273                         gpio3: gpio@30220000 {
 274                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 275                                 reg = <0x30220000 0x10000>;
 276                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 277                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 278                                 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
 279                                 gpio-controller;
 280                                 #gpio-cells = <2>;
 281                                 interrupt-controller;
 282                                 #interrupt-cells = <2>;
 283                                 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
 284                         };
 285
 286                         gpio4: gpio@30230000 {
 287                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 288                                 reg = <0x30230000 0x10000>;
 289                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 290                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 291                                 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
 292                                 gpio-controller;
 293                                 #gpio-cells = <2>;
 294                                 interrupt-controller;
 295                                 #interrupt-cells = <2>;
 296                                 gpio-ranges = <&iomuxc 0 82 32>;
 297                         };
 298
 299                         gpio5: gpio@30240000 {
 300                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 301                                 reg = <0x30240000 0x10000>;
 302                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 303                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 304                                 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
 305                                 gpio-controller;
 306                                 #gpio-cells = <2>;
 307                                 interrupt-controller;
 308                                 #interrupt-cells = <2>;
 309                                 gpio-ranges = <&iomuxc 0 114 30>;
 310                         };
 311
 312                         tmu: tmu@30260000 {
 313                                 compatible = "fsl,imx8mp-tmu";
 314                                 reg = <0x30260000 0x10000>;
 315                                 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
 316                                 #thermal-sensor-cells = <1>;
 317                         };
 318
 319                         wdog1: watchdog@30280000 {
 320                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 321                                 reg = <0x30280000 0x10000>;
 322                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 323                                 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
 324                                 status = "disabled";
 325                         };
 326
 327                         wdog2: watchdog@30290000 {
 328                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 329                                 reg = <0x30290000 0x10000>;
 330                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 331                                 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
 332                                 status = "disabled";
 333                         };
 334
 335                         wdog3: watchdog@302a0000 {
 336                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 337                                 reg = <0x302a0000 0x10000>;
 338                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 339                                 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
 340                                 status = "disabled";
 341                         };
 342
 343                         iomuxc: pinctrl@30330000 {
 344                                 compatible = "fsl,imx8mp-iomuxc";
 345                                 reg = <0x30330000 0x10000>;
 346                         };
 347
 348                         gpr: iomuxc-gpr@30340000 {
 349                                 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
 350                                 reg = <0x30340000 0x10000>;
 351                         };
 352
 353                         ocotp: efuse@30350000 {
 354                                 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
 355                                 reg = <0x30350000 0x10000>;
 356                                 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
 357                                 /* For nvmem subnodes */
 358                                 #address-cells = <1>;
 359                                 #size-cells = <1>;
 360
 361                                 imx8mp_uid: unique-id@420 {
 362                                         reg = <0x8 0x8>;
 363                                 };
 364
 365                                 cpu_speed_grade: speed-grade@10 {
 366                                         reg = <0x10 4>;
 367                                 };
 368
 369                                 eth_mac1: mac-address@90 {
 370                                         reg = <0x90 6>;
 371                                 };
 372                         };
 373
 374                         anatop: anatop@30360000 {
 375                                 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
 376                                              "syscon";
 377                                 reg = <0x30360000 0x10000>;
 378                         };
 379
 380                         snvs: snvs@30370000 {
 381                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 382                                 reg = <0x30370000 0x10000>;
 383
 384                                 snvs_rtc: snvs-rtc-lp {
 385                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 386                                         regmap =<&snvs>;
 387                                         offset = <0x34>;
 388                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 389                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 390                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 391                                         clock-names = "snvs-rtc";
 392                                 };
 393
 394                                 snvs_pwrkey: snvs-powerkey {
 395                                         compatible = "fsl,sec-v4.0-pwrkey";
 396                                         regmap = <&snvs>;
 397                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 398                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 399                                         clock-names = "snvs-pwrkey";
 400                                         linux,keycode = <KEY_POWER>;
 401                                         wakeup-source;
 402                                         status = "disabled";
 403                                 };
 404                         };
 405
 406                         clk: clock-controller@30380000 {
 407                                 compatible = "fsl,imx8mp-ccm";
 408                                 reg = <0x30380000 0x10000>;
 409                                 #clock-cells = <1>;
 410                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 411                                          <&clk_ext3>, <&clk_ext4>;
 412                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 413                                               "clk_ext3", "clk_ext4";
 414                                 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
 415                                                   <&clk IMX8MP_CLK_A53_CORE>,
 416                                                   <&clk IMX8MP_CLK_NOC>,
 417                                                   <&clk IMX8MP_CLK_NOC_IO>,
 418                                                   <&clk IMX8MP_CLK_GIC>,
 419                                                   <&clk IMX8MP_CLK_AUDIO_AHB>,
 420                                                   <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
 421                                                   <&clk IMX8MP_AUDIO_PLL1>,
 422                                                   <&clk IMX8MP_AUDIO_PLL2>;
 423                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 424                                                          <&clk IMX8MP_ARM_PLL_OUT>,
 425                                                          <&clk IMX8MP_SYS_PLL2_1000M>,
 426                                                          <&clk IMX8MP_SYS_PLL1_800M>,
 427                                                          <&clk IMX8MP_SYS_PLL2_500M>,
 428                                                          <&clk IMX8MP_SYS_PLL1_800M>,
 429                                                          <&clk IMX8MP_SYS_PLL1_800M>;
 430                                 assigned-clock-rates = <0>, <0>,
 431                                                        <1000000000>,
 432                                                        <800000000>,
 433                                                        <500000000>,
 434                                                        <400000000>,
 435                                                        <800000000>,
 436                                                        <393216000>,
 437                                                        <361267200>;
 438                         };
 439
 440                         src: reset-controller@30390000 {
 441                                 compatible = "fsl,imx8mp-src", "syscon";
 442                                 reg = <0x30390000 0x10000>;
 443                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 444                                 #reset-cells = <1>;
 445                         };
 446                 };
 447
 448                 aips2: bus@30400000 {
 449                         compatible = "fsl,aips-bus", "simple-bus";
 450                         reg = <0x30400000 0x400000>;
 451                         #address-cells = <1>;
 452                         #size-cells = <1>;
 453                         ranges;
 454
 455                         pwm1: pwm@30660000 {
 456                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 457                                 reg = <0x30660000 0x10000>;
 458                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 459                                 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
 460                                          <&clk IMX8MP_CLK_PWM1_ROOT>;
 461                                 clock-names = "ipg", "per";
 462                                 #pwm-cells = <2>;
 463                                 status = "disabled";
 464                         };
 465
 466                         pwm2: pwm@30670000 {
 467                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 468                                 reg = <0x30670000 0x10000>;
 469                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 470                                 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
 471                                          <&clk IMX8MP_CLK_PWM2_ROOT>;
 472                                 clock-names = "ipg", "per";
 473                                 #pwm-cells = <2>;
 474                                 status = "disabled";
 475                         };
 476
 477                         pwm3: pwm@30680000 {
 478                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 479                                 reg = <0x30680000 0x10000>;
 480                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 481                                 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
 482                                          <&clk IMX8MP_CLK_PWM3_ROOT>;
 483                                 clock-names = "ipg", "per";
 484                                 #pwm-cells = <2>;
 485                                 status = "disabled";
 486                         };
 487
 488                         pwm4: pwm@30690000 {
 489                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 490                                 reg = <0x30690000 0x10000>;
 491                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 492                                 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
 493                                          <&clk IMX8MP_CLK_PWM4_ROOT>;
 494                                 clock-names = "ipg", "per";
 495                                 #pwm-cells = <2>;
 496                                 status = "disabled";
 497                         };
 498
 499                         system_counter: timer@306a0000 {
 500                                 compatible = "nxp,sysctr-timer";
 501                                 reg = <0x306a0000 0x20000>;
 502                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 503                                 clocks = <&osc_24m>;
 504                                 clock-names = "per";
 505                         };
 506                 };
 507
 508                 aips3: bus@30800000 {
 509                         compatible = "fsl,aips-bus", "simple-bus";
 510                         reg = <0x30800000 0x400000>;
 511                         #address-cells = <1>;
 512                         #size-cells = <1>;
 513                         ranges;
 514
 515                         ecspi1: spi@30820000 {
 516                                 #address-cells = <1>;
 517                                 #size-cells = <0>;
 518                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 519                                 reg = <0x30820000 0x10000>;
 520                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 521                                 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
 522                                          <&clk IMX8MP_CLK_ECSPI1_ROOT>;
 523                                 clock-names = "ipg", "per";
 524                                 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 525                                 dma-names = "rx", "tx";
 526                                 status = "disabled";
 527                         };
 528
 529                         ecspi2: spi@30830000 {
 530                                 #address-cells = <1>;
 531                                 #size-cells = <0>;
 532                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 533                                 reg = <0x30830000 0x10000>;
 534                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 535                                 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
 536                                          <&clk IMX8MP_CLK_ECSPI2_ROOT>;
 537                                 clock-names = "ipg", "per";
 538                                 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 539                                 dma-names = "rx", "tx";
 540                                 status = "disabled";
 541                         };
 542
 543                         ecspi3: spi@30840000 {
 544                                 #address-cells = <1>;
 545                                 #size-cells = <0>;
 546                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 547                                 reg = <0x30840000 0x10000>;
 548                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 549                                 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
 550                                          <&clk IMX8MP_CLK_ECSPI3_ROOT>;
 551                                 clock-names = "ipg", "per";
 552                                 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 553                                 dma-names = "rx", "tx";
 554                                 status = "disabled";
 555                         };
 556
 557                         uart1: serial@30860000 {
 558                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 559                                 reg = <0x30860000 0x10000>;
 560                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 561                                 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
 562                                          <&clk IMX8MP_CLK_UART1_ROOT>;
 563                                 clock-names = "ipg", "per";
 564                                 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
 565                                 dma-names = "rx", "tx";
 566                                 status = "disabled";
 567                         };
 568
 569                         uart3: serial@30880000 {
 570                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 571                                 reg = <0x30880000 0x10000>;
 572                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 573                                 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
 574                                          <&clk IMX8MP_CLK_UART3_ROOT>;
 575                                 clock-names = "ipg", "per";
 576                                 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
 577                                 dma-names = "rx", "tx";
 578                                 status = "disabled";
 579                         };
 580
 581                         uart2: serial@30890000 {
 582                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 583                                 reg = <0x30890000 0x10000>;
 584                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 585                                 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
 586                                          <&clk IMX8MP_CLK_UART2_ROOT>;
 587                                 clock-names = "ipg", "per";
 588                                 status = "disabled";
 589                         };
 590
 591                         flexcan1: can@308c0000 {
 592                                 compatible = "fsl,imx8mp-flexcan";
 593                                 reg = <0x308c0000 0x10000>;
 594                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 595                                 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
 596                                          <&clk IMX8MP_CLK_CAN1_ROOT>;
 597                                 clock-names = "ipg", "per";
 598                                 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
 599                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
 600                                 assigned-clock-rates = <40000000>;
 601                                 fsl,clk-source = /bits/ 8 <0>;
 602                                 fsl,stop-mode = <&gpr 0x10 4>;
 603                                 status = "disabled";
 604                         };
 605
 606                         flexcan2: can@308d0000 {
 607                                 compatible = "fsl,imx8mp-flexcan";
 608                                 reg = <0x308d0000 0x10000>;
 609                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 610                                 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
 611                                          <&clk IMX8MP_CLK_CAN2_ROOT>;
 612                                 clock-names = "ipg", "per";
 613                                 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
 614                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
 615                                 assigned-clock-rates = <40000000>;
 616                                 fsl,clk-source = /bits/ 8 <0>;
 617                                 fsl,stop-mode = <&gpr 0x10 5>;
 618                                 status = "disabled";
 619                         };
 620
 621                         crypto: crypto@30900000 {
 622                                 compatible = "fsl,sec-v4.0";
 623                                 #address-cells = <1>;
 624                                 #size-cells = <1>;
 625                                 reg = <0x30900000 0x40000>;
 626                                 ranges = <0 0x30900000 0x40000>;
 627                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 628                                 clocks = <&clk IMX8MP_CLK_AHB>,
 629                                          <&clk IMX8MP_CLK_IPG_ROOT>;
 630                                 clock-names = "aclk", "ipg";
 631
 632                                 sec_jr0: jr@1000 {
 633                                         compatible = "fsl,sec-v4.0-job-ring";
 634                                         reg = <0x1000 0x1000>;
 635                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 636                                 };
 637
 638                                 sec_jr1: jr@2000 {
 639                                         compatible = "fsl,sec-v4.0-job-ring";
 640                                         reg = <0x2000 0x1000>;
 641                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 642                                 };
 643
 644                                 sec_jr2: jr@3000 {
 645                                         compatible = "fsl,sec-v4.0-job-ring";
 646                                         reg = <0x3000 0x1000>;
 647                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 648                                 };
 649                         };
 650
 651                         i2c1: i2c@30a20000 {
 652                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 653                                 #address-cells = <1>;
 654                                 #size-cells = <0>;
 655                                 reg = <0x30a20000 0x10000>;
 656                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 657                                 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
 658                                 status = "disabled";
 659                         };
 660
 661                         i2c2: i2c@30a30000 {
 662                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 663                                 #address-cells = <1>;
 664                                 #size-cells = <0>;
 665                                 reg = <0x30a30000 0x10000>;
 666                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 667                                 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
 668                                 status = "disabled";
 669                         };
 670
 671                         i2c3: i2c@30a40000 {
 672                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 673                                 #address-cells = <1>;
 674                                 #size-cells = <0>;
 675                                 reg = <0x30a40000 0x10000>;
 676                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 677                                 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
 678                                 status = "disabled";
 679                         };
 680
 681                         i2c4: i2c@30a50000 {
 682                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 683                                 #address-cells = <1>;
 684                                 #size-cells = <0>;
 685                                 reg = <0x30a50000 0x10000>;
 686                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 687                                 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
 688                                 status = "disabled";
 689                         };
 690
 691                         uart4: serial@30a60000 {
 692                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 693                                 reg = <0x30a60000 0x10000>;
 694                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 695                                 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
 696                                          <&clk IMX8MP_CLK_UART4_ROOT>;
 697                                 clock-names = "ipg", "per";
 698                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
 699                                 dma-names = "rx", "tx";
 700                                 status = "disabled";
 701                         };
 702
 703                         mu: mailbox@30aa0000 {
 704                                 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
 705                                 reg = <0x30aa0000 0x10000>;
 706                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 707                                 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
 708                                 #mbox-cells = <2>;
 709                         };
 710
 711                         mu2: mailbox@30e60000 {
 712                                 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
 713                                 reg = <0x30e60000 0x10000>;
 714                                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 715                                 #mbox-cells = <2>;
 716                                 status = "disabled";
 717                         };
 718
 719                         i2c5: i2c@30ad0000 {
 720                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 721                                 #address-cells = <1>;
 722                                 #size-cells = <0>;
 723                                 reg = <0x30ad0000 0x10000>;
 724                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 725                                 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
 726                                 status = "disabled";
 727                         };
 728
 729                         i2c6: i2c@30ae0000 {
 730                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 731                                 #address-cells = <1>;
 732                                 #size-cells = <0>;
 733                                 reg = <0x30ae0000 0x10000>;
 734                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 735                                 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
 736                                 status = "disabled";
 737                         };
 738
 739                         usdhc1: mmc@30b40000 {
 740                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
 741                                 reg = <0x30b40000 0x10000>;
 742                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 743                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 744                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 745                                          <&clk IMX8MP_CLK_USDHC1_ROOT>;
 746                                 clock-names = "ipg", "ahb", "per";
 747                                 fsl,tuning-start-tap = <20>;
 748                                 fsl,tuning-step= <2>;
 749                                 bus-width = <4>;
 750                                 status = "disabled";
 751                         };
 752
 753                         usdhc2: mmc@30b50000 {
 754                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
 755                                 reg = <0x30b50000 0x10000>;
 756                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 757                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 758                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 759                                          <&clk IMX8MP_CLK_USDHC2_ROOT>;
 760                                 clock-names = "ipg", "ahb", "per";
 761                                 fsl,tuning-start-tap = <20>;
 762                                 fsl,tuning-step= <2>;
 763                                 bus-width = <4>;
 764                                 status = "disabled";
 765                         };
 766
 767                         usdhc3: mmc@30b60000 {
 768                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
 769                                 reg = <0x30b60000 0x10000>;
 770                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 771                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 772                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 773                                          <&clk IMX8MP_CLK_USDHC3_ROOT>;
 774                                 clock-names = "ipg", "ahb", "per";
 775                                 fsl,tuning-start-tap = <20>;
 776                                 fsl,tuning-step= <2>;
 777                                 bus-width = <4>;
 778                                 status = "disabled";
 779                         };
 780
 781                         flexspi: spi@30bb0000 {
 782                                 compatible = "nxp,imx8mp-fspi";
 783                                 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
 784                                 reg-names = "fspi_base", "fspi_mmap";
 785                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 786                                 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
 787                                          <&clk IMX8MP_CLK_QSPI_ROOT>;
 788                                 clock-names = "fspi", "fspi_en";
 789                                 assigned-clock-rates = <80000000>;
 790                                 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
 791                                 #address-cells = <1>;
 792                                 #size-cells = <0>;
 793                                 status = "disabled";
 794                         };
 795
 796                         sdma1: dma-controller@30bd0000 {
 797                                 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
 798                                 reg = <0x30bd0000 0x10000>;
 799                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 800                                 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
 801                                          <&clk IMX8MP_CLK_AHB>;
 802                                 clock-names = "ipg", "ahb";
 803                                 #dma-cells = <3>;
 804                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 805                         };
 806
 807                         fec: ethernet@30be0000 {
 808                                 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 809                                 reg = <0x30be0000 0x10000>;
 810                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 811                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 812                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 813                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 814                                 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
 815                                          <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
 816                                          <&clk IMX8MP_CLK_ENET_TIMER>,
 817                                          <&clk IMX8MP_CLK_ENET_REF>,
 818                                          <&clk IMX8MP_CLK_ENET_PHY_REF>;
 819                                 clock-names = "ipg", "ahb", "ptp",
 820                                               "enet_clk_ref", "enet_out";
 821                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
 822                                                   <&clk IMX8MP_CLK_ENET_TIMER>,
 823                                                   <&clk IMX8MP_CLK_ENET_REF>,
 824                                                   <&clk IMX8MP_CLK_ENET_PHY_REF>;
 825                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
 826                                                          <&clk IMX8MP_SYS_PLL2_100M>,
 827                                                          <&clk IMX8MP_SYS_PLL2_125M>,
 828                                                          <&clk IMX8MP_SYS_PLL2_50M>;
 829                                 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
 830                                 fsl,num-tx-queues = <3>;
 831                                 fsl,num-rx-queues = <3>;
 832                                 nvmem-cells = <&eth_mac1>;
 833                                 nvmem-cell-names = "mac-address";
 834                                 fsl,stop-mode = <&gpr 0x10 3>;
 835                                 nvmem_macaddr_swap;
 836                                 status = "disabled";
 837                         };
 838
 839                         eqos: ethernet@30bf0000 {
 840                                 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
 841                                 reg = <0x30bf0000 0x10000>;
 842                                 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 843                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 844                                 interrupt-names = "macirq", "eth_wake_irq";
 845                                 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
 846                                          <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
 847                                          <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
 848                                          <&clk IMX8MP_CLK_ENET_QOS>;
 849                                 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
 850                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
 851                                                   <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
 852                                                   <&clk IMX8MP_CLK_ENET_QOS>;
 853                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
 854                                                          <&clk IMX8MP_SYS_PLL2_100M>,
 855                                                          <&clk IMX8MP_SYS_PLL2_125M>;
 856                                 assigned-clock-rates = <0>, <100000000>, <125000000>;
 857                                 intf_mode = <&gpr 0x4>;
 858                                 status = "disabled";
 859                         };
 860                 };
 861
 862                 gic: interrupt-controller@38800000 {
 863                         compatible = "arm,gic-v3";
 864                         reg = <0x38800000 0x10000>,
 865                               <0x38880000 0xc0000>;
 866                         #interrupt-cells = <3>;
 867                         interrupt-controller;
 868                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 869                         interrupt-parent = <&gic>;
 870                 };
 871
 872                 ddr-pmu@3d800000 {
 873                         compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
 874                         reg = <0x3d800000 0x400000>;
 875                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 876                 };
 877
 878                 usb3_phy0: usb-phy@381f0040 {
 879                         compatible = "fsl,imx8mp-usb-phy";
 880                         reg = <0x381f0040 0x40>;
 881                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
 882                         clock-names = "phy";
 883                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
 884                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
 885                         #phy-cells = <0>;
 886                         status = "disabled";
 887                 };
 888
 889                 usb3_0: usb@32f10100 {
 890                         compatible = "fsl,imx8mp-dwc3";
 891                         reg = <0x32f10100 0x8>;
 892                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
 893                                  <&clk IMX8MP_CLK_USB_ROOT>;
 894                         clock-names = "hsio", "suspend";
 895                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 896                         #address-cells = <1>;
 897                         #size-cells = <1>;
 898                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
 899                         ranges;
 900                         status = "disabled";
 901
 902                         usb_dwc3_0: usb@38100000 {
 903                                 compatible = "snps,dwc3";
 904                                 reg = <0x38100000 0x10000>;
 905                                 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
 906                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
 907                                          <&clk IMX8MP_CLK_USB_ROOT>;
 908                                 clock-names = "bus_early", "ref", "suspend";
 909                                 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
 910                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 911                                 assigned-clock-rates = <500000000>;
 912                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 913                                 phys = <&usb3_phy0>, <&usb3_phy0>;
 914                                 phy-names = "usb2-phy", "usb3-phy";
 915                                 snps,dis-u2-freeclk-exists-quirk;
 916                         };
 917
 918                 };
 919
 920                 usb3_phy1: usb-phy@382f0040 {
 921                         compatible = "fsl,imx8mp-usb-phy";
 922                         reg = <0x382f0040 0x40>;
 923                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
 924                         clock-names = "phy";
 925                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
 926                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
 927                         #phy-cells = <0>;
 928                 };
 929
 930                 usb3_1: usb@32f10108 {
 931                         compatible = "fsl,imx8mp-dwc3";
 932                         reg = <0x32f10108 0x8>;
 933                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
 934                                  <&clk IMX8MP_CLK_USB_ROOT>;
 935                         clock-names = "hsio", "suspend";
 936                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 937                         #address-cells = <1>;
 938                         #size-cells = <1>;
 939                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
 940                         ranges;
 941                         status = "disabled";
 942
 943                         usb_dwc3_1: usb@38200000 {
 944                                 compatible = "snps,dwc3";
 945                                 reg = <0x38200000 0x10000>;
 946                                 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
 947                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
 948                                          <&clk IMX8MP_CLK_USB_ROOT>;
 949                                 clock-names = "bus_early", "ref", "suspend";
 950                                 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
 951                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 952                                 assigned-clock-rates = <500000000>;
 953                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 954                                 phys = <&usb3_phy1>, <&usb3_phy1>;
 955                                 phy-names = "usb2-phy", "usb3-phy";
 956                                 snps,dis-u2-freeclk-exists-quirk;
 957                         };
 958                 };
 959
 960                 dsp: dsp@3b6e8000 {
 961                         compatible = "fsl,imx8mp-dsp";
 962                         reg = <0x3b6e8000 0x88000>;
 963                         mbox-names = "txdb0", "txdb1",
 964                                 "rxdb0", "rxdb1";
 965                         mboxes = <&mu2 2 0>, <&mu2 2 1>,
 966                                 <&mu2 3 0>, <&mu2 3 1>;
 967                         memory-region = <&dsp_reserved>;
 968                         status = "disabled";
 969                 };
 970         };
 971 };