arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020 PHYTEC Messtechnik GmbH
   4  * Author: Teresa Remmet <t.remmet@phytec.de>
   5  */
   6
   7 #include <dt-bindings/net/ti-dp83867.h>
   8 #include "imx8mp.dtsi"
   9
  10 / {
  11         model = "PHYTEC phyCORE-i.MX8MP";
  12         compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
  13
  14         aliases {
  15                 rtc0 = &rv3028;
  16                 rtc1 = &snvs_rtc;
  17         };
  18
  19         memory@40000000 {
  20                 device_type = "memory";
  21                 reg = <0x0 0x40000000 0 0x80000000>;
  22         };
  23 };
  24
  25 &A53_0 {
  26         cpu-supply = <&buck2>;
  27 };
  28
  29 &A53_1 {
  30         cpu-supply = <&buck2>;
  31 };
  32
  33 &A53_2 {
  34         cpu-supply = <&buck2>;
  35 };
  36
  37 &A53_3 {
  38         cpu-supply = <&buck2>;
  39 };
  40
  41 /* ethernet 1 */
  42 &fec {
  43         pinctrl-names = "default";
  44         pinctrl-0 = <&pinctrl_fec>;
  45         phy-mode = "rgmii-id";
  46         phy-handle = <&ethphy1>;
  47         fsl,magic-packet;
  48         status = "okay";
  49
  50         mdio {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 ethphy1: ethernet-phy@0 {
  55                         compatible = "ethernet-phy-ieee802.3-c22";
  56                         reg = <0>;
  57                         interrupt-parent = <&gpio1>;
  58                         interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
  59                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  60                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  61                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  62                         ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
  63                         enet-phy-lane-no-swap;
  64                 };
  65         };
  66 };
  67
  68 &flexspi {
  69         pinctrl-names = "default";
  70         pinctrl-0 = <&pinctrl_flexspi0>;
  71         status = "okay";
  72
  73         som_flash: flash@0 {
  74                 compatible = "jedec,spi-nor";
  75                 reg = <0>;
  76                 spi-max-frequency = <80000000>;
  77                 spi-tx-bus-width = <4>;
  78                 spi-rx-bus-width = <4>;
  79         };
  80 };
  81
  82 &i2c1 {
  83         clock-frequency = <400000>;
  84         pinctrl-names = "default", "gpio";
  85         pinctrl-0 = <&pinctrl_i2c1>;
  86         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  87         sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  88         scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  89         status = "okay";
  90
  91         pmic: pmic@25 {
  92                 reg = <0x25>;
  93                 compatible = "nxp,pca9450c";
  94                 pinctrl-names = "default";
  95                 pinctrl-0 = <&pinctrl_pmic>;
  96                 interrupt-parent = <&gpio4>;
  97                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
  98
  99                 regulators {
 100                         buck1: BUCK1 {
 101                                 regulator-compatible = "BUCK1";
 102                                 regulator-min-microvolt = <600000>;
 103                                 regulator-max-microvolt = <2187500>;
 104                                 regulator-boot-on;
 105                                 regulator-always-on;
 106                                 regulator-ramp-delay = <3125>;
 107                         };
 108
 109                         buck2: BUCK2 {
 110                                 regulator-compatible = "BUCK2";
 111                                 regulator-min-microvolt = <600000>;
 112                                 regulator-max-microvolt = <2187500>;
 113                                 regulator-boot-on;
 114                                 regulator-always-on;
 115                                 regulator-ramp-delay = <3125>;
 116                         };
 117
 118                         buck4: BUCK4 {
 119                                 regulator-compatible = "BUCK4";
 120                                 regulator-min-microvolt = <600000>;
 121                                 regulator-max-microvolt = <3400000>;
 122                                 regulator-boot-on;
 123                                 regulator-always-on;
 124                         };
 125
 126                         buck5: BUCK5 {
 127                                 regulator-compatible = "BUCK5";
 128                                 regulator-min-microvolt = <600000>;
 129                                 regulator-max-microvolt = <3400000>;
 130                                 regulator-boot-on;
 131                                 regulator-always-on;
 132                         };
 133
 134                         buck6: BUCK6 {
 135                                 regulator-compatible = "BUCK6";
 136                                 regulator-min-microvolt = <600000>;
 137                                 regulator-max-microvolt = <3400000>;
 138                                 regulator-boot-on;
 139                                 regulator-always-on;
 140                         };
 141
 142                         ldo1: LDO1 {
 143                                 regulator-compatible = "LDO1";
 144                                 regulator-min-microvolt = <1600000>;
 145                                 regulator-max-microvolt = <3300000>;
 146                                 regulator-boot-on;
 147                                 regulator-always-on;
 148                         };
 149
 150                         ldo2: LDO2 {
 151                                 regulator-compatible = "LDO2";
 152                                 regulator-min-microvolt = <800000>;
 153                                 regulator-max-microvolt = <1150000>;
 154                                 regulator-boot-on;
 155                                 regulator-always-on;
 156                         };
 157
 158                         ldo3: LDO3 {
 159                                 regulator-compatible = "LDO3";
 160                                 regulator-min-microvolt = <800000>;
 161                                 regulator-max-microvolt = <3300000>;
 162                                 regulator-boot-on;
 163                                 regulator-always-on;
 164                         };
 165
 166                         ldo4: LDO4 {
 167                                 regulator-compatible = "LDO4";
 168                                 regulator-min-microvolt = <800000>;
 169                                 regulator-max-microvolt = <3300000>;
 170                                 regulator-boot-on;
 171                                 regulator-always-on;
 172                         };
 173
 174                         ldo5: LDO5 {
 175                                 regulator-compatible = "LDO5";
 176                                 regulator-min-microvolt = <1800000>;
 177                                 regulator-max-microvolt = <3300000>;
 178                         };
 179                 };
 180         };
 181
 182         eeprom@51 {
 183                 compatible = "atmel,24c32";
 184                 reg = <0x51>;
 185                 pagesize = <32>;
 186         };
 187
 188         rv3028: rtc@52 {
 189                 compatible = "microcrystal,rv3028";
 190                 reg = <0x52>;
 191                 trickle-resistor-ohms = <3000>;
 192         };
 193 };
 194
 195 /* eMMC */
 196 &usdhc3 {
 197         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 198         pinctrl-0 = <&pinctrl_usdhc3>;
 199         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 200         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 201         bus-width = <8>;
 202         non-removable;
 203         status = "okay";
 204 };
 205
 206 &wdog1 {
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_wdog>;
 209         fsl,ext-reset-output;
 210         status = "okay";
 211 };
 212
 213 &iomuxc {
 214         pinctrl_fec: fecgrp {
 215                 fsl,pins = <
 216                         MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
 217                         MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x3
 218                         MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x91
 219                         MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x91
 220                         MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x91
 221                         MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x91
 222                         MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x91
 223                         MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x91
 224                         MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x1f
 225                         MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x1f
 226                         MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x1f
 227                         MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x1f
 228                         MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x1f
 229                         MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x1f
 230                         MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15             0x11
 231                 >;
 232         };
 233
 234         pinctrl_flexspi0: flexspi0grp {
 235                 fsl,pins = <
 236                         MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2
 237                         MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82
 238                         MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82
 239                         MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82
 240                         MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82
 241                         MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82
 242                 >;
 243         };
 244
 245         pinctrl_i2c1: i2c1grp {
 246                 fsl,pins = <
 247                         MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL         0x400001c3
 248                         MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA         0x400001c3
 249                 >;
 250         };
 251
 252         pinctrl_i2c1_gpio: i2c1gpiogrp {
 253                 fsl,pins = <
 254                         MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14       0x1e3
 255                         MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15       0x1e3
 256                 >;
 257         };
 258
 259         pinctrl_pmic: pmicirqgrp {
 260                 fsl,pins = <
 261                         MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18      0x141
 262                 >;
 263         };
 264
 265         pinctrl_usdhc3: usdhc3grp {
 266                 fsl,pins = <
 267                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x190
 268                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d0
 269                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d0
 270                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d0
 271                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d0
 272                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d0
 273                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d0
 274                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d0
 275                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d0
 276                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d0
 277                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x190
 278                 >;
 279         };
 280
 281         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 282                 fsl,pins = <
 283                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x194
 284                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d4
 285                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d4
 286                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d4
 287                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d4
 288                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d4
 289                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d4
 290                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d4
 291                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d4
 292                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d4
 293                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x194
 294                 >;
 295         };
 296
 297         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 298                 fsl,pins = <
 299                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x196
 300                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d6
 301                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d6
 302                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d6
 303                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d6
 304                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d6
 305                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d6
 306                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d6
 307                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d6
 308                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d6
 309                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x196
 310                 >;
 311         };
 312
 313         pinctrl_wdog: wdoggrp {
 314                 fsl,pins = <
 315                         MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B   0xc6
 316                 >;
 317         };
 318 };