arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2021 Gateworks Corporation
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/linux-event-codes.h>
  10 #include <dt-bindings/leds/common.h>
  11 #include <dt-bindings/net/ti-dp83867.h>
  12
  13 #include "imx8mn.dtsi"
  14
  15 / {
  16         model = "Gateworks Venice GW7902 i.MX8MN board";
  17         compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
  18
  19         aliases {
  20                 usb0 = &usbotg1;
  21         };
  22
  23         chosen {
  24                 stdout-path = &uart2;
  25         };
  26
  27         memory@40000000 {
  28                 device_type = "memory";
  29                 reg = <0x0 0x40000000 0 0x80000000>;
  30         };
  31
  32         can20m: can20m {
  33                 compatible = "fixed-clock";
  34                 #clock-cells = <0>;
  35                 clock-frequency = <20000000>;
  36                 clock-output-names = "can20m";
  37         };
  38
  39         gpio-keys {
  40                 compatible = "gpio-keys";
  41
  42                 user-pb {
  43                         label = "user_pb";
  44                         gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
  45                         linux,code = <BTN_0>;
  46                 };
  47
  48                 user-pb1x {
  49                         label = "user_pb1x";
  50                         linux,code = <BTN_1>;
  51                         interrupt-parent = <&gsc>;
  52                         interrupts = <0>;
  53                 };
  54
  55                 key-erased {
  56                         label = "key_erased";
  57                         linux,code = <BTN_2>;
  58                         interrupt-parent = <&gsc>;
  59                         interrupts = <1>;
  60                 };
  61
  62                 eeprom-wp {
  63                         label = "eeprom_wp";
  64                         linux,code = <BTN_3>;
  65                         interrupt-parent = <&gsc>;
  66                         interrupts = <2>;
  67                 };
  68
  69                 tamper {
  70                         label = "tamper";
  71                         linux,code = <BTN_4>;
  72                         interrupt-parent = <&gsc>;
  73                         interrupts = <5>;
  74                 };
  75
  76                 switch-hold {
  77                         label = "switch_hold";
  78                         linux,code = <BTN_5>;
  79                         interrupt-parent = <&gsc>;
  80                         interrupts = <7>;
  81                 };
  82         };
  83
  84         led-controller {
  85                 compatible = "gpio-leds";
  86                 pinctrl-names = "default";
  87                 pinctrl-0 = <&pinctrl_gpio_leds>;
  88
  89                 led-0 {
  90                         function = LED_FUNCTION_STATUS;
  91                         color = <LED_COLOR_ID_GREEN>;
  92                         label = "panel1";
  93                         gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
  94                         default-state = "off";
  95                 };
  96
  97                 led-1 {
  98                         function = LED_FUNCTION_STATUS;
  99                         color = <LED_COLOR_ID_GREEN>;
 100                         label = "panel2";
 101                         gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 102                         default-state = "off";
 103                 };
 104
 105                 led-2 {
 106                         function = LED_FUNCTION_STATUS;
 107                         color = <LED_COLOR_ID_GREEN>;
 108                         label = "panel3";
 109                         gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
 110                         default-state = "off";
 111                 };
 112
 113                 led-3 {
 114                         function = LED_FUNCTION_STATUS;
 115                         color = <LED_COLOR_ID_GREEN>;
 116                         label = "panel4";
 117                         gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
 118                         default-state = "off";
 119                 };
 120
 121                 led-4 {
 122                         function = LED_FUNCTION_STATUS;
 123                         color = <LED_COLOR_ID_GREEN>;
 124                         label = "panel5";
 125                         gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
 126                         default-state = "off";
 127                 };
 128         };
 129
 130         pps {
 131                 compatible = "pps-gpio";
 132                 pinctrl-names = "default";
 133                 pinctrl-0 = <&pinctrl_pps>;
 134                 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
 135                 status = "okay";
 136         };
 137
 138         reg_3p3v: regulator-3p3v {
 139                 compatible = "regulator-fixed";
 140                 regulator-name = "3P3V";
 141                 regulator-min-microvolt = <3300000>;
 142                 regulator-max-microvolt = <3300000>;
 143                 regulator-always-on;
 144         };
 145
 146         reg_usb1_vbus: regulator-usb1 {
 147                 compatible = "regulator-fixed";
 148                 pinctrl-names = "default";
 149                 pinctrl-0 = <&pinctrl_reg_usb1>;
 150                 regulator-name = "usb_usb1_vbus";
 151                 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
 152                 enable-active-high;
 153                 regulator-min-microvolt = <5000000>;
 154                 regulator-max-microvolt = <5000000>;
 155         };
 156
 157         reg_wifi: regulator-wifi {
 158                 compatible = "regulator-fixed";
 159                 pinctrl-names = "default";
 160                 pinctrl-0 = <&pinctrl_reg_wl>;
 161                 regulator-name = "wifi";
 162                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
 163                 enable-active-high;
 164                 startup-delay-us = <100>;
 165                 regulator-min-microvolt = <3300000>;
 166                 regulator-max-microvolt = <3300000>;
 167         };
 168 };
 169
 170 &A53_0 {
 171         cpu-supply = <&buck2>;
 172 };
 173
 174 &A53_1 {
 175         cpu-supply = <&buck2>;
 176 };
 177
 178 &A53_2 {
 179         cpu-supply = <&buck2>;
 180 };
 181
 182 &A53_3 {
 183         cpu-supply = <&buck2>;
 184 };
 185
 186 &ddrc {
 187         operating-points-v2 = <&ddrc_opp_table>;
 188
 189         ddrc_opp_table: opp-table {
 190                 compatible = "operating-points-v2";
 191
 192                 opp-25M {
 193                         opp-hz = /bits/ 64 <25000000>;
 194                 };
 195
 196                 opp-100M {
 197                         opp-hz = /bits/ 64 <100000000>;
 198                 };
 199
 200                 opp-750M {
 201                         opp-hz = /bits/ 64 <750000000>;
 202                 };
 203         };
 204 };
 205
 206 &ecspi1 {
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_spi1>;
 209         cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 210         status = "okay";
 211
 212         can@0 {
 213                 compatible = "microchip,mcp2515";
 214                 reg = <0>;
 215                 clocks = <&can20m>;
 216                 oscillator-frequency = <20000000>;
 217                 interrupt-parent = <&gpio2>;
 218                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 219                 spi-max-frequency = <10000000>;
 220         };
 221 };
 222
 223 /* off-board header */
 224 &ecspi2 {
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_spi2>;
 227         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 228         status = "okay";
 229 };
 230
 231 &fec1 {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_fec1>;
 234         phy-mode = "rgmii-id";
 235         phy-handle = <&ethphy0>;
 236         local-mac-address = [00 00 00 00 00 00];
 237         status = "okay";
 238
 239         mdio {
 240                 #address-cells = <1>;
 241                 #size-cells = <0>;
 242
 243                 ethphy0: ethernet-phy@0 {
 244                         compatible = "ethernet-phy-ieee802.3-c22";
 245                         reg = <0>;
 246                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 247                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 248                         tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 249                         rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 250                 };
 251         };
 252 };
 253
 254 &i2c1 {
 255         clock-frequency = <100000>;
 256         pinctrl-names = "default";
 257         pinctrl-0 = <&pinctrl_i2c1>;
 258         status = "okay";
 259
 260         gsc: gsc@20 {
 261                 compatible = "gw,gsc";
 262                 reg = <0x20>;
 263                 pinctrl-0 = <&pinctrl_gsc>;
 264                 interrupt-parent = <&gpio2>;
 265                 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
 266                 interrupt-controller;
 267                 #interrupt-cells = <1>;
 268
 269                 adc {
 270                         compatible = "gw,gsc-adc";
 271                         #address-cells = <1>;
 272                         #size-cells = <0>;
 273
 274                         channel@6 {
 275                                 gw,mode = <0>;
 276                                 reg = <0x06>;
 277                                 label = "temp";
 278                         };
 279
 280                         channel@8 {
 281                                 gw,mode = <1>;
 282                                 reg = <0x08>;
 283                                 label = "vdd_bat";
 284                         };
 285
 286                         channel@82 {
 287                                 gw,mode = <2>;
 288                                 reg = <0x82>;
 289                                 label = "vin";
 290                                 gw,voltage-divider-ohms = <22100 1000>;
 291                                 gw,voltage-offset-microvolt = <700000>;
 292                         };
 293
 294                         channel@84 {
 295                                 gw,mode = <2>;
 296                                 reg = <0x84>;
 297                                 label = "vin_4p0";
 298                                 gw,voltage-divider-ohms = <10000 10000>;
 299                         };
 300
 301                         channel@86 {
 302                                 gw,mode = <2>;
 303                                 reg = <0x86>;
 304                                 label = "vdd_3p3";
 305                                 gw,voltage-divider-ohms = <10000 10000>;
 306                         };
 307
 308                         channel@88 {
 309                                 gw,mode = <2>;
 310                                 reg = <0x88>;
 311                                 label = "vdd_0p9";
 312                         };
 313
 314                         channel@8c {
 315                                 gw,mode = <2>;
 316                                 reg = <0x8c>;
 317                                 label = "vdd_soc";
 318                         };
 319
 320                         channel@8e {
 321                                 gw,mode = <2>;
 322                                 reg = <0x8e>;
 323                                 label = "vdd_arm";
 324                         };
 325
 326                         channel@90 {
 327                                 gw,mode = <2>;
 328                                 reg = <0x90>;
 329                                 label = "vdd_1p8";
 330                         };
 331
 332                         channel@92 {
 333                                 gw,mode = <2>;
 334                                 reg = <0x92>;
 335                                 label = "vdd_dram";
 336                         };
 337
 338                         channel@98 {
 339                                 gw,mode = <2>;
 340                                 reg = <0x98>;
 341                                 label = "vdd_1p0";
 342                         };
 343
 344                         channel@9a {
 345                                 gw,mode = <2>;
 346                                 reg = <0x9a>;
 347                                 label = "vdd_2p5";
 348                                 gw,voltage-divider-ohms = <10000 10000>;
 349                         };
 350
 351                         channel@a2 {
 352                                 gw,mode = <2>;
 353                                 reg = <0xa2>;
 354                                 label = "vdd_gsc";
 355                                 gw,voltage-divider-ohms = <10000 10000>;
 356                         };
 357                 };
 358         };
 359
 360         gpio: gpio@23 {
 361                 compatible = "nxp,pca9555";
 362                 reg = <0x23>;
 363                 gpio-controller;
 364                 #gpio-cells = <2>;
 365                 interrupt-parent = <&gsc>;
 366                 interrupts = <4>;
 367         };
 368
 369         pmic@4b {
 370                 compatible = "rohm,bd71847";
 371                 reg = <0x4b>;
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&pinctrl_pmic>;
 374                 interrupt-parent = <&gpio3>;
 375                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 376                 rohm,reset-snvs-powered;
 377                 #clock-cells = <0>;
 378                 clocks = <&osc_32k 0>;
 379                 clock-output-names = "clk-32k-out";
 380
 381                 regulators {
 382                         /* vdd_soc: 0.805-0.900V (typ=0.8V) */
 383                         BUCK1 {
 384                                 regulator-name = "buck1";
 385                                 regulator-min-microvolt = <700000>;
 386                                 regulator-max-microvolt = <1300000>;
 387                                 regulator-boot-on;
 388                                 regulator-always-on;
 389                                 regulator-ramp-delay = <1250>;
 390                         };
 391
 392                         /* vdd_arm: 0.805-1.0V (typ=0.9V) */
 393                         buck2: BUCK2 {
 394                                 regulator-name = "buck2";
 395                                 regulator-min-microvolt = <700000>;
 396                                 regulator-max-microvolt = <1300000>;
 397                                 regulator-boot-on;
 398                                 regulator-always-on;
 399                                 regulator-ramp-delay = <1250>;
 400                                 rohm,dvs-run-voltage = <1000000>;
 401                                 rohm,dvs-idle-voltage = <900000>;
 402                         };
 403
 404                         /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
 405                         BUCK3 {
 406                                 regulator-name = "buck3";
 407                                 regulator-min-microvolt = <700000>;
 408                                 regulator-max-microvolt = <1350000>;
 409                                 regulator-boot-on;
 410                                 regulator-always-on;
 411                         };
 412
 413                         /* vdd_3p3 */
 414                         BUCK4 {
 415                                 regulator-name = "buck4";
 416                                 regulator-min-microvolt = <3000000>;
 417                                 regulator-max-microvolt = <3300000>;
 418                                 regulator-boot-on;
 419                                 regulator-always-on;
 420                         };
 421
 422                         /* vdd_1p8 */
 423                         BUCK5 {
 424                                 regulator-name = "buck5";
 425                                 regulator-min-microvolt = <1605000>;
 426                                 regulator-max-microvolt = <1995000>;
 427                                 regulator-boot-on;
 428                                 regulator-always-on;
 429                         };
 430
 431                         /* vdd_dram */
 432                         BUCK6 {
 433                                 regulator-name = "buck6";
 434                                 regulator-min-microvolt = <800000>;
 435                                 regulator-max-microvolt = <1400000>;
 436                                 regulator-boot-on;
 437                                 regulator-always-on;
 438                         };
 439
 440                         /* nvcc_snvs_1p8 */
 441                         LDO1 {
 442                                 regulator-name = "ldo1";
 443                                 regulator-min-microvolt = <1600000>;
 444                                 regulator-max-microvolt = <1900000>;
 445                                 regulator-boot-on;
 446                                 regulator-always-on;
 447                         };
 448
 449                         /* vdd_snvs_0p8 */
 450                         LDO2 {
 451                                 regulator-name = "ldo2";
 452                                 regulator-min-microvolt = <800000>;
 453                                 regulator-max-microvolt = <900000>;
 454                                 regulator-boot-on;
 455                                 regulator-always-on;
 456                         };
 457
 458                         /* vdda_1p8 */
 459                         LDO3 {
 460                                 regulator-name = "ldo3";
 461                                 regulator-min-microvolt = <1800000>;
 462                                 regulator-max-microvolt = <3300000>;
 463                                 regulator-boot-on;
 464                                 regulator-always-on;
 465                         };
 466
 467                         LDO4 {
 468                                 regulator-name = "ldo4";
 469                                 regulator-min-microvolt = <900000>;
 470                                 regulator-max-microvolt = <1800000>;
 471                                 regulator-boot-on;
 472                                 regulator-always-on;
 473                         };
 474
 475                         LDO6 {
 476                                 regulator-name = "ldo6";
 477                                 regulator-min-microvolt = <900000>;
 478                                 regulator-max-microvolt = <1800000>;
 479                                 regulator-boot-on;
 480                                 regulator-always-on;
 481                         };
 482                 };
 483         };
 484
 485         eeprom@50 {
 486                 compatible = "atmel,24c02";
 487                 reg = <0x50>;
 488                 pagesize = <16>;
 489         };
 490
 491         eeprom@51 {
 492                 compatible = "atmel,24c02";
 493                 reg = <0x51>;
 494                 pagesize = <16>;
 495         };
 496
 497         eeprom@52 {
 498                 compatible = "atmel,24c02";
 499                 reg = <0x52>;
 500                 pagesize = <16>;
 501         };
 502
 503         eeprom@53 {
 504                 compatible = "atmel,24c02";
 505                 reg = <0x53>;
 506                 pagesize = <16>;
 507         };
 508
 509         rtc@68 {
 510                 compatible = "dallas,ds1672";
 511                 reg = <0x68>;
 512         };
 513 };
 514
 515 &i2c2 {
 516         clock-frequency = <400000>;
 517         pinctrl-names = "default";
 518         pinctrl-0 = <&pinctrl_i2c2>;
 519         status = "okay";
 520
 521         accelerometer@19 {
 522                 compatible = "st,lis2de12";
 523                 pinctrl-names = "default";
 524                 pinctrl-0 = <&pinctrl_accel>;
 525                 reg = <0x19>;
 526                 st,drdy-int-pin = <1>;
 527                 interrupt-parent = <&gpio1>;
 528                 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
 529                 interrupt-names = "INT1";
 530         };
 531 };
 532
 533 /* off-board header */
 534 &i2c3 {
 535         clock-frequency = <400000>;
 536         pinctrl-names = "default";
 537         pinctrl-0 = <&pinctrl_i2c3>;
 538         status = "okay";
 539 };
 540
 541 /* off-board header */
 542 &i2c4 {
 543         clock-frequency = <400000>;
 544         pinctrl-names = "default";
 545         pinctrl-0 = <&pinctrl_i2c4>;
 546         status = "okay";
 547 };
 548
 549 /* off-board header */
 550 &sai3 {
 551         pinctrl-names = "default";
 552         pinctrl-0 = <&pinctrl_sai3>;
 553         assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
 554         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
 555         assigned-clock-rates = <24576000>;
 556         status = "okay";
 557 };
 558
 559 /* RS232/RS485/RS422 selectable */
 560 &uart1 {
 561         pinctrl-names = "default";
 562         pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
 563         status = "okay";
 564 };
 565
 566 /* RS232 console */
 567 &uart2 {
 568         pinctrl-names = "default";
 569         pinctrl-0 = <&pinctrl_uart2>;
 570         status = "okay";
 571 };
 572
 573 /* bluetooth HCI */
 574 &uart3 {
 575         pinctrl-names = "default";
 576         pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
 577         rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 578         cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 579         status = "okay";
 580
 581         bluetooth {
 582                 compatible = "brcm,bcm4330-bt";
 583                 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 584         };
 585 };
 586
 587 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
 588 &uart4 {
 589         pinctrl-names = "default";
 590         pinctrl-0 = <&pinctrl_uart4>;
 591         status = "okay";
 592 };
 593
 594 &usbotg1 {
 595         dr_mode = "host";
 596         vbus-supply = <&reg_usb1_vbus>;
 597         disable-over-current;
 598         status = "okay";
 599 };
 600
 601 /* SDIO WiFi */
 602 &usdhc2 {
 603         pinctrl-names = "default";
 604         pinctrl-0 = <&pinctrl_usdhc2>;
 605         bus-width = <4>;
 606         non-removable;
 607         vmmc-supply = <&reg_wifi>;
 608         status = "okay";
 609 };
 610
 611 /* eMMC */
 612 &usdhc3 {
 613         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 614         pinctrl-0 = <&pinctrl_usdhc3>;
 615         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 616         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 617         bus-width = <8>;
 618         non-removable;
 619         status = "okay";
 620 };
 621
 622 &wdog1 {
 623         pinctrl-names = "default";
 624         pinctrl-0 = <&pinctrl_wdog>;
 625         fsl,ext-reset-output;
 626         status = "okay";
 627 };
 628
 629 &iomuxc {
 630         pinctrl-names = "default";
 631         pinctrl-0 = <&pinctrl_hog>;
 632
 633         pinctrl_hog: hoggrp {
 634                 fsl,pins = <
 635                         MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1       0x40000159 /* M2_GDIS# */
 636                         MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x40000041 /* M2_RST# */
 637                         MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7      0x40000119 /* M2_OFF# */
 638                         MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x40000159 /* M2_WDIS# */
 639                         MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x40000041 /* APP GPIO1 */
 640                         MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27       0x40000041 /* APP GPIO2 */
 641                         MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8        0x40000041 /* UART2_EN# */
 642                         MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28       0x40000041 /* MIPI_GPIO1 */
 643                         MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0x40000041 /* MIPI_GPIO2 */
 644                         MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4         0x40000041 /* MIPI_GPIO3/PWM2 */
 645                         MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3         0x40000041 /* MIPI_GPIO4/PWM3 */
 646                 >;
 647         };
 648
 649         pinctrl_accel: accelgrp {
 650                 fsl,pins = <
 651                         MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x159
 652                 >;
 653         };
 654
 655         pinctrl_fec1: fec1grp {
 656                 fsl,pins = <
 657                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 658                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 659                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 660                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 661                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 662                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 663                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 664                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 665                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 666                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 667                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 668                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 669                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 670                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 671                         MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10              0x19 /* RST# */
 672                         MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x19 /* IRQ# */
 673                         MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN    0x141
 674                         MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT   0x141
 675                 >;
 676         };
 677
 678         pinctrl_gsc: gscgrp {
 679                 fsl,pins = <
 680                         MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6        0x40
 681                 >;
 682         };
 683
 684         pinctrl_i2c1: i2c1grp {
 685                 fsl,pins = <
 686                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 687                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 688                 >;
 689         };
 690
 691         pinctrl_i2c2: i2c2grp {
 692                 fsl,pins = <
 693                         MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 694                         MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 695                 >;
 696         };
 697
 698         pinctrl_i2c3: i2c3grp {
 699                 fsl,pins = <
 700                         MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 701                         MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 702                 >;
 703         };
 704
 705         pinctrl_i2c4: i2c4grp {
 706                 fsl,pins = <
 707                         MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL          0x400001c3
 708                         MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA          0x400001c3
 709                 >;
 710         };
 711
 712         pinctrl_gpio_leds: gpioledgrp {
 713                 fsl,pins = <
 714                         MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21       0x19
 715                         MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23       0x19
 716                         MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22       0x19
 717                         MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20        0x19
 718                         MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25       0x19
 719                 >;
 720         };
 721
 722         pinctrl_pmic: pmicgrp {
 723                 fsl,pins = <
 724                         MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8      0x41
 725                 >;
 726         };
 727
 728         pinctrl_pps: ppsgrp {
 729                 fsl,pins = <
 730                         MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24       0x141 /* PPS */
 731                 >;
 732         };
 733
 734         pinctrl_reg_wl: regwlgrp {
 735                 fsl,pins = <
 736                         MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41 /* WLAN_WLON */
 737                 >;
 738         };
 739
 740         pinctrl_reg_usb1: regusb1grp {
 741                 fsl,pins = <
 742                         MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7        0x41
 743                 >;
 744         };
 745
 746         pinctrl_sai3: sai3grp {
 747                 fsl,pins = <
 748                         MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
 749                         MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
 750                         MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
 751                         MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
 752                         MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
 753                 >;
 754         };
 755
 756         pinctrl_spi1: spi1grp {
 757                 fsl,pins = <
 758                         MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x82
 759                         MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x82
 760                         MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x82
 761                         MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9       0x40
 762                         MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3        0x140 /* CAN_IRQ# */
 763                 >;
 764         };
 765
 766         pinctrl_spi2: spi2grp {
 767                 fsl,pins = <
 768                         MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x82
 769                         MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x82
 770                         MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x82
 771                         MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x40 /* SS0 */
 772                 >;
 773         };
 774
 775         pinctrl_uart1: uart1grp {
 776                 fsl,pins = <
 777                         MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 778                         MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 779                 >;
 780         };
 781
 782         pinctrl_uart1_gpio: uart1gpiogrp {
 783                 fsl,pins = <
 784                         MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26       0x40000110 /* HALF */
 785                         MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25        0x40000110 /* TERM */
 786                         MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23       0x40000110 /* RS485 */
 787                 >;
 788         };
 789
 790         pinctrl_uart2: uart2grp {
 791                 fsl,pins = <
 792                         MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 793                         MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 794                 >;
 795         };
 796
 797         pinctrl_uart3_gpio: uart3_gpiogrp {
 798                 fsl,pins = <
 799                         MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12        0x41 /* BT_EN# */
 800                 >;
 801         };
 802
 803         pinctrl_uart3: uart3grp {
 804                 fsl,pins = <
 805                         MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
 806                         MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
 807                         MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0          0x140 /* CTS */
 808                         MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1          0x140 /* RTS */
 809                 >;
 810         };
 811
 812         pinctrl_uart4: uart4grp {
 813                 fsl,pins = <
 814                         MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX     0x140
 815                         MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140
 816                         MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6       0x141 /* GNSS_GASP */
 817                 >;
 818         };
 819
 820         pinctrl_usdhc2: usdhc2grp {
 821                 fsl,pins = <
 822                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 823                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 824                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 825                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 826                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 827                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 828                 >;
 829         };
 830
 831         pinctrl_usdhc3: usdhc3grp {
 832                 fsl,pins = <
 833                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
 834                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
 835                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
 836                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
 837                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
 838                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
 839                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0
 840                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0
 841                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0
 842                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0
 843                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190
 844                 >;
 845         };
 846
 847         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 848                 fsl,pins = <
 849                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
 850                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
 851                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
 852                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
 853                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
 854                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
 855                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4
 856                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4
 857                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4
 858                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4
 859                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194
 860                 >;
 861         };
 862
 863         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 864                 fsl,pins = <
 865                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
 866                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
 867                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
 868                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
 869                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
 870                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
 871                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6
 872                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6
 873                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6
 874                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6
 875                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196
 876                 >;
 877         };
 878
 879         pinctrl_wdog: wdoggrp {
 880                 fsl,pins = <
 881                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
 882                 >;
 883         };
 884 };