arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2020 Gateworks Corporation
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/linux-event-codes.h>
  10 #include <dt-bindings/leds/common.h>
  11
  12 #include "imx8mm.dtsi"
  13
  14 / {
  15         model = "Gateworks Venice GW7901 i.MX8MM board";
  16         compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
  17
  18         aliases {
  19                 ethernet0 = &fec1;
  20                 ethernet1 = &lan1;
  21                 ethernet2 = &lan2;
  22                 ethernet3 = &lan3;
  23                 ethernet4 = &lan4;
  24                 usb0 = &usbotg1;
  25                 usb1 = &usbotg2;
  26         };
  27
  28         chosen {
  29                 stdout-path = &uart2;
  30         };
  31
  32         memory@40000000 {
  33                 device_type = "memory";
  34                 reg = <0x0 0x40000000 0 0x80000000>;
  35         };
  36
  37         gpio-keys {
  38                 compatible = "gpio-keys";
  39
  40                 user-pb {
  41                         label = "user_pb";
  42                         gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
  43                         linux,code = <BTN_0>;
  44                 };
  45
  46                 user-pb1x {
  47                         label = "user_pb1x";
  48                         linux,code = <BTN_1>;
  49                         interrupt-parent = <&gsc>;
  50                         interrupts = <0>;
  51                 };
  52
  53                 key-erased {
  54                         label = "key_erased";
  55                         linux,code = <BTN_2>;
  56                         interrupt-parent = <&gsc>;
  57                         interrupts = <1>;
  58                 };
  59
  60                 eeprom-wp {
  61                         label = "eeprom_wp";
  62                         linux,code = <BTN_3>;
  63                         interrupt-parent = <&gsc>;
  64                         interrupts = <2>;
  65                 };
  66
  67                 tamper {
  68                         label = "tamper";
  69                         linux,code = <BTN_4>;
  70                         interrupt-parent = <&gsc>;
  71                         interrupts = <5>;
  72                 };
  73
  74                 switch-hold {
  75                         label = "switch_hold";
  76                         linux,code = <BTN_5>;
  77                         interrupt-parent = <&gsc>;
  78                         interrupts = <7>;
  79                 };
  80         };
  81
  82         led-controller {
  83                 compatible = "gpio-leds";
  84
  85                 led-0 {
  86                         function = LED_FUNCTION_STATUS;
  87                         color = <LED_COLOR_ID_RED>;
  88                         label = "led01_red";
  89                         gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
  90                         default-state = "off";
  91                 };
  92
  93                 led-1 {
  94                         function = LED_FUNCTION_STATUS;
  95                         color = <LED_COLOR_ID_GREEN>;
  96                         label = "led01_grn";
  97                         gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
  98                         default-state = "off";
  99                 };
 100
 101                 led-2 {
 102                         function = LED_FUNCTION_STATUS;
 103                         color = <LED_COLOR_ID_RED>;
 104                         label = "led02_red";
 105                         gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
 106                         default-state = "off";
 107                 };
 108
 109                 led-3 {
 110                         function = LED_FUNCTION_STATUS;
 111                         color = <LED_COLOR_ID_GREEN>;
 112                         label = "led02_grn";
 113                         gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
 114                         default-state = "off";
 115                 };
 116
 117                 led-4 {
 118                         function = LED_FUNCTION_STATUS;
 119                         color = <LED_COLOR_ID_RED>;
 120                         label = "led03_red";
 121                         gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
 122                         default-state = "off";
 123                 };
 124
 125                 led-5 {
 126                         function = LED_FUNCTION_STATUS;
 127                         color = <LED_COLOR_ID_GREEN>;
 128                         label = "led03_grn";
 129                         gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
 130                         default-state = "off";
 131                 };
 132
 133                 led-6 {
 134                         function = LED_FUNCTION_STATUS;
 135                         color = <LED_COLOR_ID_RED>;
 136                         label = "led04_red";
 137                         gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
 138                         default-state = "off";
 139                 };
 140
 141                 led-7 {
 142                         function = LED_FUNCTION_STATUS;
 143                         color = <LED_COLOR_ID_GREEN>;
 144                         label = "led04_grn";
 145                         gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
 146                         default-state = "off";
 147                 };
 148
 149                 led-8 {
 150                         function = LED_FUNCTION_STATUS;
 151                         color = <LED_COLOR_ID_RED>;
 152                         label = "led05_red";
 153                         gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
 154                         default-state = "off";
 155                 };
 156
 157                 led-9 {
 158                         function = LED_FUNCTION_STATUS;
 159                         color = <LED_COLOR_ID_GREEN>;
 160                         label = "led05_grn";
 161                         gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
 162                         default-state = "off";
 163                 };
 164
 165                 led-a {
 166                         function = LED_FUNCTION_STATUS;
 167                         color = <LED_COLOR_ID_RED>;
 168                         label = "led06_red";
 169                         gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
 170                         default-state = "off";
 171                 };
 172
 173                 led-b {
 174                         function = LED_FUNCTION_STATUS;
 175                         color = <LED_COLOR_ID_GREEN>;
 176                         label = "led06_grn";
 177                         gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
 178                         default-state = "off";
 179                 };
 180         };
 181
 182         reg_3p3v: regulator-3p3v {
 183                 compatible = "regulator-fixed";
 184                 regulator-name = "3P3V";
 185                 regulator-min-microvolt = <3300000>;
 186                 regulator-max-microvolt = <3300000>;
 187         };
 188
 189         regulator-ioexp {
 190                 pinctrl-names = "default";
 191                 pinctrl-0 = <&pinctrl_reg_ioexp>;
 192                 compatible = "regulator-fixed";
 193                 regulator-name = "ioexp";
 194                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 195                 enable-active-high;
 196                 startup-delay-us = <100>;
 197                 regulator-min-microvolt = <3300000>;
 198                 regulator-max-microvolt = <3300000>;
 199                 regulator-always-on;
 200         };
 201
 202         regulator-isouart {
 203                 pinctrl-names = "default";
 204                 pinctrl-0 = <&pinctrl_reg_isouart>;
 205                 compatible = "regulator-fixed";
 206                 regulator-name = "iso_uart";
 207                 gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
 208                 startup-delay-us = <100>;
 209                 regulator-min-microvolt = <3300000>;
 210                 regulator-max-microvolt = <3300000>;
 211                 regulator-always-on;
 212         };
 213
 214         reg_usb2_vbus: regulator-usb2 {
 215                 pinctrl-names = "default";
 216                 pinctrl-0 = <&pinctrl_reg_usb2>;
 217                 compatible = "regulator-fixed";
 218                 regulator-name = "usb_usb2_vbus";
 219                 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
 220                 enable-active-high;
 221                 regulator-min-microvolt = <5000000>;
 222                 regulator-max-microvolt = <5000000>;
 223         };
 224
 225         reg_wifi: regulator-wifi {
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&pinctrl_reg_wl>;
 228                 compatible = "regulator-fixed";
 229                 regulator-name = "wifi";
 230                 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
 231                 enable-active-high;
 232                 startup-delay-us = <100>;
 233                 regulator-min-microvolt = <3300000>;
 234                 regulator-max-microvolt = <3300000>;
 235         };
 236 };
 237
 238 &ddrc {
 239         operating-points-v2 = <&ddrc_opp_table>;
 240
 241         ddrc_opp_table: opp-table {
 242                 compatible = "operating-points-v2";
 243
 244                 opp-25M {
 245                         opp-hz = /bits/ 64 <25000000>;
 246                 };
 247
 248                 opp-100M {
 249                         opp-hz = /bits/ 64 <100000000>;
 250                 };
 251
 252                 opp-750M {
 253                         opp-hz = /bits/ 64 <750000000>;
 254                 };
 255         };
 256 };
 257
 258 &ecspi1 {
 259         pinctrl-names = "default";
 260         pinctrl-0 = <&pinctrl_spi1>;
 261         cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 262         status = "okay";
 263
 264         flash@0 {
 265                 compatible = "jedec,spi-nor";
 266                 reg = <0>;
 267                 spi-max-frequency = <40000000>;
 268                 status = "okay";
 269         };
 270 };
 271
 272 &fec1 {
 273         pinctrl-names = "default";
 274         pinctrl-0 = <&pinctrl_fec1>;
 275         phy-mode = "rgmii-id";
 276         local-mac-address = [00 00 00 00 00 00];
 277         status = "okay";
 278
 279         fixed-link {
 280                 speed = <1000>;
 281                 full-duplex;
 282         };
 283 };
 284
 285 &i2c1 {
 286         clock-frequency = <100000>;
 287         pinctrl-names = "default";
 288         pinctrl-0 = <&pinctrl_i2c1>;
 289         status = "okay";
 290
 291         gsc: gsc@20 {
 292                 compatible = "gw,gsc";
 293                 reg = <0x20>;
 294                 pinctrl-0 = <&pinctrl_gsc>;
 295                 interrupt-parent = <&gpio4>;
 296                 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
 297                 interrupt-controller;
 298                 #interrupt-cells = <1>;
 299
 300                 adc {
 301                         compatible = "gw,gsc-adc";
 302                         #address-cells = <1>;
 303                         #size-cells = <0>;
 304
 305                         channel@6 {
 306                                 gw,mode = <0>;
 307                                 reg = <0x06>;
 308                                 label = "temp";
 309                         };
 310
 311                         channel@8 {
 312                                 gw,mode = <1>;
 313                                 reg = <0x08>;
 314                                 label = "vdd_bat";
 315                         };
 316
 317                         channel@82 {
 318                                 gw,mode = <2>;
 319                                 reg = <0x82>;
 320                                 label = "vin_aux1";
 321                                 gw,voltage-divider-ohms = <22100 1000>;
 322                         };
 323
 324                         channel@84 {
 325                                 gw,mode = <2>;
 326                                 reg = <0x84>;
 327                                 label = "vin_aux2";
 328                                 gw,voltage-divider-ohms = <22100 1000>;
 329                         };
 330
 331                         channel@86 {
 332                                 gw,mode = <2>;
 333                                 reg = <0x86>;
 334                                 label = "vdd_vin";
 335                                 gw,voltage-divider-ohms = <22100 1000>;
 336                         };
 337
 338                         channel@88 {
 339                                 gw,mode = <2>;
 340                                 reg = <0x88>;
 341                                 label = "vdd_3p3";
 342                                 gw,voltage-divider-ohms = <10000 10000>;
 343                         };
 344
 345                         channel@8c {
 346                                 gw,mode = <2>;
 347                                 reg = <0x8c>;
 348                                 label = "vdd_2p5";
 349                                 gw,voltage-divider-ohms = <10000 10000>;
 350                         };
 351
 352                         channel@8e {
 353                                 gw,mode = <2>;
 354                                 reg = <0x8e>;
 355                                 label = "vdd_0p95";
 356                         };
 357
 358                         channel@90 {
 359                                 gw,mode = <2>;
 360                                 reg = <0x90>;
 361                                 label = "vdd_soc";
 362                         };
 363
 364                         channel@92 {
 365                                 gw,mode = <2>;
 366                                 reg = <0x92>;
 367                                 label = "vdd_arm";
 368                         };
 369
 370                         channel@98 {
 371                                 gw,mode = <2>;
 372                                 reg = <0x98>;
 373                                 label = "vdd_1p8";
 374                         };
 375
 376                         channel@9a {
 377                                 gw,mode = <2>;
 378                                 reg = <0x9a>;
 379                                 label = "vdd_1p2";
 380                         };
 381
 382                         channel@9c {
 383                                 gw,mode = <2>;
 384                                 reg = <0x9c>;
 385                                 label = "vdd_dram";
 386                         };
 387
 388                         channel@a2 {
 389                                 gw,mode = <2>;
 390                                 reg = <0xa2>;
 391                                 label = "vdd_gsc";
 392                                 gw,voltage-divider-ohms = <10000 10000>;
 393                         };
 394                 };
 395         };
 396
 397         gpio: gpio@23 {
 398                 compatible = "nxp,pca9555";
 399                 reg = <0x23>;
 400                 gpio-controller;
 401                 #gpio-cells = <2>;
 402                 interrupt-parent = <&gsc>;
 403                 interrupts = <4>;
 404         };
 405
 406         eeprom@50 {
 407                 compatible = "atmel,24c02";
 408                 reg = <0x50>;
 409                 pagesize = <16>;
 410         };
 411
 412         eeprom@51 {
 413                 compatible = "atmel,24c02";
 414                 reg = <0x51>;
 415                 pagesize = <16>;
 416         };
 417
 418         eeprom@52 {
 419                 compatible = "atmel,24c02";
 420                 reg = <0x52>;
 421                 pagesize = <16>;
 422         };
 423
 424         eeprom@53 {
 425                 compatible = "atmel,24c02";
 426                 reg = <0x53>;
 427                 pagesize = <16>;
 428         };
 429
 430         rtc@68 {
 431                 compatible = "dallas,ds1672";
 432                 reg = <0x68>;
 433         };
 434 };
 435
 436 &i2c2 {
 437         clock-frequency = <400000>;
 438         pinctrl-names = "default";
 439         pinctrl-0 = <&pinctrl_i2c2>;
 440         status = "okay";
 441
 442         pmic@4b {
 443                 compatible = "rohm,bd71847";
 444                 reg = <0x4b>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&pinctrl_pmic>;
 447                 interrupt-parent = <&gpio3>;
 448                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 449                 rohm,reset-snvs-powered;
 450                 #clock-cells = <0>;
 451                 clocks = <&osc_32k 0>;
 452                 clock-output-names = "clk-32k-out";
 453
 454                 regulators {
 455                         /* vdd_soc: 0.805-0.900V (typ=0.8V) */
 456                         BUCK1 {
 457                                 regulator-name = "buck1";
 458                                 regulator-min-microvolt = <700000>;
 459                                 regulator-max-microvolt = <1300000>;
 460                                 regulator-boot-on;
 461                                 regulator-always-on;
 462                                 regulator-ramp-delay = <1250>;
 463                         };
 464
 465                         /* vdd_arm: 0.805-1.0V (typ=0.9V) */
 466                         BUCK2 {
 467                                 regulator-name = "buck2";
 468                                 regulator-min-microvolt = <700000>;
 469                                 regulator-max-microvolt = <1300000>;
 470                                 regulator-boot-on;
 471                                 regulator-always-on;
 472                                 regulator-ramp-delay = <1250>;
 473                                 rohm,dvs-run-voltage = <1000000>;
 474                                 rohm,dvs-idle-voltage = <900000>;
 475                         };
 476
 477                         /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
 478                         BUCK3 {
 479                                 regulator-name = "buck3";
 480                                 regulator-min-microvolt = <700000>;
 481                                 regulator-max-microvolt = <1350000>;
 482                                 regulator-boot-on;
 483                                 regulator-always-on;
 484                         };
 485
 486                         /* vdd_3p3 */
 487                         BUCK4 {
 488                                 regulator-name = "buck4";
 489                                 regulator-min-microvolt = <3000000>;
 490                                 regulator-max-microvolt = <3300000>;
 491                                 regulator-boot-on;
 492                                 regulator-always-on;
 493                         };
 494
 495                         /* vdd_1p8 */
 496                         BUCK5 {
 497                                 regulator-name = "buck5";
 498                                 regulator-min-microvolt = <1605000>;
 499                                 regulator-max-microvolt = <1995000>;
 500                                 regulator-boot-on;
 501                                 regulator-always-on;
 502                         };
 503
 504                         /* vdd_dram */
 505                         BUCK6 {
 506                                 regulator-name = "buck6";
 507                                 regulator-min-microvolt = <800000>;
 508                                 regulator-max-microvolt = <1400000>;
 509                                 regulator-boot-on;
 510                                 regulator-always-on;
 511                         };
 512
 513                         /* nvcc_snvs_1p8 */
 514                         LDO1 {
 515                                 regulator-name = "ldo1";
 516                                 regulator-min-microvolt = <1600000>;
 517                                 regulator-max-microvolt = <1900000>;
 518                                 regulator-boot-on;
 519                                 regulator-always-on;
 520                         };
 521
 522                         /* vdd_snvs_0p8 */
 523                         LDO2 {
 524                                 regulator-name = "ldo2";
 525                                 regulator-min-microvolt = <800000>;
 526                                 regulator-max-microvolt = <900000>;
 527                                 regulator-boot-on;
 528                                 regulator-always-on;
 529                         };
 530
 531                         /* vdda_1p8 */
 532                         LDO3 {
 533                                 regulator-name = "ldo3";
 534                                 regulator-min-microvolt = <1800000>;
 535                                 regulator-max-microvolt = <3300000>;
 536                                 regulator-boot-on;
 537                                 regulator-always-on;
 538                         };
 539
 540                         LDO4 {
 541                                 regulator-name = "ldo4";
 542                                 regulator-min-microvolt = <900000>;
 543                                 regulator-max-microvolt = <1800000>;
 544                                 regulator-boot-on;
 545                                 regulator-always-on;
 546                         };
 547
 548                         LDO6 {
 549                                 regulator-name = "ldo6";
 550                                 regulator-min-microvolt = <900000>;
 551                                 regulator-max-microvolt = <1800000>;
 552                                 regulator-boot-on;
 553                                 regulator-always-on;
 554                         };
 555                 };
 556         };
 557 };
 558
 559 &i2c3 {
 560         clock-frequency = <400000>;
 561         pinctrl-names = "default";
 562         pinctrl-0 = <&pinctrl_i2c3>;
 563         status = "okay";
 564
 565         leds_gpio: gpio@20 {
 566                 compatible = "nxp,pca9555";
 567                 reg = <0x20>;
 568                 gpio-controller;
 569                 #gpio-cells = <2>;
 570         };
 571
 572         switch: switch@5f {
 573                 compatible = "microchip,ksz9897";
 574                 reg = <0x5f>;
 575                 pinctrl-0 = <&pinctrl_ksz>;
 576                 interrupt-parent = <&gpio4>;
 577                 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
 578                 phy-mode = "rgmii-id";
 579
 580                 ports {
 581                         #address-cells = <1>;
 582                         #size-cells = <0>;
 583
 584                         lan1: port@0 {
 585                                 reg = <0>;
 586                                 label = "lan1";
 587                                 local-mac-address = [00 00 00 00 00 00];
 588                         };
 589
 590                         lan2: port@1 {
 591                                 reg = <1>;
 592                                 label = "lan2";
 593                                 local-mac-address = [00 00 00 00 00 00];
 594                         };
 595
 596                         lan3: port@2 {
 597                                 reg = <2>;
 598                                 label = "lan3";
 599                                 local-mac-address = [00 00 00 00 00 00];
 600                         };
 601
 602                         lan4: port@3 {
 603                                 reg = <3>;
 604                                 label = "lan4";
 605                                 local-mac-address = [00 00 00 00 00 00];
 606                         };
 607
 608                         port@5 {
 609                                 reg = <5>;
 610                                 label = "cpu";
 611                                 ethernet = <&fec1>;
 612                                 phy-mode = "rgmii-id";
 613
 614                                 fixed-link {
 615                                         speed = <1000>;
 616                                         full-duplex;
 617                                 };
 618                         };
 619                 };
 620         };
 621
 622         crypto@60 {
 623                 compatible = "atmel,atecc508a";
 624                 reg = <0x60>;
 625         };
 626 };
 627
 628 &i2c4 {
 629         clock-frequency = <400000>;
 630         pinctrl-names = "default";
 631         pinctrl-0 = <&pinctrl_i2c4>;
 632         status = "okay";
 633 };
 634
 635 &uart1 {
 636         pinctrl-names = "default";
 637         pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
 638         rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
 639         cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
 640         dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 641         dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 642         dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 643         status = "okay";
 644 };
 645
 646 /* console */
 647 &uart2 {
 648         pinctrl-names = "default";
 649         pinctrl-0 = <&pinctrl_uart2>;
 650         status = "okay";
 651 };
 652
 653 &uart3 {
 654         pinctrl-names = "default";
 655         pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
 656         cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
 657         rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
 658         status = "okay";
 659 };
 660
 661 &uart4 {
 662         pinctrl-names = "default";
 663         pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
 664         cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
 665         rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
 666         status = "okay";
 667 };
 668
 669 &usbotg1 {
 670         dr_mode = "host";
 671         disable-over-current;
 672         status = "okay";
 673 };
 674
 675 &usbotg2 {
 676         dr_mode = "host";
 677         vbus-supply = <&reg_usb2_vbus>;
 678         status = "okay";
 679 };
 680
 681 /* SDIO WiFi */
 682 &usdhc1 {
 683         pinctrl-names = "default";
 684         pinctrl-0 = <&pinctrl_usdhc1>;
 685         bus-width = <4>;
 686         non-removable;
 687         vmmc-supply = <&reg_wifi>;
 688         status = "okay";
 689 };
 690
 691 /* microSD */
 692 &usdhc2 {
 693         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 694         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 695         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 696         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 697         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 698         bus-width = <4>;
 699         vmmc-supply = <&reg_3p3v>;
 700         status = "okay";
 701 };
 702
 703 /* eMMC */
 704 &usdhc3 {
 705         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 706         pinctrl-0 = <&pinctrl_usdhc3>;
 707         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 708         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 709         bus-width = <8>;
 710         non-removable;
 711         status = "okay";
 712 };
 713
 714 &wdog1 {
 715         pinctrl-names = "default";
 716         pinctrl-0 = <&pinctrl_wdog>;
 717         fsl,ext-reset-output;
 718         status = "okay";
 719 };
 720
 721 &iomuxc {
 722         pinctrl-names = "default";
 723         pinctrl-0 = <&pinctrl_hog>;
 724
 725         pinctrl_hog: hoggrp {
 726                 fsl,pins = <
 727                         MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3         0x40000041 /* DIG2_OUT */
 728                         MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4         0x40000041 /* DIG2_IN */
 729                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6       0x40000041 /* DIG1_IN */
 730                         MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x40000041 /* DIG1_OUT */
 731                         MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30        0x40000041 /* SIM2DET# */
 732                         MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29        0x40000041 /* SIM1DET# */
 733                         MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0x40000041 /* SIM2SEL */
 734                 >;
 735         };
 736
 737         pinctrl_fec1: fec1grp {
 738                 fsl,pins = <
 739                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 740                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 741                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 742                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 743                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 744                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 745                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 746                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 747                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 748                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 749                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 750                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 751                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 752                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 753                         MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18               0x19 /* IRQ# */
 754                         MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19               0x19 /* RST# */
 755                 >;
 756         };
 757
 758         pinctrl_gsc: gscgrp {
 759                 fsl,pins = <
 760                         MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16       0x159
 761                 >;
 762         };
 763
 764         pinctrl_i2c1: i2c1grp {
 765                 fsl,pins = <
 766                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 767                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 768                 >;
 769         };
 770
 771         pinctrl_i2c2: i2c2grp {
 772                 fsl,pins = <
 773                         MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 774                         MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 775                 >;
 776         };
 777
 778         pinctrl_i2c3: i2c3grp {
 779                 fsl,pins = <
 780                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 781                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 782                 >;
 783         };
 784
 785         pinctrl_i2c4: i2c4grp {
 786                 fsl,pins = <
 787                         MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL          0x400001c3
 788                         MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA          0x400001c3
 789                 >;
 790         };
 791
 792         pinctrl_ksz: kszgrp {
 793                 fsl,pins = <
 794                         MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18       0x41
 795                         MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19       0x41 /* RST# */
 796                 >;
 797         };
 798
 799         pinctrl_pmic: pmicgrp {
 800                 fsl,pins = <
 801                         MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20        0x41
 802                 >;
 803         };
 804
 805         pinctrl_reg_isouart: regisouartgrp {
 806                 fsl,pins = <
 807                         MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13      0x40000041
 808                 >;
 809         };
 810
 811         pinctrl_reg_ioexp: regioexpgrp {
 812                 fsl,pins = <
 813                         MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x40000041
 814                 >;
 815         };
 816
 817         pinctrl_reg_wl: regwlgrp {
 818                 fsl,pins = <
 819                         MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25       0x40000041
 820                 >;
 821         };
 822
 823         pinctrl_reg_usb2: regusb1grp {
 824                 fsl,pins = <
 825                         MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2        0x41
 826                         MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17       0x140
 827                         MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC     0x140
 828                 >;
 829         };
 830
 831         pinctrl_spi1: spi1grp {
 832                 fsl,pins = <
 833                         MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x82
 834                         MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x82
 835                         MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x82
 836                         MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9       0x140
 837                 >;
 838         };
 839
 840         pinctrl_uart1: uart1grp {
 841                 fsl,pins = <
 842                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 843                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 844                         MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1       0x140
 845                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10      0x140
 846                         MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11      0x140
 847                         MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x140
 848                         MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14      0x140
 849                 >;
 850         };
 851
 852         pinctrl_uart1_gpio: uart1gpiogrp {
 853                 fsl,pins = <
 854                         MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0       0x40000041 /* RS422# */
 855                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x40000041 /* RS485# */
 856                         MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x40000041 /* RS232# */
 857                 >;
 858         };
 859
 860         pinctrl_uart2: uart2grp {
 861                 fsl,pins = <
 862                         MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 863                         MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 864                 >;
 865         };
 866
 867         pinctrl_uart3: uart3grp {
 868                 fsl,pins = <
 869                         MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
 870                         MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
 871                         MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9        0x140
 872                         MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10       0x140
 873                 >;
 874         };
 875
 876         pinctrl_uart3_gpio: uart3gpiogrp {
 877                 fsl,pins = <
 878                         MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6        0x40000110 /* RS232# */
 879                         MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7        0x40000110 /* RS422# */
 880                         MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8        0x40000110 /* RS485# */
 881                 >;
 882         };
 883
 884         pinctrl_uart4: uart4grp {
 885                 fsl,pins = <
 886                         MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX     0x140
 887                         MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140
 888                         MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11     0x140
 889                         MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12     0x140
 890                 >;
 891         };
 892
 893         pinctrl_uart4_gpio: uart4gpiogrp {
 894                 fsl,pins = <
 895
 896                         MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10     0x40000041 /* RS232# */
 897                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x40000041 /* RS422# */
 898                         MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27       0x40000041 /* RS485# */
 899                 >;
 900         };
 901
 902         pinctrl_usdhc1: usdhc1grp {
 903                 fsl,pins = <
 904                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 905                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 906                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 907                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 908                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 909                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 910                 >;
 911         };
 912
 913         pinctrl_usdhc2: usdhc2grp {
 914                 fsl,pins = <
 915                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 916                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 917                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 918                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 919                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 920                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 921                 >;
 922         };
 923
 924         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 925                 fsl,pins = <
 926                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 927                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 928                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 929                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 930                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 931                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 932                 >;
 933         };
 934
 935         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 936                 fsl,pins = <
 937                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 938                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 939                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 940                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 941                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 942                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 943                 >;
 944         };
 945
 946         pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
 947                 fsl,pins = <
 948                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12        0x1c4
 949                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 950                 >;
 951         };
 952
 953         pinctrl_usdhc3: usdhc3grp {
 954                 fsl,pins = <
 955                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
 956                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
 957                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
 958                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
 959                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
 960                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
 961                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0
 962                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0
 963                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0
 964                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0
 965                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190
 966                 >;
 967         };
 968
 969         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 970                 fsl,pins = <
 971                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
 972                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
 973                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
 974                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
 975                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
 976                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
 977                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4
 978                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4
 979                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4
 980                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4
 981                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194
 982                 >;
 983         };
 984
 985         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 986                 fsl,pins = <
 987                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
 988                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
 989                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
 990                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
 991                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
 992                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
 993                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6
 994                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6
 995                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6
 996                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6
 997                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196
 998                 >;
 999         };
1000
1001         pinctrl_wdog: wdoggrp {
1002                 fsl,pins = <
1003                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
1004                 >;
1005         };
1006 };
1007
1008 &cpu_alert0 {
1009         temperature = <95000>;
1010         hysteresis = <2000>;
1011         type = "passive";
1012 };
1013
1014 &cpu_crit0 {
1015         temperature = <105000>;
1016         hysteresis = <2000>;
1017         type = "critical";
1018 };