arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-2088A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  * Copyright 2017 NXP
   7  *
   8  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
   9  *
  10  */
  11
  12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
  13 #include "fsl-ls208xa.dtsi"
  14
  15 &cpu {
  16         cpu0: cpu@0 {
  17                 device_type = "cpu";
  18                 compatible = "arm,cortex-a72";
  19                 reg = <0x0>;
  20                 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  21                 cpu-idle-states = <&CPU_PW20>;
  22                 next-level-cache = <&cluster0_l2>;
  23                 #cooling-cells = <2>;
  24         };
  25
  26         cpu1: cpu@1 {
  27                 device_type = "cpu";
  28                 compatible = "arm,cortex-a72";
  29                 reg = <0x1>;
  30                 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  31                 cpu-idle-states = <&CPU_PW20>;
  32                 next-level-cache = <&cluster0_l2>;
  33                 #cooling-cells = <2>;
  34         };
  35
  36         cpu2: cpu@100 {
  37                 device_type = "cpu";
  38                 compatible = "arm,cortex-a72";
  39                 reg = <0x100>;
  40                 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
  41                 cpu-idle-states = <&CPU_PW20>;
  42                 next-level-cache = <&cluster1_l2>;
  43                 #cooling-cells = <2>;
  44         };
  45
  46         cpu3: cpu@101 {
  47                 device_type = "cpu";
  48                 compatible = "arm,cortex-a72";
  49                 reg = <0x101>;
  50                 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
  51                 cpu-idle-states = <&CPU_PW20>;
  52                 next-level-cache = <&cluster1_l2>;
  53                 #cooling-cells = <2>;
  54         };
  55
  56         cpu4: cpu@200 {
  57                 device_type = "cpu";
  58                 compatible = "arm,cortex-a72";
  59                 reg = <0x200>;
  60                 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
  61                 next-level-cache = <&cluster2_l2>;
  62                 cpu-idle-states = <&CPU_PW20>;
  63                 #cooling-cells = <2>;
  64         };
  65
  66         cpu5: cpu@201 {
  67                 device_type = "cpu";
  68                 compatible = "arm,cortex-a72";
  69                 reg = <0x201>;
  70                 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
  71                 cpu-idle-states = <&CPU_PW20>;
  72                 next-level-cache = <&cluster2_l2>;
  73                 #cooling-cells = <2>;
  74         };
  75
  76         cpu6: cpu@300 {
  77                 device_type = "cpu";
  78                 compatible = "arm,cortex-a72";
  79                 reg = <0x300>;
  80                 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
  81                 cpu-idle-states = <&CPU_PW20>;
  82                 next-level-cache = <&cluster3_l2>;
  83                 #cooling-cells = <2>;
  84         };
  85
  86         cpu7: cpu@301 {
  87                 device_type = "cpu";
  88                 compatible = "arm,cortex-a72";
  89                 reg = <0x301>;
  90                 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
  91                 cpu-idle-states = <&CPU_PW20>;
  92                 next-level-cache = <&cluster3_l2>;
  93                 #cooling-cells = <2>;
  94         };
  95
  96         cluster0_l2: l2-cache0 {
  97                 compatible = "cache";
  98         };
  99
 100         cluster1_l2: l2-cache1 {
 101                 compatible = "cache";
 102         };
 103
 104         cluster2_l2: l2-cache2 {
 105                 compatible = "cache";
 106         };
 107
 108         cluster3_l2: l2-cache3 {
 109                 compatible = "cache";
 110         };
 111
 112         CPU_PW20: cpu-pw20 {
 113                 compatible = "arm,idle-state";
 114                 idle-state-name = "PW20";
 115                 arm,psci-suspend-param = <0x0>;
 116                 entry-latency-us = <2000>;
 117                 exit-latency-us = <2000>;
 118                 min-residency-us = <6000>;
 119         };
 120 };
 121
 122 &pcie1 {
 123         compatible = "fsl,ls2088a-pcie";
 124         reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
 125               <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 126
 127         ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
 128                   0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
 129 };
 130
 131 &pcie2 {
 132         compatible = "fsl,ls2088a-pcie";
 133         reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
 134               <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 135
 136         ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
 137                   0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
 138 };
 139
 140 &pcie3 {
 141         compatible = "fsl,ls2088a-pcie";
 142         reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
 143               <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 144
 145         ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
 146                   0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
 147 };
 148
 149 &pcie4 {
 150         compatible = "fsl,ls2088a-pcie";
 151         reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
 152               <0x38 0x00000000 0x0 0x00002000>; /* configuration space */
 153
 154         ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
 155                   0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
 156 };