arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree file for Travese Ten64 (LS1088) board
   4  * Based on fsl-ls1088a-rdb.dts
   5  * Copyright 2017-2020 NXP
   6  * Copyright 2019-2021 Traverse Technologies
   7  *
   8  * Author: Mathew McBride <matt@traverse.com.au>
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "fsl-ls1088a.dtsi"
  14
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/input/input.h>
  17
  18 / {
  19         model = "Traverse Ten64";
  20         compatible = "traverse,ten64", "fsl,ls1088a";
  21
  22         aliases {
  23                 serial0 = &duart0;
  24                 serial1 = &duart1;
  25         };
  26
  27         chosen {
  28                 stdout-path = "serial0:115200n8";
  29         };
  30
  31         buttons {
  32                 compatible = "gpio-keys";
  33
  34                 /* Fired by system controller when
  35                  * external power off (e.g ATX Power Button)
  36                  * asserted
  37                  */
  38                 powerdn {
  39                         label = "External Power Down";
  40                         gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
  41                         interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>;
  42                         linux,code = <KEY_POWER>;
  43                 };
  44
  45                 /* Rear Panel 'ADMIN' button (GPIO_H) */
  46                 admin {
  47                         label = "ADMIN button";
  48                         gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
  49                         interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>;
  50                         linux,code = <KEY_WPS_BUTTON>;
  51                 };
  52         };
  53
  54         leds {
  55                 compatible = "gpio-leds";
  56
  57                 sfp1down {
  58                         label = "ten64:green:sfp1:down";
  59                         gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
  60                 };
  61
  62                 sfp2up {
  63                         label = "ten64:green:sfp2:up";
  64                         gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
  65                 };
  66
  67                 admin {
  68                         label = "ten64:admin";
  69                         gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
  70                 };
  71         };
  72
  73         sfp_xg0: dpmac2-sfp {
  74                 compatible = "sff,sfp";
  75                 i2c-bus = <&sfplower_i2c>;
  76                 tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
  77                 tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
  78                 mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
  79                 los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
  80                 maximum-power-milliwatt = <2000>;
  81         };
  82
  83         sfp_xg1: dpmac1-sfp {
  84                 compatible = "sff,sfp";
  85                 i2c-bus = <&sfpupper_i2c>;
  86                 tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
  87                 tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
  88                 mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
  89                 los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
  90                 maximum-power-milliwatt = <2000>;
  91         };
  92 };
  93
  94 /* XG1 - Upper SFP */
  95 &dpmac1 {
  96         sfp = <&sfp_xg1>;
  97         pcs-handle = <&pcs1>;
  98         phy-connection-type = "10gbase-r";
  99         managed = "in-band-status";
 100 };
 101
 102 /* XG0 - Lower SFP */
 103 &dpmac2 {
 104         sfp = <&sfp_xg0>;
 105         pcs-handle = <&pcs2>;
 106         phy-connection-type = "10gbase-r";
 107         managed = "in-band-status";
 108 };
 109
 110 /* DPMAC3..6 is GE4 to GE8 */
 111 &dpmac3 {
 112         phy-handle = <&mdio1_phy5>;
 113         phy-connection-type = "qsgmii";
 114         managed = "in-band-status";
 115         pcs-handle = <&pcs3_0>;
 116 };
 117
 118 &dpmac4 {
 119         phy-handle = <&mdio1_phy6>;
 120         phy-connection-type = "qsgmii";
 121         managed = "in-band-status";
 122         pcs-handle = <&pcs3_1>;
 123 };
 124
 125 &dpmac5 {
 126         phy-handle = <&mdio1_phy7>;
 127         phy-connection-type = "qsgmii";
 128         managed = "in-band-status";
 129         pcs-handle = <&pcs3_2>;
 130 };
 131
 132 &dpmac6 {
 133         phy-handle = <&mdio1_phy8>;
 134         phy-connection-type = "qsgmii";
 135         managed = "in-band-status";
 136         pcs-handle = <&pcs3_3>;
 137 };
 138
 139 /* DPMAC7..10 is GE0 to GE3 */
 140 &dpmac7 {
 141         phy-handle = <&mdio1_phy1>;
 142         phy-connection-type = "qsgmii";
 143         managed = "in-band-status";
 144         pcs-handle = <&pcs7_0>;
 145 };
 146
 147 &dpmac8 {
 148         phy-handle = <&mdio1_phy2>;
 149         phy-connection-type = "qsgmii";
 150         managed = "in-band-status";
 151         pcs-handle = <&pcs7_1>;
 152 };
 153
 154 &dpmac9 {
 155         phy-handle = <&mdio1_phy3>;
 156         phy-connection-type = "qsgmii";
 157         managed = "in-band-status";
 158         pcs-handle = <&pcs7_2>;
 159 };
 160
 161 &dpmac10 {
 162         phy-handle = <&mdio1_phy4>;
 163         phy-connection-type = "qsgmii";
 164         managed = "in-band-status";
 165         pcs-handle = <&pcs7_3>;
 166 };
 167
 168 &duart0 {
 169         status = "okay";
 170 };
 171
 172 &duart1 {
 173         status = "okay";
 174 };
 175
 176 &emdio1 {
 177         status = "okay";
 178
 179         mdio1_phy5: ethernet-phy@c {
 180                 reg = <0xc>;
 181         };
 182
 183         mdio1_phy6: ethernet-phy@d {
 184                 reg = <0xd>;
 185         };
 186
 187         mdio1_phy7: ethernet-phy@e {
 188                 reg = <0xe>;
 189         };
 190
 191         mdio1_phy8: ethernet-phy@f {
 192                 reg = <0xf>;
 193         };
 194
 195         mdio1_phy1: ethernet-phy@1c {
 196                 reg = <0x1c>;
 197         };
 198
 199         mdio1_phy2: ethernet-phy@1d {
 200                 reg = <0x1d>;
 201         };
 202
 203         mdio1_phy3: ethernet-phy@1e {
 204                 reg = <0x1e>;
 205         };
 206
 207         mdio1_phy4: ethernet-phy@1f {
 208                 reg = <0x1f>;
 209         };
 210 };
 211
 212 &esdhc {
 213         status = "okay";
 214 };
 215
 216 &i2c0 {
 217         status = "okay";
 218
 219         sfpgpio: gpio@76 {
 220                 compatible = "ti,tca9539";
 221                 reg = <0x76>;
 222                 #gpio-cells = <2>;
 223                 gpio-controller;
 224
 225                 admin_led_lower {
 226                         gpio-hog;
 227                         gpios = <13 GPIO_ACTIVE_HIGH>;
 228                         output-low;
 229                 };
 230         };
 231
 232         at97sc: tpm@29 {
 233                 compatible = "atmel,at97sc3204t";
 234                 reg = <0x29>;
 235         };
 236 };
 237
 238 &i2c2 {
 239         status = "okay";
 240
 241         rx8035: rtc@32 {
 242                 compatible = "epson,rx8035";
 243                 reg = <0x32>;
 244         };
 245 };
 246
 247 &i2c3 {
 248         status = "okay";
 249
 250         i2c-switch@70 {
 251                 compatible = "nxp,pca9540";
 252                 #address-cells = <1>;
 253                 #size-cells = <0>;
 254                 reg = <0x70>;
 255
 256                 sfpupper_i2c: i2c@0 {
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         reg = <0>;
 260                 };
 261
 262                 sfplower_i2c: i2c@1 {
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         reg = <1>;
 266                 };
 267         };
 268 };
 269
 270 &pcs_mdio1 {
 271         status = "okay";
 272 };
 273
 274 &pcs_mdio2 {
 275         status = "okay";
 276 };
 277
 278 &pcs_mdio3 {
 279         status = "okay";
 280 };
 281
 282 &pcs_mdio7 {
 283         status = "okay";
 284 };
 285
 286 &qspi {
 287         status = "okay";
 288
 289         en25s64: flash@0 {
 290                 compatible = "jedec,spi-nor";
 291                 #address-cells = <1>;
 292                 #size-cells = <1>;
 293                 reg = <0>;
 294                 spi-max-frequency = <20000000>;
 295                 spi-rx-bus-width = <4>;
 296                 spi-tx-bus-width = <4>;
 297
 298                 partitions {
 299                         compatible = "fixed-partitions";
 300                         #address-cells = <1>;
 301                         #size-cells = <1>;
 302
 303                         partition@0 {
 304                                 label = "bl2";
 305                                 reg = <0 0x100000>;
 306                         };
 307
 308                         partition@100000 {
 309                                 label = "bl3";
 310                                 reg = <0x100000 0x200000>;
 311                         };
 312
 313                         partition@300000 {
 314                                 label = "mcfirmware";
 315                                 reg = <0x300000 0x200000>;
 316                         };
 317
 318                         partition@500000 {
 319                                 label = "ubootenv";
 320                                 reg = <0x500000 0x80000>;
 321                         };
 322
 323                         partition@580000 {
 324                                 label = "dpl";
 325                                 reg = <0x580000 0x40000>;
 326                         };
 327
 328                         partition@5C0000 {
 329                                 label = "dpc";
 330                                 reg = <0x5C0000 0x40000>;
 331                         };
 332
 333                         partition@600000 {
 334                                 label = "devicetree";
 335                                 reg = <0x600000 0x40000>;
 336                         };
 337                 };
 338         };
 339
 340         nand: flash@1 {
 341                 compatible = "spi-nand";
 342                 #address-cells = <1>;
 343                 #size-cells = <1>;
 344                 reg = <1>;
 345                 spi-max-frequency = <20000000>;
 346                 spi-rx-bus-width = <4>;
 347                 spi-tx-bus-width = <4>;
 348
 349                 partitions {
 350                         compatible = "fixed-partitions";
 351                         #address-cells = <1>;
 352                         #size-cells = <1>;
 353
 354                         /* reserved for future boot direct from NAND flash
 355                          * (this would use the same layout as the 8MiB NOR flash)
 356                          */
 357                         partition@0 {
 358                                 label = "nand-boot-reserved";
 359                                 reg = <0 0x800000>;
 360                         };
 361
 362                         /* recovery / install environment */
 363                         partition@800000 {
 364                                 label = "recovery";
 365                                 reg = <0x800000 0x2000000>;
 366                         };
 367
 368                         /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
 369                         partition@2800000 {
 370                                 label = "ubia";
 371                                 reg = <0x2800000 0x6C00000>;
 372                         };
 373
 374                         /* ubib (second OpenWrt) */
 375                         partition@9400000 {
 376                                 label = "ubib";
 377                                 reg = <0x9400000 0x6C00000>;
 378                         };
 379                 };
 380         };
 381 };
 382
 383 &usb0 {
 384         status = "okay";
 385 };
 386
 387 &usb1 {
 388         status = "okay";
 389 };