arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1012A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  * Copyright 2019-2020 NXP
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "fsl,ls1012a";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 crypto = &crypto;
  21                 rtc1 = &ftm_alarm0;
  22                 rtic-a = &rtic_a;
  23                 rtic-b = &rtic_b;
  24                 rtic-c = &rtic_c;
  25                 rtic-d = &rtic_d;
  26                 sec-mon = &sec_mon;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53";
  36                         reg = <0x0>;
  37                         clocks = <&clockgen 1 0>;
  38                         #cooling-cells = <2>;
  39                         cpu-idle-states = <&CPU_PH20>;
  40                 };
  41         };
  42
  43         idle-states {
  44                 /*
  45                  * PSCI node is not added default, U-boot will add missing
  46                  * parts if it determines to use PSCI.
  47                  */
  48                 entry-method = "psci";
  49
  50                 CPU_PH20: cpu-ph20 {
  51                         compatible = "arm,idle-state";
  52                         idle-state-name = "PH20";
  53                         arm,psci-suspend-param = <0x0>;
  54                         entry-latency-us = <1000>;
  55                         exit-latency-us = <1000>;
  56                         min-residency-us = <3000>;
  57                 };
  58         };
  59
  60         sysclk: sysclk {
  61                 compatible = "fixed-clock";
  62                 #clock-cells = <0>;
  63                 clock-frequency = <125000000>;
  64                 clock-output-names = "sysclk";
  65         };
  66
  67         coreclk: coreclk {
  68                 compatible = "fixed-clock";
  69                 #clock-cells = <0>;
  70                 clock-frequency = <100000000>;
  71                 clock-output-names = "coreclk";
  72         };
  73
  74         timer {
  75                 compatible = "arm,armv8-timer";
  76                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
  77                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
  78                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
  79                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
  80         };
  81
  82         pmu {
  83                 compatible = "arm,armv8-pmuv3";
  84                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
  85         };
  86
  87         gic: interrupt-controller@1400000 {
  88                 compatible = "arm,gic-400";
  89                 #interrupt-cells = <3>;
  90                 interrupt-controller;
  91                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
  92                       <0x0 0x1402000 0 0x2000>, /* GICC */
  93                       <0x0 0x1404000 0 0x2000>, /* GICH */
  94                       <0x0 0x1406000 0 0x2000>; /* GICV */
  95                 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
  96         };
  97
  98         reboot {
  99                 compatible = "syscon-reboot";
 100                 regmap = <&dcfg>;
 101                 offset = <0xb0>;
 102                 mask = <0x02>;
 103         };
 104
 105         thermal-zones {
 106                 cpu_thermal: cpu-thermal {
 107                         polling-delay-passive = <1000>;
 108                         polling-delay = <5000>;
 109                         thermal-sensors = <&tmu 0>;
 110
 111                         trips {
 112                                 cpu_alert: cpu-alert {
 113                                         temperature = <85000>;
 114                                         hysteresis = <2000>;
 115                                         type = "passive";
 116                                 };
 117
 118                                 cpu_crit: cpu-crit {
 119                                         temperature = <95000>;
 120                                         hysteresis = <2000>;
 121                                         type = "critical";
 122                                 };
 123                         };
 124
 125                         cooling-maps {
 126                                 map0 {
 127                                         trip = <&cpu_alert>;
 128                                         cooling-device =
 129                                                 <&cpu0 THERMAL_NO_LIMIT
 130                                                 THERMAL_NO_LIMIT>;
 131                                 };
 132                         };
 133                 };
 134         };
 135
 136         soc {
 137                 compatible = "simple-bus";
 138                 #address-cells = <2>;
 139                 #size-cells = <2>;
 140                 ranges;
 141
 142                 qspi: spi@1550000 {
 143                         compatible = "fsl,ls1021a-qspi";
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         reg = <0x0 0x1550000 0x0 0x10000>,
 147                                 <0x0 0x40000000 0x0 0x10000000>;
 148                         reg-names = "QuadSPI", "QuadSPI-memory";
 149                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 150                         clock-names = "qspi_en", "qspi";
 151                         clocks = <&clockgen 4 0>, <&clockgen 4 0>;
 152                         status = "disabled";
 153                 };
 154
 155                 esdhc0: esdhc@1560000 {
 156                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 157                         reg = <0x0 0x1560000 0x0 0x10000>;
 158                         interrupts = <0 62 0x4>;
 159                         clocks = <&clockgen 4 0>;
 160                         voltage-ranges = <1800 1800 3300 3300>;
 161                         sdhci,auto-cmd12;
 162                         big-endian;
 163                         bus-width = <4>;
 164                         status = "disabled";
 165                 };
 166
 167                 scfg: scfg@1570000 {
 168                         compatible = "fsl,ls1012a-scfg", "syscon";
 169                         reg = <0x0 0x1570000 0x0 0x10000>;
 170                         big-endian;
 171                 };
 172
 173                 esdhc1: esdhc@1580000 {
 174                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 175                         reg = <0x0 0x1580000 0x0 0x10000>;
 176                         interrupts = <0 65 0x4>;
 177                         clocks = <&clockgen 4 0>;
 178                         voltage-ranges = <1800 1800 3300 3300>;
 179                         sdhci,auto-cmd12;
 180                         big-endian;
 181                         broken-cd;
 182                         bus-width = <4>;
 183                         status = "disabled";
 184                 };
 185
 186                 crypto: crypto@1700000 {
 187                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 188                                      "fsl,sec-v4.0";
 189                         fsl,sec-era = <8>;
 190                         #address-cells = <1>;
 191                         #size-cells = <1>;
 192                         ranges = <0x0 0x00 0x1700000 0x100000>;
 193                         reg = <0x00 0x1700000 0x0 0x100000>;
 194                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 195
 196                         sec_jr0: jr@10000 {
 197                                 compatible = "fsl,sec-v5.4-job-ring",
 198                                              "fsl,sec-v5.0-job-ring",
 199                                              "fsl,sec-v4.0-job-ring";
 200                                 reg        = <0x10000 0x10000>;
 201                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 202                         };
 203
 204                         sec_jr1: jr@20000 {
 205                                 compatible = "fsl,sec-v5.4-job-ring",
 206                                              "fsl,sec-v5.0-job-ring",
 207                                              "fsl,sec-v4.0-job-ring";
 208                                 reg        = <0x20000 0x10000>;
 209                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 210                         };
 211
 212                         sec_jr2: jr@30000 {
 213                                 compatible = "fsl,sec-v5.4-job-ring",
 214                                              "fsl,sec-v5.0-job-ring",
 215                                              "fsl,sec-v4.0-job-ring";
 216                                 reg        = <0x30000 0x10000>;
 217                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 218                         };
 219
 220                         sec_jr3: jr@40000 {
 221                                 compatible = "fsl,sec-v5.4-job-ring",
 222                                              "fsl,sec-v5.0-job-ring",
 223                                              "fsl,sec-v4.0-job-ring";
 224                                 reg        = <0x40000 0x10000>;
 225                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 226                         };
 227
 228                         rtic@60000 {
 229                                 compatible = "fsl,sec-v5.4-rtic",
 230                                              "fsl,sec-v5.0-rtic",
 231                                              "fsl,sec-v4.0-rtic";
 232                                 #address-cells = <1>;
 233                                 #size-cells = <1>;
 234                                 reg = <0x60000 0x100 0x60e00 0x18>;
 235                                 ranges = <0x0 0x60100 0x500>;
 236
 237                                 rtic_a: rtic-a@0 {
 238                                         compatible = "fsl,sec-v5.4-rtic-memory",
 239                                                      "fsl,sec-v5.0-rtic-memory",
 240                                                      "fsl,sec-v4.0-rtic-memory";
 241                                         reg = <0x00 0x20 0x100 0x100>;
 242                                 };
 243
 244                                 rtic_b: rtic-b@20 {
 245                                         compatible = "fsl,sec-v5.4-rtic-memory",
 246                                                      "fsl,sec-v5.0-rtic-memory",
 247                                                      "fsl,sec-v4.0-rtic-memory";
 248                                         reg = <0x20 0x20 0x200 0x100>;
 249                                 };
 250
 251                                 rtic_c: rtic-c@40 {
 252                                         compatible = "fsl,sec-v5.4-rtic-memory",
 253                                                      "fsl,sec-v5.0-rtic-memory",
 254                                                      "fsl,sec-v4.0-rtic-memory";
 255                                         reg = <0x40 0x20 0x300 0x100>;
 256                                 };
 257
 258                                 rtic_d: rtic-d@60 {
 259                                         compatible = "fsl,sec-v5.4-rtic-memory",
 260                                                      "fsl,sec-v5.0-rtic-memory",
 261                                                      "fsl,sec-v4.0-rtic-memory";
 262                                         reg = <0x60 0x20 0x400 0x100>;
 263                                 };
 264                         };
 265                 };
 266
 267                 sec_mon: sec_mon@1e90000 {
 268                         compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
 269                                      "fsl,sec-v4.0-mon";
 270                         reg = <0x0 0x1e90000 0x0 0x10000>;
 271                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 273                 };
 274
 275                 dcfg: dcfg@1ee0000 {
 276                         compatible = "fsl,ls1012a-dcfg",
 277                                      "syscon";
 278                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 279                         big-endian;
 280                 };
 281
 282                 clockgen: clocking@1ee1000 {
 283                         compatible = "fsl,ls1012a-clockgen";
 284                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 285                         #clock-cells = <2>;
 286                         clocks = <&sysclk &coreclk>;
 287                         clock-names = "sysclk", "coreclk";
 288                 };
 289
 290                 tmu: tmu@1f00000 {
 291                         compatible = "fsl,qoriq-tmu";
 292                         reg = <0x0 0x1f00000 0x0 0x10000>;
 293                         interrupts = <0 33 0x4>;
 294                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
 295                         fsl,tmu-calibration = <0x00000000 0x00000025
 296                                                0x00000001 0x0000002c
 297                                                0x00000002 0x00000032
 298                                                0x00000003 0x00000039
 299                                                0x00000004 0x0000003f
 300                                                0x00000005 0x00000046
 301                                                0x00000006 0x0000004c
 302                                                0x00000007 0x00000053
 303                                                0x00000008 0x00000059
 304                                                0x00000009 0x0000005f
 305                                                0x0000000a 0x00000066
 306                                                0x0000000b 0x0000006c
 307
 308                                                0x00010000 0x00000026
 309                                                0x00010001 0x0000002d
 310                                                0x00010002 0x00000035
 311                                                0x00010003 0x0000003d
 312                                                0x00010004 0x00000045
 313                                                0x00010005 0x0000004d
 314                                                0x00010006 0x00000055
 315                                                0x00010007 0x0000005d
 316                                                0x00010008 0x00000065
 317                                                0x00010009 0x0000006d
 318
 319                                                0x00020000 0x00000026
 320                                                0x00020001 0x00000030
 321                                                0x00020002 0x0000003a
 322                                                0x00020003 0x00000044
 323                                                0x00020004 0x0000004e
 324                                                0x00020005 0x00000059
 325                                                0x00020006 0x00000063
 326
 327                                                0x00030000 0x00000014
 328                                                0x00030001 0x00000021
 329                                                0x00030002 0x0000002e
 330                                                0x00030003 0x0000003a
 331                                                0x00030004 0x00000047
 332                                                0x00030005 0x00000053
 333                                                0x00030006 0x00000060>;
 334                         big-endian;
 335                         #thermal-sensor-cells = <1>;
 336                 };
 337
 338                 i2c0: i2c@2180000 {
 339                         compatible = "fsl,vf610-i2c";
 340                         #address-cells = <1>;
 341                         #size-cells = <0>;
 342                         reg = <0x0 0x2180000 0x0 0x10000>;
 343                         interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 344                         clocks = <&clockgen 4 3>;
 345                         status = "disabled";
 346                 };
 347
 348                 i2c1: i2c@2190000 {
 349                         compatible = "fsl,vf610-i2c";
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         reg = <0x0 0x2190000 0x0 0x10000>;
 353                         interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 354                         clocks = <&clockgen 4 3>;
 355                         status = "disabled";
 356                 };
 357
 358                 dspi: spi@2100000 {
 359                         compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
 360                         #address-cells = <1>;
 361                         #size-cells = <0>;
 362                         reg = <0x0 0x2100000 0x0 0x10000>;
 363                         interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
 364                         clock-names = "dspi";
 365                         clocks = <&clockgen 4 0>;
 366                         spi-num-chipselects = <5>;
 367                         big-endian;
 368                         status = "disabled";
 369                 };
 370
 371                 duart0: serial@21c0500 {
 372                         compatible = "fsl,ns16550", "ns16550a";
 373                         reg = <0x00 0x21c0500 0x0 0x100>;
 374                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 375                         clocks = <&clockgen 4 0>;
 376                         status = "disabled";
 377                 };
 378
 379                 duart1: serial@21c0600 {
 380                         compatible = "fsl,ns16550", "ns16550a";
 381                         reg = <0x00 0x21c0600 0x0 0x100>;
 382                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&clockgen 4 0>;
 384                         status = "disabled";
 385                 };
 386
 387                 gpio0: gpio@2300000 {
 388                         compatible = "fsl,qoriq-gpio";
 389                         reg = <0x0 0x2300000 0x0 0x10000>;
 390                         interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
 391                         gpio-controller;
 392                         #gpio-cells = <2>;
 393                         interrupt-controller;
 394                         #interrupt-cells = <2>;
 395                 };
 396
 397                 gpio1: gpio@2310000 {
 398                         compatible = "fsl,qoriq-gpio";
 399                         reg = <0x0 0x2310000 0x0 0x10000>;
 400                         interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 401                         gpio-controller;
 402                         #gpio-cells = <2>;
 403                         interrupt-controller;
 404                         #interrupt-cells = <2>;
 405                 };
 406
 407                 wdog0: watchdog@2ad0000 {
 408                         compatible = "fsl,ls1012a-wdt",
 409                                      "fsl,imx21-wdt";
 410                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 411                         interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 412                         clocks = <&clockgen 4 0>;
 413                         big-endian;
 414                 };
 415
 416                 sai1: sai@2b50000 {
 417                         #sound-dai-cells = <0>;
 418                         compatible = "fsl,vf610-sai";
 419                         reg = <0x0 0x2b50000 0x0 0x10000>;
 420                         interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&clockgen 4 3>, <&clockgen 4 3>,
 422                                  <&clockgen 4 3>, <&clockgen 4 3>;
 423                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 424                         dma-names = "tx", "rx";
 425                         dmas = <&edma0 1 47>,
 426                                <&edma0 1 46>;
 427                         status = "disabled";
 428                 };
 429
 430                 sai2: sai@2b60000 {
 431                         #sound-dai-cells = <0>;
 432                         compatible = "fsl,vf610-sai";
 433                         reg = <0x0 0x2b60000 0x0 0x10000>;
 434                         interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 435                         clocks = <&clockgen 4 3>, <&clockgen 4 3>,
 436                                  <&clockgen 4 3>, <&clockgen 4 3>;
 437                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 438                         dma-names = "tx", "rx";
 439                         dmas = <&edma0 1 45>,
 440                                <&edma0 1 44>;
 441                         status = "disabled";
 442                 };
 443
 444                 edma0: edma@2c00000 {
 445                         #dma-cells = <2>;
 446                         compatible = "fsl,vf610-edma";
 447                         reg = <0x0 0x2c00000 0x0 0x10000>,
 448                               <0x0 0x2c10000 0x0 0x10000>,
 449                               <0x0 0x2c20000 0x0 0x10000>;
 450                         interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
 451                                      <0 103 IRQ_TYPE_LEVEL_HIGH>;
 452                         interrupt-names = "edma-tx", "edma-err";
 453                         dma-channels = <32>;
 454                         big-endian;
 455                         clock-names = "dmamux0", "dmamux1";
 456                         clocks = <&clockgen 4 3>,
 457                                  <&clockgen 4 3>;
 458                 };
 459
 460                 usb0: usb@2f00000 {
 461                         compatible = "snps,dwc3";
 462                         reg = <0x0 0x2f00000 0x0 0x10000>;
 463                         interrupts = <0 60 0x4>;
 464                         dr_mode = "host";
 465                         snps,quirk-frame-length-adjustment = <0x20>;
 466                         snps,dis_rxdet_inp3_quirk;
 467                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 468                 };
 469
 470                 sata: sata@3200000 {
 471                         compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
 472                         reg = <0x0 0x3200000 0x0 0x10000>,
 473                                 <0x0 0x20140520 0x0 0x4>;
 474                         reg-names = "ahci", "sata-ecc";
 475                         interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 476                         clocks = <&clockgen 4 0>;
 477                         dma-coherent;
 478                         status = "disabled";
 479                 };
 480
 481                 usb1: usb@8600000 {
 482                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 483                         reg = <0x0 0x8600000 0x0 0x1000>;
 484                         interrupts = <0 139 0x4>;
 485                         dr_mode = "host";
 486                         phy_type = "ulpi";
 487                 };
 488
 489                 msi: msi-controller1@1572000 {
 490                         compatible = "fsl,ls1012a-msi";
 491                         reg = <0x0 0x1572000 0x0 0x8>;
 492                         msi-controller;
 493                         interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 494                 };
 495
 496                 pcie1: pcie@3400000 {
 497                         compatible = "fsl,ls1012a-pcie";
 498                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 499                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 500                         reg-names = "regs", "config";
 501                         interrupts = <0 118 0x4>, /* controller interrupt */
 502                                      <0 117 0x4>; /* PME interrupt */
 503                         interrupt-names = "aer", "pme";
 504                         #address-cells = <3>;
 505                         #size-cells = <2>;
 506                         device_type = "pci";
 507                         num-viewport = <2>;
 508                         bus-range = <0x0 0xff>;
 509                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 510                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 511                         msi-parent = <&msi>;
 512                         #interrupt-cells = <1>;
 513                         interrupt-map-mask = <0 0 0 7>;
 514                         interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
 515                                         <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
 516                                         <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
 517                                         <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
 518                         status = "disabled";
 519                 };
 520
 521                 rcpm: power-controller@1ee2140 {
 522                         compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
 523                         reg = <0x0 0x1ee2140 0x0 0x4>;
 524                         #fsl,rcpm-wakeup-cells = <1>;
 525                 };
 526
 527                 ftm_alarm0: timer@29d0000 {
 528                         compatible = "fsl,ls1012a-ftm-alarm";
 529                         reg = <0x0 0x29d0000 0x0 0x10000>;
 530                         fsl,rcpm-wakeup = <&rcpm 0x20000>;
 531                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 532                         big-endian;
 533                 };
 534         };
 535
 536         firmware {
 537                 optee {
 538                         compatible = "linaro,optee-tz";
 539                         method = "smc";
 540                 };
 541         };
 542 };