arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1012A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  * Copyright 2019-2020 NXP
   7  *
   8  */
   9
  10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "fsl,ls1012a";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 crypto = &crypto;
  22                 rtc1 = &ftm_alarm0;
  23                 rtic-a = &rtic_a;
  24                 rtic-b = &rtic_b;
  25                 rtic-c = &rtic_c;
  26                 rtic-d = &rtic_d;
  27                 sec-mon = &sec_mon;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53";
  37                         reg = <0x0>;
  38                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  39                         #cooling-cells = <2>;
  40                         cpu-idle-states = <&CPU_PH20>;
  41                 };
  42         };
  43
  44         idle-states {
  45                 /*
  46                  * PSCI node is not added default, U-boot will add missing
  47                  * parts if it determines to use PSCI.
  48                  */
  49                 entry-method = "psci";
  50
  51                 CPU_PH20: cpu-ph20 {
  52                         compatible = "arm,idle-state";
  53                         idle-state-name = "PH20";
  54                         arm,psci-suspend-param = <0x0>;
  55                         entry-latency-us = <1000>;
  56                         exit-latency-us = <1000>;
  57                         min-residency-us = <3000>;
  58                 };
  59         };
  60
  61         sysclk: sysclk {
  62                 compatible = "fixed-clock";
  63                 #clock-cells = <0>;
  64                 clock-frequency = <125000000>;
  65                 clock-output-names = "sysclk";
  66         };
  67
  68         coreclk: coreclk {
  69                 compatible = "fixed-clock";
  70                 #clock-cells = <0>;
  71                 clock-frequency = <100000000>;
  72                 clock-output-names = "coreclk";
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv8-timer";
  77                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
  78                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
  79                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
  80                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
  81         };
  82
  83         pmu {
  84                 compatible = "arm,armv8-pmuv3";
  85                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
  86         };
  87
  88         gic: interrupt-controller@1400000 {
  89                 compatible = "arm,gic-400";
  90                 #interrupt-cells = <3>;
  91                 interrupt-controller;
  92                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
  93                       <0x0 0x1402000 0 0x2000>, /* GICC */
  94                       <0x0 0x1404000 0 0x2000>, /* GICH */
  95                       <0x0 0x1406000 0 0x2000>; /* GICV */
  96                 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
  97         };
  98
  99         reboot {
 100                 compatible = "syscon-reboot";
 101                 regmap = <&dcfg>;
 102                 offset = <0xb0>;
 103                 mask = <0x02>;
 104         };
 105
 106         thermal-zones {
 107                 cpu_thermal: cpu-thermal {
 108                         polling-delay-passive = <1000>;
 109                         polling-delay = <5000>;
 110                         thermal-sensors = <&tmu 0>;
 111
 112                         trips {
 113                                 cpu_alert: cpu-alert {
 114                                         temperature = <85000>;
 115                                         hysteresis = <2000>;
 116                                         type = "passive";
 117                                 };
 118
 119                                 cpu_crit: cpu-crit {
 120                                         temperature = <95000>;
 121                                         hysteresis = <2000>;
 122                                         type = "critical";
 123                                 };
 124                         };
 125
 126                         cooling-maps {
 127                                 map0 {
 128                                         trip = <&cpu_alert>;
 129                                         cooling-device =
 130                                                 <&cpu0 THERMAL_NO_LIMIT
 131                                                 THERMAL_NO_LIMIT>;
 132                                 };
 133                         };
 134                 };
 135         };
 136
 137         soc {
 138                 compatible = "simple-bus";
 139                 #address-cells = <2>;
 140                 #size-cells = <2>;
 141                 ranges;
 142
 143                 qspi: spi@1550000 {
 144                         compatible = "fsl,ls1021a-qspi";
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         reg = <0x0 0x1550000 0x0 0x10000>,
 148                                 <0x0 0x40000000 0x0 0x10000000>;
 149                         reg-names = "QuadSPI", "QuadSPI-memory";
 150                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 151                         clock-names = "qspi_en", "qspi";
 152                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 153                                             QORIQ_CLK_PLL_DIV(1)>,
 154                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 155                                             QORIQ_CLK_PLL_DIV(1)>;
 156                         status = "disabled";
 157                 };
 158
 159                 esdhc0: esdhc@1560000 {
 160                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 161                         reg = <0x0 0x1560000 0x0 0x10000>;
 162                         interrupts = <0 62 0x4>;
 163                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 164                                             QORIQ_CLK_PLL_DIV(1)>;
 165                         voltage-ranges = <1800 1800 3300 3300>;
 166                         sdhci,auto-cmd12;
 167                         big-endian;
 168                         bus-width = <4>;
 169                         status = "disabled";
 170                 };
 171
 172                 scfg: scfg@1570000 {
 173                         compatible = "fsl,ls1012a-scfg", "syscon";
 174                         reg = <0x0 0x1570000 0x0 0x10000>;
 175                         big-endian;
 176                 };
 177
 178                 esdhc1: esdhc@1580000 {
 179                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 180                         reg = <0x0 0x1580000 0x0 0x10000>;
 181                         interrupts = <0 65 0x4>;
 182                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 183                                             QORIQ_CLK_PLL_DIV(1)>;
 184                         voltage-ranges = <1800 1800 3300 3300>;
 185                         sdhci,auto-cmd12;
 186                         big-endian;
 187                         broken-cd;
 188                         bus-width = <4>;
 189                         status = "disabled";
 190                 };
 191
 192                 crypto: crypto@1700000 {
 193                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 194                                      "fsl,sec-v4.0";
 195                         fsl,sec-era = <8>;
 196                         #address-cells = <1>;
 197                         #size-cells = <1>;
 198                         ranges = <0x0 0x00 0x1700000 0x100000>;
 199                         reg = <0x00 0x1700000 0x0 0x100000>;
 200                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 201                         dma-coherent;
 202
 203                         sec_jr0: jr@10000 {
 204                                 compatible = "fsl,sec-v5.4-job-ring",
 205                                              "fsl,sec-v5.0-job-ring",
 206                                              "fsl,sec-v4.0-job-ring";
 207                                 reg        = <0x10000 0x10000>;
 208                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 209                         };
 210
 211                         sec_jr1: jr@20000 {
 212                                 compatible = "fsl,sec-v5.4-job-ring",
 213                                              "fsl,sec-v5.0-job-ring",
 214                                              "fsl,sec-v4.0-job-ring";
 215                                 reg        = <0x20000 0x10000>;
 216                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 217                         };
 218
 219                         sec_jr2: jr@30000 {
 220                                 compatible = "fsl,sec-v5.4-job-ring",
 221                                              "fsl,sec-v5.0-job-ring",
 222                                              "fsl,sec-v4.0-job-ring";
 223                                 reg        = <0x30000 0x10000>;
 224                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 225                         };
 226
 227                         sec_jr3: jr@40000 {
 228                                 compatible = "fsl,sec-v5.4-job-ring",
 229                                              "fsl,sec-v5.0-job-ring",
 230                                              "fsl,sec-v4.0-job-ring";
 231                                 reg        = <0x40000 0x10000>;
 232                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 233                         };
 234
 235                         rtic@60000 {
 236                                 compatible = "fsl,sec-v5.4-rtic",
 237                                              "fsl,sec-v5.0-rtic",
 238                                              "fsl,sec-v4.0-rtic";
 239                                 #address-cells = <1>;
 240                                 #size-cells = <1>;
 241                                 reg = <0x60000 0x100>, <0x60e00 0x18>;
 242                                 ranges = <0x0 0x60100 0x500>;
 243
 244                                 rtic_a: rtic-a@0 {
 245                                         compatible = "fsl,sec-v5.4-rtic-memory",
 246                                                      "fsl,sec-v5.0-rtic-memory",
 247                                                      "fsl,sec-v4.0-rtic-memory";
 248                                         reg = <0x00 0x20>, <0x100 0x100>;
 249                                 };
 250
 251                                 rtic_b: rtic-b@20 {
 252                                         compatible = "fsl,sec-v5.4-rtic-memory",
 253                                                      "fsl,sec-v5.0-rtic-memory",
 254                                                      "fsl,sec-v4.0-rtic-memory";
 255                                         reg = <0x20 0x20>, <0x200 0x100>;
 256                                 };
 257
 258                                 rtic_c: rtic-c@40 {
 259                                         compatible = "fsl,sec-v5.4-rtic-memory",
 260                                                      "fsl,sec-v5.0-rtic-memory",
 261                                                      "fsl,sec-v4.0-rtic-memory";
 262                                         reg = <0x40 0x20>, <0x300 0x100>;
 263                                 };
 264
 265                                 rtic_d: rtic-d@60 {
 266                                         compatible = "fsl,sec-v5.4-rtic-memory",
 267                                                      "fsl,sec-v5.0-rtic-memory",
 268                                                      "fsl,sec-v4.0-rtic-memory";
 269                                         reg = <0x60 0x20>, <0x400 0x100>;
 270                                 };
 271                         };
 272                 };
 273
 274                 sec_mon: sec_mon@1e90000 {
 275                         compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
 276                                      "fsl,sec-v4.0-mon";
 277                         reg = <0x0 0x1e90000 0x0 0x10000>;
 278                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 279                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 280                 };
 281
 282                 dcfg: dcfg@1ee0000 {
 283                         compatible = "fsl,ls1012a-dcfg",
 284                                      "syscon";
 285                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 286                         big-endian;
 287                 };
 288
 289                 clockgen: clocking@1ee1000 {
 290                         compatible = "fsl,ls1012a-clockgen";
 291                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 292                         #clock-cells = <2>;
 293                         clocks = <&sysclk &coreclk>;
 294                         clock-names = "sysclk", "coreclk";
 295                 };
 296
 297                 tmu: tmu@1f00000 {
 298                         compatible = "fsl,qoriq-tmu";
 299                         reg = <0x0 0x1f00000 0x0 0x10000>;
 300                         interrupts = <0 33 0x4>;
 301                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
 302                         fsl,tmu-calibration = <0x00000000 0x00000025
 303                                                0x00000001 0x0000002c
 304                                                0x00000002 0x00000032
 305                                                0x00000003 0x00000039
 306                                                0x00000004 0x0000003f
 307                                                0x00000005 0x00000046
 308                                                0x00000006 0x0000004c
 309                                                0x00000007 0x00000053
 310                                                0x00000008 0x00000059
 311                                                0x00000009 0x0000005f
 312                                                0x0000000a 0x00000066
 313                                                0x0000000b 0x0000006c
 314
 315                                                0x00010000 0x00000026
 316                                                0x00010001 0x0000002d
 317                                                0x00010002 0x00000035
 318                                                0x00010003 0x0000003d
 319                                                0x00010004 0x00000045
 320                                                0x00010005 0x0000004d
 321                                                0x00010006 0x00000055
 322                                                0x00010007 0x0000005d
 323                                                0x00010008 0x00000065
 324                                                0x00010009 0x0000006d
 325
 326                                                0x00020000 0x00000026
 327                                                0x00020001 0x00000030
 328                                                0x00020002 0x0000003a
 329                                                0x00020003 0x00000044
 330                                                0x00020004 0x0000004e
 331                                                0x00020005 0x00000059
 332                                                0x00020006 0x00000063
 333
 334                                                0x00030000 0x00000014
 335                                                0x00030001 0x00000021
 336                                                0x00030002 0x0000002e
 337                                                0x00030003 0x0000003a
 338                                                0x00030004 0x00000047
 339                                                0x00030005 0x00000053
 340                                                0x00030006 0x00000060>;
 341                         big-endian;
 342                         #thermal-sensor-cells = <1>;
 343                 };
 344
 345                 i2c0: i2c@2180000 {
 346                         compatible = "fsl,vf610-i2c";
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                         reg = <0x0 0x2180000 0x0 0x10000>;
 350                         interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 351                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 352                                             QORIQ_CLK_PLL_DIV(4)>;
 353                         status = "disabled";
 354                 };
 355
 356                 i2c1: i2c@2190000 {
 357                         compatible = "fsl,vf610-i2c";
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         reg = <0x0 0x2190000 0x0 0x10000>;
 361                         interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 362                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 363                                             QORIQ_CLK_PLL_DIV(4)>;
 364                         status = "disabled";
 365                 };
 366
 367                 dspi: spi@2100000 {
 368                         compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         reg = <0x0 0x2100000 0x0 0x10000>;
 372                         interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
 373                         clock-names = "dspi";
 374                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 375                                             QORIQ_CLK_PLL_DIV(1)>;
 376                         spi-num-chipselects = <5>;
 377                         big-endian;
 378                         status = "disabled";
 379                 };
 380
 381                 duart0: serial@21c0500 {
 382                         compatible = "fsl,ns16550", "ns16550a";
 383                         reg = <0x00 0x21c0500 0x0 0x100>;
 384                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 385                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 386                                             QORIQ_CLK_PLL_DIV(1)>;
 387                         status = "disabled";
 388                 };
 389
 390                 duart1: serial@21c0600 {
 391                         compatible = "fsl,ns16550", "ns16550a";
 392                         reg = <0x00 0x21c0600 0x0 0x100>;
 393                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 395                                             QORIQ_CLK_PLL_DIV(1)>;
 396                         status = "disabled";
 397                 };
 398
 399                 gpio0: gpio@2300000 {
 400                         compatible = "fsl,qoriq-gpio";
 401                         reg = <0x0 0x2300000 0x0 0x10000>;
 402                         interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
 403                         gpio-controller;
 404                         #gpio-cells = <2>;
 405                         interrupt-controller;
 406                         #interrupt-cells = <2>;
 407                 };
 408
 409                 gpio1: gpio@2310000 {
 410                         compatible = "fsl,qoriq-gpio";
 411                         reg = <0x0 0x2310000 0x0 0x10000>;
 412                         interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 413                         gpio-controller;
 414                         #gpio-cells = <2>;
 415                         interrupt-controller;
 416                         #interrupt-cells = <2>;
 417                 };
 418
 419                 wdog0: watchdog@2ad0000 {
 420                         compatible = "fsl,ls1012a-wdt",
 421                                      "fsl,imx21-wdt";
 422                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 423                         interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 424                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>;
 425                         big-endian;
 426                 };
 427
 428                 sai1: sai@2b50000 {
 429                         #sound-dai-cells = <0>;
 430                         compatible = "fsl,vf610-sai";
 431                         reg = <0x0 0x2b50000 0x0 0x10000>;
 432                         interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 433                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 434                                             QORIQ_CLK_PLL_DIV(4)>,
 435                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 436                                             QORIQ_CLK_PLL_DIV(4)>,
 437                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 438                                             QORIQ_CLK_PLL_DIV(4)>,
 439                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 440                                             QORIQ_CLK_PLL_DIV(4)>;
 441                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 442                         dma-names = "tx", "rx";
 443                         dmas = <&edma0 1 47>,
 444                                <&edma0 1 46>;
 445                         status = "disabled";
 446                 };
 447
 448                 sai2: sai@2b60000 {
 449                         #sound-dai-cells = <0>;
 450                         compatible = "fsl,vf610-sai";
 451                         reg = <0x0 0x2b60000 0x0 0x10000>;
 452                         interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 453                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 454                                             QORIQ_CLK_PLL_DIV(4)>,
 455                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 456                                             QORIQ_CLK_PLL_DIV(4)>,
 457                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 458                                             QORIQ_CLK_PLL_DIV(4)>,
 459                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 460                                             QORIQ_CLK_PLL_DIV(4)>;
 461                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 462                         dma-names = "tx", "rx";
 463                         dmas = <&edma0 1 45>,
 464                                <&edma0 1 44>;
 465                         status = "disabled";
 466                 };
 467
 468                 edma0: edma@2c00000 {
 469                         #dma-cells = <2>;
 470                         compatible = "fsl,vf610-edma";
 471                         reg = <0x0 0x2c00000 0x0 0x10000>,
 472                               <0x0 0x2c10000 0x0 0x10000>,
 473                               <0x0 0x2c20000 0x0 0x10000>;
 474                         interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
 475                                      <0 103 IRQ_TYPE_LEVEL_HIGH>;
 476                         interrupt-names = "edma-tx", "edma-err";
 477                         dma-channels = <32>;
 478                         big-endian;
 479                         clock-names = "dmamux0", "dmamux1";
 480                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 481                                             QORIQ_CLK_PLL_DIV(4)>,
 482                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 483                                             QORIQ_CLK_PLL_DIV(4)>;
 484                 };
 485
 486                 usb0: usb@2f00000 {
 487                         compatible = "snps,dwc3";
 488                         reg = <0x0 0x2f00000 0x0 0x10000>;
 489                         interrupts = <0 60 0x4>;
 490                         dr_mode = "host";
 491                         snps,quirk-frame-length-adjustment = <0x20>;
 492                         snps,dis_rxdet_inp3_quirk;
 493                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 494                 };
 495
 496                 sata: sata@3200000 {
 497                         compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
 498                         reg = <0x0 0x3200000 0x0 0x10000>,
 499                                 <0x0 0x20140520 0x0 0x4>;
 500                         reg-names = "ahci", "sata-ecc";
 501                         interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 502                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 503                                             QORIQ_CLK_PLL_DIV(1)>;
 504                         dma-coherent;
 505                         status = "disabled";
 506                 };
 507
 508                 usb1: usb@8600000 {
 509                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 510                         reg = <0x0 0x8600000 0x0 0x1000>;
 511                         interrupts = <0 139 0x4>;
 512                         dr_mode = "host";
 513                         phy_type = "ulpi";
 514                 };
 515
 516                 msi: msi-controller1@1572000 {
 517                         compatible = "fsl,ls1012a-msi";
 518                         reg = <0x0 0x1572000 0x0 0x8>;
 519                         msi-controller;
 520                         interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 521                 };
 522
 523                 pcie1: pcie@3400000 {
 524                         compatible = "fsl,ls1012a-pcie";
 525                         reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
 526                               <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 527                         reg-names = "regs", "config";
 528                         interrupts = <0 118 0x4>, /* controller interrupt */
 529                                      <0 117 0x4>; /* PME interrupt */
 530                         interrupt-names = "aer", "pme";
 531                         #address-cells = <3>;
 532                         #size-cells = <2>;
 533                         device_type = "pci";
 534                         num-viewport = <2>;
 535                         bus-range = <0x0 0xff>;
 536                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 537                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 538                         msi-parent = <&msi>;
 539                         #interrupt-cells = <1>;
 540                         interrupt-map-mask = <0 0 0 7>;
 541                         interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
 542                                         <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
 543                                         <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
 544                                         <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
 545                         status = "disabled";
 546                 };
 547
 548                 rcpm: power-controller@1ee2140 {
 549                         compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
 550                         reg = <0x0 0x1ee2140 0x0 0x4>;
 551                         #fsl,rcpm-wakeup-cells = <1>;
 552                 };
 553
 554                 ftm_alarm0: timer@29d0000 {
 555                         compatible = "fsl,ls1012a-ftm-alarm";
 556                         reg = <0x0 0x29d0000 0x0 0x10000>;
 557                         fsl,rcpm-wakeup = <&rcpm 0x20000>;
 558                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 559                         big-endian;
 560                 };
 561         };
 562
 563         firmware {
 564                 optee {
 565                         compatible = "linaro,optee-tz";
 566                         method = "smc";
 567                 };
 568         };
 569 };