1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC device tree source
5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
9 * values for board specific bindings.
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
13 * additional nodes can be added to this file.
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 compatible = "samsung,exynos5433";
24 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a53-pmu";
28 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
36 compatible = "arm,cortex-a57-pmu";
37 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
41 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
46 compatible = "fixed-clock";
47 clock-output-names = "oscclk";
89 compatible = "arm,cortex-a53";
90 enable-method = "psci";
92 clock-frequency = <1300000000>;
93 clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
94 clock-names = "apolloclk";
95 operating-points-v2 = <&cluster_a53_opp_table>;
97 i-cache-size = <0x8000>;
98 i-cache-line-size = <64>;
100 d-cache-size = <0x8000>;
101 d-cache-line-size = <64>;
102 d-cache-sets = <128>;
103 next-level-cache = <&cluster_a53_l2>;
108 compatible = "arm,cortex-a53";
109 enable-method = "psci";
111 clock-frequency = <1300000000>;
112 operating-points-v2 = <&cluster_a53_opp_table>;
113 #cooling-cells = <2>;
114 i-cache-size = <0x8000>;
115 i-cache-line-size = <64>;
116 i-cache-sets = <256>;
117 d-cache-size = <0x8000>;
118 d-cache-line-size = <64>;
119 d-cache-sets = <128>;
120 next-level-cache = <&cluster_a53_l2>;
125 compatible = "arm,cortex-a53";
126 enable-method = "psci";
128 clock-frequency = <1300000000>;
129 operating-points-v2 = <&cluster_a53_opp_table>;
130 #cooling-cells = <2>;
131 i-cache-size = <0x8000>;
132 i-cache-line-size = <64>;
133 i-cache-sets = <256>;
134 d-cache-size = <0x8000>;
135 d-cache-line-size = <64>;
136 d-cache-sets = <128>;
137 next-level-cache = <&cluster_a53_l2>;
142 compatible = "arm,cortex-a53";
143 enable-method = "psci";
145 clock-frequency = <1300000000>;
146 operating-points-v2 = <&cluster_a53_opp_table>;
147 #cooling-cells = <2>;
148 i-cache-size = <0x8000>;
149 i-cache-line-size = <64>;
150 i-cache-sets = <256>;
151 d-cache-size = <0x8000>;
152 d-cache-line-size = <64>;
153 d-cache-sets = <128>;
154 next-level-cache = <&cluster_a53_l2>;
159 compatible = "arm,cortex-a57";
160 enable-method = "psci";
162 clock-frequency = <1900000000>;
163 clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
164 clock-names = "atlasclk";
165 operating-points-v2 = <&cluster_a57_opp_table>;
166 #cooling-cells = <2>;
167 i-cache-size = <0xc000>;
168 i-cache-line-size = <64>;
169 i-cache-sets = <256>;
170 d-cache-size = <0x8000>;
171 d-cache-line-size = <64>;
172 d-cache-sets = <256>;
173 next-level-cache = <&cluster_a57_l2>;
178 compatible = "arm,cortex-a57";
179 enable-method = "psci";
181 clock-frequency = <1900000000>;
182 operating-points-v2 = <&cluster_a57_opp_table>;
183 #cooling-cells = <2>;
184 i-cache-size = <0xc000>;
185 i-cache-line-size = <64>;
186 i-cache-sets = <256>;
187 d-cache-size = <0x8000>;
188 d-cache-line-size = <64>;
189 d-cache-sets = <256>;
190 next-level-cache = <&cluster_a57_l2>;
195 compatible = "arm,cortex-a57";
196 enable-method = "psci";
198 clock-frequency = <1900000000>;
199 operating-points-v2 = <&cluster_a57_opp_table>;
200 #cooling-cells = <2>;
201 i-cache-size = <0xc000>;
202 i-cache-line-size = <64>;
203 i-cache-sets = <256>;
204 d-cache-size = <0x8000>;
205 d-cache-line-size = <64>;
206 d-cache-sets = <256>;
207 next-level-cache = <&cluster_a57_l2>;
212 compatible = "arm,cortex-a57";
213 enable-method = "psci";
215 clock-frequency = <1900000000>;
216 operating-points-v2 = <&cluster_a57_opp_table>;
217 #cooling-cells = <2>;
218 i-cache-size = <0xc000>;
219 i-cache-line-size = <64>;
220 i-cache-sets = <256>;
221 d-cache-size = <0x8000>;
222 d-cache-line-size = <64>;
223 d-cache-sets = <256>;
224 next-level-cache = <&cluster_a57_l2>;
227 cluster_a57_l2: l2-cache0 {
228 compatible = "cache";
229 cache-size = <0x200000>;
230 cache-line-size = <64>;
234 cluster_a53_l2: l2-cache1 {
235 compatible = "cache";
236 cache-size = <0x40000>;
237 cache-line-size = <64>;
242 cluster_a53_opp_table: opp-table0 {
243 compatible = "operating-points-v2";
247 opp-hz = /bits/ 64 <400000000>;
248 opp-microvolt = <900000>;
251 opp-hz = /bits/ 64 <500000000>;
252 opp-microvolt = <925000>;
255 opp-hz = /bits/ 64 <600000000>;
256 opp-microvolt = <950000>;
259 opp-hz = /bits/ 64 <700000000>;
260 opp-microvolt = <975000>;
263 opp-hz = /bits/ 64 <800000000>;
264 opp-microvolt = <1000000>;
267 opp-hz = /bits/ 64 <900000000>;
268 opp-microvolt = <1050000>;
271 opp-hz = /bits/ 64 <1000000000>;
272 opp-microvolt = <1075000>;
275 opp-hz = /bits/ 64 <1100000000>;
276 opp-microvolt = <1112500>;
279 opp-hz = /bits/ 64 <1200000000>;
280 opp-microvolt = <1112500>;
283 opp-hz = /bits/ 64 <1300000000>;
284 opp-microvolt = <1150000>;
288 cluster_a57_opp_table: opp-table1 {
289 compatible = "operating-points-v2";
293 opp-hz = /bits/ 64 <500000000>;
294 opp-microvolt = <900000>;
297 opp-hz = /bits/ 64 <600000000>;
298 opp-microvolt = <900000>;
301 opp-hz = /bits/ 64 <700000000>;
302 opp-microvolt = <912500>;
305 opp-hz = /bits/ 64 <800000000>;
306 opp-microvolt = <912500>;
309 opp-hz = /bits/ 64 <900000000>;
310 opp-microvolt = <937500>;
313 opp-hz = /bits/ 64 <1000000000>;
314 opp-microvolt = <975000>;
317 opp-hz = /bits/ 64 <1100000000>;
318 opp-microvolt = <1012500>;
321 opp-hz = /bits/ 64 <1200000000>;
322 opp-microvolt = <1037500>;
325 opp-hz = /bits/ 64 <1300000000>;
326 opp-microvolt = <1062500>;
329 opp-hz = /bits/ 64 <1400000000>;
330 opp-microvolt = <1087500>;
333 opp-hz = /bits/ 64 <1500000000>;
334 opp-microvolt = <1125000>;
337 opp-hz = /bits/ 64 <1600000000>;
338 opp-microvolt = <1137500>;
341 opp-hz = /bits/ 64 <1700000000>;
342 opp-microvolt = <1175000>;
345 opp-hz = /bits/ 64 <1800000000>;
346 opp-microvolt = <1212500>;
349 opp-hz = /bits/ 64 <1900000000>;
350 opp-microvolt = <1262500>;
355 compatible = "arm,psci";
357 cpu_off = <0x84000002>;
358 cpu_on = <0xC4000003>;
362 compatible = "simple-bus";
363 #address-cells = <1>;
365 ranges = <0x0 0x0 0x0 0x18000000>;
368 compatible = "samsung,exynos4210-chipid";
369 reg = <0x10000000 0x100>;
372 cmu_top: clock-controller@10030000 {
373 compatible = "samsung,exynos5433-cmu-top";
374 reg = <0x10030000 0x1000>;
377 clock-names = "oscclk",
382 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
383 <&cmu_mif CLK_SCLK_MFC_PLL>,
384 <&cmu_mif CLK_SCLK_BUS_PLL>;
387 cmu_cpif: clock-controller@10fc0000 {
388 compatible = "samsung,exynos5433-cmu-cpif";
389 reg = <0x10fc0000 0x1000>;
392 clock-names = "oscclk";
396 cmu_mif: clock-controller@105b0000 {
397 compatible = "samsung,exynos5433-cmu-mif";
398 reg = <0x105b0000 0x2000>;
401 clock-names = "oscclk",
404 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
407 cmu_peric: clock-controller@14c80000 {
408 compatible = "samsung,exynos5433-cmu-peric";
409 reg = <0x14c80000 0x1000>;
413 cmu_peris: clock-controller@10040000 {
414 compatible = "samsung,exynos5433-cmu-peris";
415 reg = <0x10040000 0x1000>;
419 cmu_fsys: clock-controller@156e0000 {
420 compatible = "samsung,exynos5433-cmu-fsys";
421 reg = <0x156e0000 0x1000>;
424 clock-names = "oscclk",
427 "sclk_pcie_100_fsys",
428 "sclk_ufsunipro_fsys",
432 "sclk_usbhost30_fsys",
433 "sclk_usbdrd30_fsys";
435 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
436 <&cmu_top CLK_ACLK_FSYS_200>,
437 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
438 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
439 <&cmu_top CLK_SCLK_MMC2_FSYS>,
440 <&cmu_top CLK_SCLK_MMC1_FSYS>,
441 <&cmu_top CLK_SCLK_MMC0_FSYS>,
442 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
443 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
446 cmu_g2d: clock-controller@12460000 {
447 compatible = "samsung,exynos5433-cmu-g2d";
448 reg = <0x12460000 0x1000>;
451 clock-names = "oscclk",
455 <&cmu_top CLK_ACLK_G2D_266>,
456 <&cmu_top CLK_ACLK_G2D_400>;
457 power-domains = <&pd_g2d>;
460 cmu_disp: clock-controller@13b90000 {
461 compatible = "samsung,exynos5433-cmu-disp";
462 reg = <0x13b90000 0x1000>;
465 clock-names = "oscclk",
469 "sclk_decon_tv_eclk_disp",
470 "sclk_decon_vclk_disp",
471 "sclk_decon_eclk_disp",
472 "sclk_decon_tv_vclk_disp",
475 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
476 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
477 <&cmu_mif CLK_SCLK_DSD_DISP>,
478 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
479 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
480 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
481 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
482 <&cmu_mif CLK_ACLK_DISP_333>;
483 power-domains = <&pd_disp>;
486 cmu_aud: clock-controller@114c0000 {
487 compatible = "samsung,exynos5433-cmu-aud";
488 reg = <0x114c0000 0x1000>;
490 clock-names = "oscclk", "fout_aud_pll";
491 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
492 power-domains = <&pd_aud>;
495 cmu_bus0: clock-controller@13600000 {
496 compatible = "samsung,exynos5433-cmu-bus0";
497 reg = <0x13600000 0x1000>;
500 clock-names = "aclk_bus0_400";
501 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
504 cmu_bus1: clock-controller@14800000 {
505 compatible = "samsung,exynos5433-cmu-bus1";
506 reg = <0x14800000 0x1000>;
509 clock-names = "aclk_bus1_400";
510 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
513 cmu_bus2: clock-controller@13400000 {
514 compatible = "samsung,exynos5433-cmu-bus2";
515 reg = <0x13400000 0x1000>;
518 clock-names = "oscclk", "aclk_bus2_400";
519 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
522 cmu_g3d: clock-controller@14aa0000 {
523 compatible = "samsung,exynos5433-cmu-g3d";
524 reg = <0x14aa0000 0x2000>;
527 clock-names = "oscclk", "aclk_g3d_400";
528 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
529 power-domains = <&pd_g3d>;
532 cmu_gscl: clock-controller@13cf0000 {
533 compatible = "samsung,exynos5433-cmu-gscl";
534 reg = <0x13cf0000 0x1000>;
537 clock-names = "oscclk",
541 <&cmu_top CLK_ACLK_GSCL_111>,
542 <&cmu_top CLK_ACLK_GSCL_333>;
543 power-domains = <&pd_gscl>;
546 cmu_apollo: clock-controller@11900000 {
547 compatible = "samsung,exynos5433-cmu-apollo";
548 reg = <0x11900000 0x2000>;
551 clock-names = "oscclk", "sclk_bus_pll_apollo";
552 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
555 cmu_atlas: clock-controller@11800000 {
556 compatible = "samsung,exynos5433-cmu-atlas";
557 reg = <0x11800000 0x2000>;
560 clock-names = "oscclk", "sclk_bus_pll_atlas";
561 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
564 cmu_mscl: clock-controller@150d0000 {
565 compatible = "samsung,exynos5433-cmu-mscl";
566 reg = <0x150d0000 0x1000>;
569 clock-names = "oscclk",
573 <&cmu_top CLK_SCLK_JPEG_MSCL>,
574 <&cmu_top CLK_ACLK_MSCL_400>;
575 power-domains = <&pd_mscl>;
578 cmu_mfc: clock-controller@15280000 {
579 compatible = "samsung,exynos5433-cmu-mfc";
580 reg = <0x15280000 0x1000>;
583 clock-names = "oscclk", "aclk_mfc_400";
584 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
585 power-domains = <&pd_mfc>;
588 cmu_hevc: clock-controller@14f80000 {
589 compatible = "samsung,exynos5433-cmu-hevc";
590 reg = <0x14f80000 0x1000>;
593 clock-names = "oscclk", "aclk_hevc_400";
594 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
595 power-domains = <&pd_hevc>;
598 cmu_isp: clock-controller@146d0000 {
599 compatible = "samsung,exynos5433-cmu-isp";
600 reg = <0x146d0000 0x1000>;
603 clock-names = "oscclk",
607 <&cmu_top CLK_ACLK_ISP_DIS_400>,
608 <&cmu_top CLK_ACLK_ISP_400>;
609 power-domains = <&pd_isp>;
612 cmu_cam0: clock-controller@120d0000 {
613 compatible = "samsung,exynos5433-cmu-cam0";
614 reg = <0x120d0000 0x1000>;
617 clock-names = "oscclk",
622 <&cmu_top CLK_ACLK_CAM0_333>,
623 <&cmu_top CLK_ACLK_CAM0_400>,
624 <&cmu_top CLK_ACLK_CAM0_552>;
625 power-domains = <&pd_cam0>;
628 cmu_cam1: clock-controller@145d0000 {
629 compatible = "samsung,exynos5433-cmu-cam1";
630 reg = <0x145d0000 0x1000>;
633 clock-names = "oscclk",
634 "sclk_isp_uart_cam1",
635 "sclk_isp_spi1_cam1",
636 "sclk_isp_spi0_cam1",
641 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
642 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
643 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
644 <&cmu_top CLK_ACLK_CAM1_333>,
645 <&cmu_top CLK_ACLK_CAM1_400>,
646 <&cmu_top CLK_ACLK_CAM1_552>;
647 power-domains = <&pd_cam1>;
650 cmu_imem: clock-controller@11060000 {
651 compatible = "samsung,exynos5433-cmu-imem";
652 reg = <0x11060000 0x1000>;
655 clock-names = "oscclk",
656 "aclk_imem_sssx_266",
660 <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
661 <&cmu_top CLK_DIV_ACLK_IMEM_266>,
662 <&cmu_top CLK_DIV_ACLK_IMEM_200>;
665 slim_sss: slim-sss@11140000 {
666 compatible = "samsung,exynos5433-slim-sss";
667 reg = <0x11140000 0x1000>;
668 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
669 clock-names = "pclk", "aclk";
670 clocks = <&cmu_imem CLK_PCLK_SLIMSSS>,
671 <&cmu_imem CLK_ACLK_SLIMSSS>;
674 pd_gscl: power-domain@105c4000 {
675 compatible = "samsung,exynos5433-pd";
676 reg = <0x105c4000 0x20>;
677 #power-domain-cells = <0>;
681 pd_cam0: power-domain@105c4020 {
682 compatible = "samsung,exynos5433-pd";
683 reg = <0x105c4020 0x20>;
684 #power-domain-cells = <0>;
685 power-domains = <&pd_cam1>;
689 pd_mscl: power-domain@105c4040 {
690 compatible = "samsung,exynos5433-pd";
691 reg = <0x105c4040 0x20>;
692 #power-domain-cells = <0>;
696 pd_g3d: power-domain@105c4060 {
697 compatible = "samsung,exynos5433-pd";
698 reg = <0x105c4060 0x20>;
699 #power-domain-cells = <0>;
703 pd_disp: power-domain@105c4080 {
704 compatible = "samsung,exynos5433-pd";
705 reg = <0x105c4080 0x20>;
706 #power-domain-cells = <0>;
710 pd_cam1: power-domain@105c40a0 {
711 compatible = "samsung,exynos5433-pd";
712 reg = <0x105c40a0 0x20>;
713 #power-domain-cells = <0>;
717 pd_aud: power-domain@105c40c0 {
718 compatible = "samsung,exynos5433-pd";
719 reg = <0x105c40c0 0x20>;
720 #power-domain-cells = <0>;
724 pd_g2d: power-domain@105c4120 {
725 compatible = "samsung,exynos5433-pd";
726 reg = <0x105c4120 0x20>;
727 #power-domain-cells = <0>;
731 pd_isp: power-domain@105c4140 {
732 compatible = "samsung,exynos5433-pd";
733 reg = <0x105c4140 0x20>;
734 #power-domain-cells = <0>;
735 power-domains = <&pd_cam0>;
739 pd_mfc: power-domain@105c4180 {
740 compatible = "samsung,exynos5433-pd";
741 reg = <0x105c4180 0x20>;
742 #power-domain-cells = <0>;
746 pd_hevc: power-domain@105c41c0 {
747 compatible = "samsung,exynos5433-pd";
748 reg = <0x105c41c0 0x20>;
749 #power-domain-cells = <0>;
753 tmu_atlas0: tmu@10060000 {
754 compatible = "samsung,exynos5433-tmu";
755 reg = <0x10060000 0x200>;
756 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
758 <&cmu_peris CLK_SCLK_TMU0>;
759 clock-names = "tmu_apbif", "tmu_sclk";
760 #thermal-sensor-cells = <0>;
764 tmu_atlas1: tmu@10068000 {
765 compatible = "samsung,exynos5433-tmu";
766 reg = <0x10068000 0x200>;
767 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
769 <&cmu_peris CLK_SCLK_TMU0>;
770 clock-names = "tmu_apbif", "tmu_sclk";
771 #thermal-sensor-cells = <0>;
775 tmu_g3d: tmu@10070000 {
776 compatible = "samsung,exynos5433-tmu";
777 reg = <0x10070000 0x200>;
778 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
780 <&cmu_peris CLK_SCLK_TMU1>;
781 clock-names = "tmu_apbif", "tmu_sclk";
782 #thermal-sensor-cells = <0>;
786 tmu_apollo: tmu@10078000 {
787 compatible = "samsung,exynos5433-tmu";
788 reg = <0x10078000 0x200>;
789 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
791 <&cmu_peris CLK_SCLK_TMU1>;
792 clock-names = "tmu_apbif", "tmu_sclk";
793 #thermal-sensor-cells = <0>;
797 tmu_isp: tmu@1007c000 {
798 compatible = "samsung,exynos5433-tmu";
799 reg = <0x1007c000 0x200>;
800 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
802 <&cmu_peris CLK_SCLK_TMU1>;
803 clock-names = "tmu_apbif", "tmu_sclk";
804 #thermal-sensor-cells = <0>;
809 compatible = "samsung,exynos4210-mct";
810 reg = <0x101c0000 0x800>;
811 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
819 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
824 clock-names = "fin_pll", "mct";
827 ppmu_d0_cpu: ppmu@10480000 {
828 compatible = "samsung,exynos-ppmu-v2";
829 reg = <0x10480000 0x2000>;
833 ppmu_d0_general: ppmu@10490000 {
834 compatible = "samsung,exynos-ppmu-v2";
835 reg = <0x10490000 0x2000>;
839 ppmu_d1_cpu: ppmu@104b0000 {
840 compatible = "samsung,exynos-ppmu-v2";
841 reg = <0x104b0000 0x2000>;
845 ppmu_d1_general: ppmu@104c0000 {
846 compatible = "samsung,exynos-ppmu-v2";
847 reg = <0x104c0000 0x2000>;
851 pinctrl_alive: pinctrl@10580000 {
852 compatible = "samsung,exynos5433-pinctrl";
853 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
855 wakeup-interrupt-controller {
856 compatible = "samsung,exynos7-wakeup-eint";
857 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
861 pinctrl_aud: pinctrl@114b0000 {
862 compatible = "samsung,exynos5433-pinctrl";
863 reg = <0x114b0000 0x1000>;
864 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
865 power-domains = <&pd_aud>;
868 pinctrl_cpif: pinctrl@10fe0000 {
869 compatible = "samsung,exynos5433-pinctrl";
870 reg = <0x10fe0000 0x1000>;
871 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
874 pinctrl_ese: pinctrl@14ca0000 {
875 compatible = "samsung,exynos5433-pinctrl";
876 reg = <0x14ca0000 0x1000>;
877 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
880 pinctrl_finger: pinctrl@14cb0000 {
881 compatible = "samsung,exynos5433-pinctrl";
882 reg = <0x14cb0000 0x1000>;
883 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
886 pinctrl_fsys: pinctrl@15690000 {
887 compatible = "samsung,exynos5433-pinctrl";
888 reg = <0x15690000 0x1000>;
889 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
892 pinctrl_imem: pinctrl@11090000 {
893 compatible = "samsung,exynos5433-pinctrl";
894 reg = <0x11090000 0x1000>;
895 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
898 pinctrl_nfc: pinctrl@14cd0000 {
899 compatible = "samsung,exynos5433-pinctrl";
900 reg = <0x14cd0000 0x1000>;
901 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
904 pinctrl_peric: pinctrl@14cc0000 {
905 compatible = "samsung,exynos5433-pinctrl";
906 reg = <0x14cc0000 0x1100>;
907 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
910 pinctrl_touch: pinctrl@14ce0000 {
911 compatible = "samsung,exynos5433-pinctrl";
912 reg = <0x14ce0000 0x1100>;
913 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
916 pmu_system_controller: system-controller@105c0000 {
917 compatible = "samsung,exynos5433-pmu", "syscon";
918 reg = <0x105c0000 0x5008>;
920 clock-names = "clkout16";
923 reboot: syscon-reboot {
924 compatible = "syscon-reboot";
925 regmap = <&pmu_system_controller>;
926 offset = <0x400>; /* SWRESET */
931 gic: interrupt-controller@11001000 {
932 compatible = "arm,gic-400";
933 #interrupt-cells = <3>;
934 interrupt-controller;
935 reg = <0x11001000 0x1000>,
939 interrupts = <GIC_PPI 9 0xf04>;
942 mipi_phy: video-phy {
943 compatible = "samsung,exynos5433-mipi-video-phy";
945 samsung,pmu-syscon = <&pmu_system_controller>;
946 samsung,cam0-sysreg = <&syscon_cam0>;
947 samsung,cam1-sysreg = <&syscon_cam1>;
948 samsung,disp-sysreg = <&syscon_disp>;
951 decon: decon@13800000 {
952 compatible = "samsung,exynos5433-decon";
953 reg = <0x13800000 0x2104>;
954 clocks = <&cmu_disp CLK_PCLK_DECON>,
955 <&cmu_disp CLK_ACLK_DECON>,
956 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
957 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
958 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
959 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
960 <&cmu_disp CLK_ACLK_XIU_DECON1X>,
961 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
962 <&cmu_disp CLK_SCLK_DECON_VCLK>,
963 <&cmu_disp CLK_SCLK_DECON_ECLK>,
964 <&cmu_disp CLK_SCLK_DSD>;
965 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
966 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
967 "aclk_smmu_decon1x", "aclk_xiu_decon1x",
968 "pclk_smmu_decon1x", "sclk_decon_vclk",
969 "sclk_decon_eclk", "dsd";
970 power-domains = <&pd_disp>;
971 interrupt-names = "fifo", "vsync", "lcd_sys";
972 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
975 samsung,disp-sysreg = <&syscon_disp>;
977 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
978 iommu-names = "m0", "m1";
981 #address-cells = <1>;
986 decon_to_mic: endpoint {
994 decon_tv: decon@13880000 {
995 compatible = "samsung,exynos5433-decon-tv";
996 reg = <0x13880000 0x20b8>;
997 clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
998 <&cmu_disp CLK_ACLK_DECON_TV>,
999 <&cmu_disp CLK_ACLK_SMMU_TV0X>,
1000 <&cmu_disp CLK_ACLK_XIU_TV0X>,
1001 <&cmu_disp CLK_PCLK_SMMU_TV0X>,
1002 <&cmu_disp CLK_ACLK_SMMU_TV1X>,
1003 <&cmu_disp CLK_ACLK_XIU_TV1X>,
1004 <&cmu_disp CLK_PCLK_SMMU_TV1X>,
1005 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
1006 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>,
1007 <&cmu_disp CLK_SCLK_DSD>;
1008 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
1009 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
1010 "aclk_smmu_decon1x", "aclk_xiu_decon1x",
1011 "pclk_smmu_decon1x", "sclk_decon_vclk",
1012 "sclk_decon_eclk", "dsd";
1013 samsung,disp-sysreg = <&syscon_disp>;
1014 power-domains = <&pd_disp>;
1015 interrupt-names = "fifo", "vsync", "lcd_sys";
1016 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1018 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1019 status = "disabled";
1020 iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
1021 iommu-names = "m0", "m1";
1025 compatible = "samsung,exynos5433-mipi-dsi";
1026 reg = <0x13900000 0xC0>;
1027 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1028 phys = <&mipi_phy 1>;
1030 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
1031 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
1032 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
1033 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
1034 <&cmu_disp CLK_SCLK_DSIM0>;
1035 clock-names = "bus_clk",
1036 "phyclk_mipidphy0_bitclkdiv8",
1037 "phyclk_mipidphy0_rxclkesc0",
1038 "sclk_rgb_vclk_to_dsim0",
1040 power-domains = <&pd_disp>;
1041 status = "disabled";
1042 #address-cells = <1>;
1046 #address-cells = <1>;
1051 dsi_to_mic: endpoint {
1052 remote-endpoint = <&mic_to_dsi>;
1059 compatible = "samsung,exynos5433-mic";
1060 reg = <0x13930000 0x48>;
1061 clocks = <&cmu_disp CLK_PCLK_MIC0>,
1062 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
1063 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
1064 power-domains = <&pd_disp>;
1065 samsung,disp-syscon = <&syscon_disp>;
1066 status = "disabled";
1069 #address-cells = <1>;
1074 mic_to_decon: endpoint {
1082 mic_to_dsi: endpoint {
1083 remote-endpoint = <&dsi_to_mic>;
1089 hdmi: hdmi@13970000 {
1090 compatible = "samsung,exynos5433-hdmi";
1091 reg = <0x13970000 0x70000>;
1092 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&cmu_disp CLK_PCLK_HDMI>,
1094 <&cmu_disp CLK_PCLK_HDMIPHY>,
1095 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
1096 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
1097 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
1098 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
1099 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
1100 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
1101 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
1102 clock-names = "hdmi_pclk", "hdmi_i_pclk",
1103 "i_tmds_clk", "i_pixel_clk",
1104 "tmds_clko", "tmds_clko_user",
1105 "pixel_clko", "pixel_clko_user",
1106 "oscclk", "i_spdif_clk";
1109 samsung,syscon-phandle = <&pmu_system_controller>;
1110 samsung,sysreg-phandle = <&syscon_disp>;
1111 #sound-dai-cells = <0>;
1112 status = "disabled";
1115 hdmiphy: hdmiphy@13af0000 {
1116 reg = <0x13af0000 0x80>;
1119 syscon_disp: syscon@13b80000 {
1120 compatible = "samsung,exynos5433-sysreg", "syscon";
1121 reg = <0x13b80000 0x1010>;
1124 syscon_cam0: syscon@120f0000 {
1125 compatible = "samsung,exynos5433-sysreg", "syscon";
1126 reg = <0x120f0000 0x1020>;
1129 syscon_cam1: syscon@145f0000 {
1130 compatible = "samsung,exynos5433-sysreg", "syscon";
1131 reg = <0x145f0000 0x1038>;
1134 syscon_fsys: syscon@156f0000 {
1135 compatible = "syscon";
1136 reg = <0x156f0000 0x1044>;
1139 gsc_0: video-scaler@13c00000 {
1140 compatible = "samsung,exynos5433-gsc";
1141 reg = <0x13c00000 0x1000>;
1142 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
1143 clock-names = "pclk", "aclk", "aclk_xiu",
1144 "aclk_gsclbend", "gsd";
1145 clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
1146 <&cmu_gscl CLK_ACLK_GSCL0>,
1147 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1148 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1149 <&cmu_gscl CLK_ACLK_GSD>;
1150 iommus = <&sysmmu_gscl0>;
1151 power-domains = <&pd_gscl>;
1154 gsc_1: video-scaler@13c10000 {
1155 compatible = "samsung,exynos5433-gsc";
1156 reg = <0x13c10000 0x1000>;
1157 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1158 clock-names = "pclk", "aclk", "aclk_xiu",
1159 "aclk_gsclbend", "gsd";
1160 clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
1161 <&cmu_gscl CLK_ACLK_GSCL1>,
1162 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1163 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1164 <&cmu_gscl CLK_ACLK_GSD>;
1165 iommus = <&sysmmu_gscl1>;
1166 power-domains = <&pd_gscl>;
1169 gsc_2: video-scaler@13c20000 {
1170 compatible = "samsung,exynos5433-gsc";
1171 reg = <0x13c20000 0x1000>;
1172 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1173 clock-names = "pclk", "aclk", "aclk_xiu",
1174 "aclk_gsclbend", "gsd";
1175 clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
1176 <&cmu_gscl CLK_ACLK_GSCL2>,
1177 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1178 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1179 <&cmu_gscl CLK_ACLK_GSD>;
1180 iommus = <&sysmmu_gscl2>;
1181 power-domains = <&pd_gscl>;
1185 compatible = "samsung,exynos5433-mali", "arm,mali-t760";
1186 reg = <0x14ac0000 0x5000>;
1187 interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
1190 interrupt-names = "job", "mmu", "gpu";
1191 clocks = <&cmu_g3d CLK_ACLK_G3D>;
1192 clock-names = "core";
1193 power-domains = <&pd_g3d>;
1194 operating-points-v2 = <&gpu_opp_table>;
1195 status = "disabled";
1197 gpu_opp_table: opp-table {
1198 compatible = "operating-points-v2";
1201 opp-hz = /bits/ 64 <160000000>;
1202 opp-microvolt = <1000000>;
1205 opp-hz = /bits/ 64 <267000000>;
1206 opp-microvolt = <1000000>;
1209 opp-hz = /bits/ 64 <350000000>;
1210 opp-microvolt = <1025000>;
1213 opp-hz = /bits/ 64 <420000000>;
1214 opp-microvolt = <1025000>;
1217 opp-hz = /bits/ 64 <500000000>;
1218 opp-microvolt = <1075000>;
1221 opp-hz = /bits/ 64 <550000000>;
1222 opp-microvolt = <1125000>;
1225 opp-hz = /bits/ 64 <600000000>;
1226 opp-microvolt = <1150000>;
1229 opp-hz = /bits/ 64 <700000000>;
1230 opp-microvolt = <1150000>;
1235 scaler_0: scaler@15000000 {
1236 compatible = "samsung,exynos5433-scaler";
1237 reg = <0x15000000 0x1294>;
1238 interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>;
1239 clock-names = "pclk", "aclk", "aclk_xiu";
1240 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>,
1241 <&cmu_mscl CLK_ACLK_M2MSCALER0>,
1242 <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1243 iommus = <&sysmmu_scaler_0>;
1244 power-domains = <&pd_mscl>;
1247 scaler_1: scaler@15010000 {
1248 compatible = "samsung,exynos5433-scaler";
1249 reg = <0x15010000 0x1294>;
1250 interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>;
1251 clock-names = "pclk", "aclk", "aclk_xiu";
1252 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>,
1253 <&cmu_mscl CLK_ACLK_M2MSCALER1>,
1254 <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1255 iommus = <&sysmmu_scaler_1>;
1256 power-domains = <&pd_mscl>;
1259 jpeg: codec@15020000 {
1260 compatible = "samsung,exynos5433-jpeg";
1261 reg = <0x15020000 0x10000>;
1262 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
1263 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
1264 clocks = <&cmu_mscl CLK_PCLK_JPEG>,
1265 <&cmu_mscl CLK_ACLK_JPEG>,
1266 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
1267 <&cmu_mscl CLK_SCLK_JPEG>;
1268 iommus = <&sysmmu_jpeg>;
1269 power-domains = <&pd_mscl>;
1272 mfc: codec@152e0000 {
1273 compatible = "samsung,exynos5433-mfc";
1274 reg = <0x152E0000 0x10000>;
1275 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1276 clock-names = "pclk", "aclk", "aclk_xiu";
1277 clocks = <&cmu_mfc CLK_PCLK_MFC>,
1278 <&cmu_mfc CLK_ACLK_MFC>,
1279 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
1280 iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
1281 iommu-names = "left", "right";
1282 power-domains = <&pd_mfc>;
1285 sysmmu_decon0x: sysmmu@13a00000 {
1286 compatible = "samsung,exynos-sysmmu";
1287 reg = <0x13a00000 0x1000>;
1288 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1289 clock-names = "aclk", "pclk";
1290 clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
1291 <&cmu_disp CLK_PCLK_SMMU_DECON0X>;
1292 power-domains = <&pd_disp>;
1296 sysmmu_decon1x: sysmmu@13a10000 {
1297 compatible = "samsung,exynos-sysmmu";
1298 reg = <0x13a10000 0x1000>;
1299 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1300 clock-names = "aclk", "pclk";
1301 clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
1302 <&cmu_disp CLK_PCLK_SMMU_DECON1X>;
1304 power-domains = <&pd_disp>;
1307 sysmmu_tv0x: sysmmu@13a20000 {
1308 compatible = "samsung,exynos-sysmmu";
1309 reg = <0x13a20000 0x1000>;
1310 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
1311 clock-names = "aclk", "pclk";
1312 clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>,
1313 <&cmu_disp CLK_PCLK_SMMU_TV0X>;
1315 power-domains = <&pd_disp>;
1318 sysmmu_tv1x: sysmmu@13a30000 {
1319 compatible = "samsung,exynos-sysmmu";
1320 reg = <0x13a30000 0x1000>;
1321 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1322 clock-names = "aclk", "pclk";
1323 clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>,
1324 <&cmu_disp CLK_PCLK_SMMU_TV1X>;
1326 power-domains = <&pd_disp>;
1329 sysmmu_gscl0: sysmmu@13c80000 {
1330 compatible = "samsung,exynos-sysmmu";
1331 reg = <0x13C80000 0x1000>;
1332 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
1333 clock-names = "aclk", "pclk";
1334 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
1335 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
1337 power-domains = <&pd_gscl>;
1340 sysmmu_gscl1: sysmmu@13c90000 {
1341 compatible = "samsung,exynos-sysmmu";
1342 reg = <0x13C90000 0x1000>;
1343 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1344 clock-names = "aclk", "pclk";
1345 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
1346 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
1348 power-domains = <&pd_gscl>;
1351 sysmmu_gscl2: sysmmu@13ca0000 {
1352 compatible = "samsung,exynos-sysmmu";
1353 reg = <0x13CA0000 0x1000>;
1354 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1355 clock-names = "aclk", "pclk";
1356 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
1357 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
1359 power-domains = <&pd_gscl>;
1362 sysmmu_scaler_0: sysmmu@15040000 {
1363 compatible = "samsung,exynos-sysmmu";
1364 reg = <0x15040000 0x1000>;
1365 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1366 clock-names = "aclk", "pclk";
1367 clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>,
1368 <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>;
1370 power-domains = <&pd_mscl>;
1373 sysmmu_scaler_1: sysmmu@15050000 {
1374 compatible = "samsung,exynos-sysmmu";
1375 reg = <0x15050000 0x1000>;
1376 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
1377 clock-names = "aclk", "pclk";
1378 clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>,
1379 <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>;
1381 power-domains = <&pd_mscl>;
1384 sysmmu_jpeg: sysmmu@15060000 {
1385 compatible = "samsung,exynos-sysmmu";
1386 reg = <0x15060000 0x1000>;
1387 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1388 clock-names = "aclk", "pclk";
1389 clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>,
1390 <&cmu_mscl CLK_PCLK_SMMU_JPEG>;
1392 power-domains = <&pd_mscl>;
1395 sysmmu_mfc_0: sysmmu@15200000 {
1396 compatible = "samsung,exynos-sysmmu";
1397 reg = <0x15200000 0x1000>;
1398 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1399 clock-names = "aclk", "pclk";
1400 clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>,
1401 <&cmu_mfc CLK_PCLK_SMMU_MFC_0>;
1403 power-domains = <&pd_mfc>;
1406 sysmmu_mfc_1: sysmmu@15210000 {
1407 compatible = "samsung,exynos-sysmmu";
1408 reg = <0x15210000 0x1000>;
1409 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1410 clock-names = "aclk", "pclk";
1411 clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>,
1412 <&cmu_mfc CLK_PCLK_SMMU_MFC_1>;
1414 power-domains = <&pd_mfc>;
1417 serial_0: serial@14c10000 {
1418 compatible = "samsung,exynos5433-uart";
1419 reg = <0x14c10000 0x100>;
1420 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&cmu_peric CLK_PCLK_UART0>,
1422 <&cmu_peric CLK_SCLK_UART0>;
1423 clock-names = "uart", "clk_uart_baud0";
1424 pinctrl-names = "default";
1425 pinctrl-0 = <&uart0_bus>;
1426 status = "disabled";
1429 serial_1: serial@14c20000 {
1430 compatible = "samsung,exynos5433-uart";
1431 reg = <0x14c20000 0x100>;
1432 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1433 clocks = <&cmu_peric CLK_PCLK_UART1>,
1434 <&cmu_peric CLK_SCLK_UART1>;
1435 clock-names = "uart", "clk_uart_baud0";
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&uart1_bus>;
1438 status = "disabled";
1441 serial_2: serial@14c30000 {
1442 compatible = "samsung,exynos5433-uart";
1443 reg = <0x14c30000 0x100>;
1444 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
1445 clocks = <&cmu_peric CLK_PCLK_UART2>,
1446 <&cmu_peric CLK_SCLK_UART2>;
1447 clock-names = "uart", "clk_uart_baud0";
1448 pinctrl-names = "default";
1449 pinctrl-0 = <&uart2_bus>;
1450 status = "disabled";
1453 spi_0: spi@14d20000 {
1454 compatible = "samsung,exynos5433-spi";
1455 reg = <0x14d20000 0x100>;
1456 interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
1457 dmas = <&pdma0 9>, <&pdma0 8>;
1458 dma-names = "tx", "rx";
1459 #address-cells = <1>;
1461 clocks = <&cmu_peric CLK_PCLK_SPI0>,
1462 <&cmu_peric CLK_SCLK_SPI0>,
1463 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
1464 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1465 samsung,spi-src-clk = <0>;
1466 pinctrl-names = "default";
1467 pinctrl-0 = <&spi0_bus>;
1469 status = "disabled";
1472 spi_1: spi@14d30000 {
1473 compatible = "samsung,exynos5433-spi";
1474 reg = <0x14d30000 0x100>;
1475 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1476 dmas = <&pdma0 11>, <&pdma0 10>;
1477 dma-names = "tx", "rx";
1478 #address-cells = <1>;
1480 clocks = <&cmu_peric CLK_PCLK_SPI1>,
1481 <&cmu_peric CLK_SCLK_SPI1>,
1482 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1483 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1484 samsung,spi-src-clk = <0>;
1485 pinctrl-names = "default";
1486 pinctrl-0 = <&spi1_bus>;
1488 status = "disabled";
1491 spi_2: spi@14d40000 {
1492 compatible = "samsung,exynos5433-spi";
1493 reg = <0x14d40000 0x100>;
1494 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1495 dmas = <&pdma0 13>, <&pdma0 12>;
1496 dma-names = "tx", "rx";
1497 #address-cells = <1>;
1499 clocks = <&cmu_peric CLK_PCLK_SPI2>,
1500 <&cmu_peric CLK_SCLK_SPI2>,
1501 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1502 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1503 samsung,spi-src-clk = <0>;
1504 pinctrl-names = "default";
1505 pinctrl-0 = <&spi2_bus>;
1507 status = "disabled";
1510 spi_3: spi@14d50000 {
1511 compatible = "samsung,exynos5433-spi";
1512 reg = <0x14d50000 0x100>;
1513 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1514 dmas = <&pdma0 23>, <&pdma0 22>;
1515 dma-names = "tx", "rx";
1516 #address-cells = <1>;
1518 clocks = <&cmu_peric CLK_PCLK_SPI3>,
1519 <&cmu_peric CLK_SCLK_SPI3>,
1520 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1521 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1522 samsung,spi-src-clk = <0>;
1523 pinctrl-names = "default";
1524 pinctrl-0 = <&spi3_bus>;
1526 status = "disabled";
1529 spi_4: spi@14d00000 {
1530 compatible = "samsung,exynos5433-spi";
1531 reg = <0x14d00000 0x100>;
1532 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1533 dmas = <&pdma0 25>, <&pdma0 24>;
1534 dma-names = "tx", "rx";
1535 #address-cells = <1>;
1537 clocks = <&cmu_peric CLK_PCLK_SPI4>,
1538 <&cmu_peric CLK_SCLK_SPI4>,
1539 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1540 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1541 samsung,spi-src-clk = <0>;
1542 pinctrl-names = "default";
1543 pinctrl-0 = <&spi4_bus>;
1545 status = "disabled";
1549 compatible = "samsung,exynos7-adc";
1550 reg = <0x14d10000 0x100>;
1551 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1552 clock-names = "adc";
1553 clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1554 #io-channel-cells = <1>;
1555 status = "disabled";
1558 i2s1: i2s@14d60000 {
1559 compatible = "samsung,exynos7-i2s";
1560 reg = <0x14d60000 0x100>;
1561 dmas = <&pdma0 31>, <&pdma0 30>;
1562 dma-names = "tx", "rx";
1563 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
1564 clocks = <&cmu_peric CLK_PCLK_I2S1>,
1565 <&cmu_peric CLK_PCLK_I2S1>,
1566 <&cmu_peric CLK_SCLK_I2S1>;
1567 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1569 #sound-dai-cells = <1>;
1570 status = "disabled";
1574 compatible = "samsung,exynos4210-pwm";
1575 reg = <0x14dd0000 0x100>;
1576 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1577 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1578 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1579 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1580 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1581 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1582 clocks = <&cmu_peric CLK_PCLK_PWM>;
1583 clock-names = "timers";
1585 status = "disabled";
1588 hsi2c_0: hsi2c@14e40000 {
1589 compatible = "samsung,exynos7-hsi2c";
1590 reg = <0x14e40000 0x1000>;
1591 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1592 #address-cells = <1>;
1594 pinctrl-names = "default";
1595 pinctrl-0 = <&hs_i2c0_bus>;
1596 clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1597 clock-names = "hsi2c";
1598 status = "disabled";
1601 hsi2c_1: hsi2c@14e50000 {
1602 compatible = "samsung,exynos7-hsi2c";
1603 reg = <0x14e50000 0x1000>;
1604 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1605 #address-cells = <1>;
1607 pinctrl-names = "default";
1608 pinctrl-0 = <&hs_i2c1_bus>;
1609 clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1610 clock-names = "hsi2c";
1611 status = "disabled";
1614 hsi2c_2: hsi2c@14e60000 {
1615 compatible = "samsung,exynos7-hsi2c";
1616 reg = <0x14e60000 0x1000>;
1617 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1618 #address-cells = <1>;
1620 pinctrl-names = "default";
1621 pinctrl-0 = <&hs_i2c2_bus>;
1622 clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1623 clock-names = "hsi2c";
1624 status = "disabled";
1627 hsi2c_3: hsi2c@14e70000 {
1628 compatible = "samsung,exynos7-hsi2c";
1629 reg = <0x14e70000 0x1000>;
1630 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1631 #address-cells = <1>;
1633 pinctrl-names = "default";
1634 pinctrl-0 = <&hs_i2c3_bus>;
1635 clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1636 clock-names = "hsi2c";
1637 status = "disabled";
1640 hsi2c_4: hsi2c@14ec0000 {
1641 compatible = "samsung,exynos7-hsi2c";
1642 reg = <0x14ec0000 0x1000>;
1643 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1644 #address-cells = <1>;
1646 pinctrl-names = "default";
1647 pinctrl-0 = <&hs_i2c4_bus>;
1648 clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1649 clock-names = "hsi2c";
1650 status = "disabled";
1653 hsi2c_5: hsi2c@14ed0000 {
1654 compatible = "samsung,exynos7-hsi2c";
1655 reg = <0x14ed0000 0x1000>;
1656 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1657 #address-cells = <1>;
1659 pinctrl-names = "default";
1660 pinctrl-0 = <&hs_i2c5_bus>;
1661 clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1662 clock-names = "hsi2c";
1663 status = "disabled";
1666 hsi2c_6: hsi2c@14ee0000 {
1667 compatible = "samsung,exynos7-hsi2c";
1668 reg = <0x14ee0000 0x1000>;
1669 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1670 #address-cells = <1>;
1672 pinctrl-names = "default";
1673 pinctrl-0 = <&hs_i2c6_bus>;
1674 clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1675 clock-names = "hsi2c";
1676 status = "disabled";
1679 hsi2c_7: hsi2c@14ef0000 {
1680 compatible = "samsung,exynos7-hsi2c";
1681 reg = <0x14ef0000 0x1000>;
1682 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cells = <1>;
1685 pinctrl-names = "default";
1686 pinctrl-0 = <&hs_i2c7_bus>;
1687 clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1688 clock-names = "hsi2c";
1689 status = "disabled";
1692 hsi2c_8: hsi2c@14d90000 {
1693 compatible = "samsung,exynos7-hsi2c";
1694 reg = <0x14d90000 0x1000>;
1695 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1696 #address-cells = <1>;
1698 pinctrl-names = "default";
1699 pinctrl-0 = <&hs_i2c8_bus>;
1700 clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1701 clock-names = "hsi2c";
1702 status = "disabled";
1705 hsi2c_9: hsi2c@14da0000 {
1706 compatible = "samsung,exynos7-hsi2c";
1707 reg = <0x14da0000 0x1000>;
1708 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1709 #address-cells = <1>;
1711 pinctrl-names = "default";
1712 pinctrl-0 = <&hs_i2c9_bus>;
1713 clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1714 clock-names = "hsi2c";
1715 status = "disabled";
1718 hsi2c_10: hsi2c@14de0000 {
1719 compatible = "samsung,exynos7-hsi2c";
1720 reg = <0x14de0000 0x1000>;
1721 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1722 #address-cells = <1>;
1724 pinctrl-names = "default";
1725 pinctrl-0 = <&hs_i2c10_bus>;
1726 clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1727 clock-names = "hsi2c";
1728 status = "disabled";
1731 hsi2c_11: hsi2c@14df0000 {
1732 compatible = "samsung,exynos7-hsi2c";
1733 reg = <0x14df0000 0x1000>;
1734 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1735 #address-cells = <1>;
1737 pinctrl-names = "default";
1738 pinctrl-0 = <&hs_i2c11_bus>;
1739 clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1740 clock-names = "hsi2c";
1741 status = "disabled";
1745 compatible = "samsung,exynos5433-dwusb3";
1746 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1747 <&cmu_fsys CLK_SCLK_USBDRD30>,
1748 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1749 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1750 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1751 #address-cells = <1>;
1754 status = "disabled";
1756 usbdrd_dwc3: usb@15400000 {
1757 compatible = "snps,dwc3";
1758 clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1759 <&cmu_fsys CLK_ACLK_USBDRD30>,
1760 <&cmu_fsys CLK_SCLK_USBDRD30>;
1761 clock-names = "ref", "bus_early", "suspend";
1762 reg = <0x15400000 0x10000>;
1763 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1764 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1765 phy-names = "usb2-phy", "usb3-phy";
1769 usbdrd30_phy: phy@15500000 {
1770 compatible = "samsung,exynos5433-usbdrd-phy";
1771 reg = <0x15500000 0x100>;
1772 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1773 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1774 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1775 <&cmu_fsys CLK_SCLK_USBDRD30>;
1776 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1779 samsung,pmu-syscon = <&pmu_system_controller>;
1780 status = "disabled";
1783 usbhost30_phy: phy@15580000 {
1784 compatible = "samsung,exynos5433-usbdrd-phy";
1785 reg = <0x15580000 0x100>;
1786 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1787 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1788 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1789 <&cmu_fsys CLK_SCLK_USBHOST30>;
1790 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1793 samsung,pmu-syscon = <&pmu_system_controller>;
1794 status = "disabled";
1797 usbhost30: usbhost {
1798 compatible = "samsung,exynos5433-dwusb3";
1799 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1800 <&cmu_fsys CLK_SCLK_USBHOST30>,
1801 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1802 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
1803 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1804 #address-cells = <1>;
1807 status = "disabled";
1809 usbhost_dwc3: usb@15a00000 {
1810 compatible = "snps,dwc3";
1811 clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
1812 <&cmu_fsys CLK_ACLK_USBHOST30>,
1813 <&cmu_fsys CLK_SCLK_USBHOST30>;
1814 clock-names = "ref", "bus_early", "suspend";
1815 reg = <0x15a00000 0x10000>;
1816 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1817 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1818 phy-names = "usb2-phy", "usb3-phy";
1822 mshc_0: mshc@15540000 {
1823 compatible = "samsung,exynos7-dw-mshc-smu";
1824 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1825 #address-cells = <1>;
1827 reg = <0x15540000 0x2000>;
1828 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1829 <&cmu_fsys CLK_SCLK_MMC0>;
1830 clock-names = "biu", "ciu";
1831 fifo-depth = <0x40>;
1832 status = "disabled";
1835 mshc_1: mshc@15550000 {
1836 compatible = "samsung,exynos7-dw-mshc-smu";
1837 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1838 #address-cells = <1>;
1840 reg = <0x15550000 0x2000>;
1841 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1842 <&cmu_fsys CLK_SCLK_MMC1>;
1843 clock-names = "biu", "ciu";
1844 fifo-depth = <0x40>;
1845 status = "disabled";
1848 mshc_2: mshc@15560000 {
1849 compatible = "samsung,exynos7-dw-mshc-smu";
1850 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1851 #address-cells = <1>;
1853 reg = <0x15560000 0x2000>;
1854 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1855 <&cmu_fsys CLK_SCLK_MMC2>;
1856 clock-names = "biu", "ciu";
1857 fifo-depth = <0x40>;
1858 status = "disabled";
1861 pdma0: pdma@15610000 {
1862 compatible = "arm,pl330", "arm,primecell";
1863 reg = <0x15610000 0x1000>;
1864 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1865 clocks = <&cmu_fsys CLK_PDMA0>;
1866 clock-names = "apb_pclk";
1868 #dma-channels = <8>;
1869 #dma-requests = <32>;
1872 pdma1: pdma@15600000 {
1873 compatible = "arm,pl330", "arm,primecell";
1874 reg = <0x15600000 0x1000>;
1875 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1876 clocks = <&cmu_fsys CLK_PDMA1>;
1877 clock-names = "apb_pclk";
1879 #dma-channels = <8>;
1880 #dma-requests = <32>;
1883 audio-subsystem@11400000 {
1884 compatible = "samsung,exynos5433-lpass";
1885 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1886 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1887 clock-names = "sfr0_ctrl";
1888 samsung,pmu-syscon = <&pmu_system_controller>;
1889 power-domains = <&pd_aud>;
1890 #address-cells = <1>;
1894 adma: adma@11420000 {
1895 compatible = "arm,pl330", "arm,primecell";
1896 reg = <0x11420000 0x1000>;
1897 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1898 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1899 clock-names = "apb_pclk";
1901 #dma-channels = <8>;
1902 #dma-requests = <32>;
1903 power-domains = <&pd_aud>;
1906 i2s0: i2s@11440000 {
1907 compatible = "samsung,exynos7-i2s";
1908 reg = <0x11440000 0x100>;
1909 dmas = <&adma 0>, <&adma 2>;
1910 dma-names = "tx", "rx";
1911 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1912 #address-cells = <1>;
1914 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1915 <&cmu_aud CLK_SCLK_AUD_I2S>,
1916 <&cmu_aud CLK_SCLK_I2S_BCLK>;
1917 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1919 pinctrl-names = "default";
1920 pinctrl-0 = <&i2s0_bus>;
1921 power-domains = <&pd_aud>;
1922 #sound-dai-cells = <1>;
1923 status = "disabled";
1926 serial_3: serial@11460000 {
1927 compatible = "samsung,exynos5433-uart";
1928 reg = <0x11460000 0x100>;
1929 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1930 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1931 <&cmu_aud CLK_SCLK_AUD_UART>;
1932 clock-names = "uart", "clk_uart_baud0";
1933 pinctrl-names = "default";
1934 pinctrl-0 = <&uart_aud_bus>;
1935 power-domains = <&pd_aud>;
1936 status = "disabled";
1940 pcie_phy: pcie-phy@15680000 {
1941 compatible = "samsung,exynos5433-pcie-phy";
1942 reg = <0x15680000 0x1000>;
1943 samsung,pmu-syscon = <&pmu_system_controller>;
1944 samsung,fsys-sysreg = <&syscon_fsys>;
1946 status = "disabled";
1949 pcie: pcie@15700000 {
1950 compatible = "samsung,exynos5433-pcie";
1951 reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
1952 <0x0c000000 0x1000>;
1953 reg-names = "dbi", "elbi", "config";
1954 #address-cells = <3>;
1956 #interrupt-cells = <1>;
1957 device_type = "pci";
1958 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1959 clocks = <&cmu_fsys CLK_PCIE>,
1960 <&cmu_fsys CLK_PCLK_PCIE_PHY>;
1961 clock-names = "pcie", "pcie_bus";
1964 bus-range = <0x00 0xff>;
1966 ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
1967 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
1968 status = "disabled";
1973 compatible = "arm,armv8-timer";
1974 interrupts = <GIC_PPI 13
1975 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1977 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1979 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1981 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1985 #include "exynos5433-bus.dtsi"
1986 #include "exynos5433-pinctrl.dtsi"
1987 #include "exynos5433-tmu.dtsi"