4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
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7 * modification, are permitted provided that the following conditions
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11 * notice, this list of conditions and the following disclaimer.
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13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
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17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 compatible = "brcm,stingray";
37 interrupt-parent = <&gic>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
55 compatible = "arm,cortex-a72";
57 enable-method = "psci";
58 next-level-cache = <&CLUSTER0_L2>;
63 compatible = "arm,cortex-a72";
65 enable-method = "psci";
66 next-level-cache = <&CLUSTER1_L2>;
71 compatible = "arm,cortex-a72";
73 enable-method = "psci";
74 next-level-cache = <&CLUSTER1_L2>;
79 compatible = "arm,cortex-a72";
81 enable-method = "psci";
82 next-level-cache = <&CLUSTER2_L2>;
87 compatible = "arm,cortex-a72";
89 enable-method = "psci";
90 next-level-cache = <&CLUSTER2_L2>;
95 compatible = "arm,cortex-a72";
97 enable-method = "psci";
98 next-level-cache = <&CLUSTER3_L2>;
103 compatible = "arm,cortex-a72";
105 enable-method = "psci";
106 next-level-cache = <&CLUSTER3_L2>;
109 CLUSTER0_L2: l2-cache@0 {
110 compatible = "cache";
113 CLUSTER1_L2: l2-cache@100 {
114 compatible = "cache";
117 CLUSTER2_L2: l2-cache@200 {
118 compatible = "cache";
121 CLUSTER3_L2: l2-cache@300 {
122 compatible = "cache";
126 memory: memory@80000000 {
127 device_type = "memory";
128 reg = <0x00000000 0x80000000 0 0x40000000>;
132 compatible = "arm,psci-0.2";
137 compatible = "arm,armv8-pmuv3";
138 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
142 compatible = "arm,armv8-timer";
143 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
144 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
145 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
146 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
149 mhb: syscon@60401000 {
150 compatible = "brcm,sr-mhb", "syscon";
151 reg = <0 0x60401000 0 0x38c>;
155 compatible = "simple-bus";
156 #address-cells = <1>;
158 ranges = <0x0 0x0 0x61000000 0x05000000>;
161 compatible = "arm,ccn-502";
162 reg = <0x00000000 0x900000>;
163 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
166 gic: interrupt-controller@2c00000 {
167 compatible = "arm,gic-v3";
168 #interrupt-cells = <3>;
169 #address-cells = <1>;
172 interrupt-controller;
173 reg = <0x02c00000 0x010000>, /* GICD */
174 <0x02e00000 0x600000>; /* GICR */
175 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
177 gic_its: gic-its@63c20000 {
178 compatible = "arm,gic-v3-its";
181 reg = <0x02c20000 0x10000>;
186 compatible = "arm,mmu-500";
187 reg = <0x03000000 0x80000>;
188 #global-interrupts = <1>;
189 interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
259 compatible = "simple-bus";
260 #address-cells = <1>;
262 ranges = <0x0 0x0 0x66400000 0x100000>;
264 #include "stingray-clock.dtsi"
267 compatible = "brcm,ocotp-v2";
268 reg = <0x0001c400 0x68>;
269 brcm,ocotp-size = <2048>;
274 compatible = "brcm,sr-cdru", "syscon";
275 reg = <0x0001d000 0x400>;
278 gpio_crmu: gpio@24800 {
279 compatible = "brcm,iproc-gpio";
280 reg = <0x00024800 0x4c>;
287 #include "stingray-fs4.dtsi"
288 #include "stingray-pcie.dtsi"
289 #include "stingray-usb.dtsi"
292 compatible = "simple-bus";
293 #address-cells = <1>;
295 ranges = <0x0 0x0 0x68900000 0x17700000>;
297 #include "stingray-pinctrl.dtsi"
299 mdio_mux_iproc: mdio-mux@20000 {
300 compatible = "brcm,mdio-mux-iproc";
301 reg = <0x00020000 0x250>;
302 #address-cells = <1>;
305 mdio@0 { /* PCIe serdes */
307 #address-cells = <1>;
313 #address-cells = <1>;
317 mdio@10 { /* RGMII */
319 #address-cells = <1>;
325 compatible = "brcm,iproc-pwm";
326 reg = <0x00010000 0x1000>;
327 clocks = <&crmu_ref25m>;
332 timer0: timer@30000 {
333 compatible = "arm,sp804", "arm,primecell";
334 reg = <0x00030000 0x1000>;
335 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&hsls_25m_div2_clk>,
337 <&hsls_25m_div2_clk>,
339 clock-names = "timer1", "timer2", "apb_pclk";
343 timer1: timer@40000 {
344 compatible = "arm,sp804", "arm,primecell";
345 reg = <0x00040000 0x1000>;
346 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&hsls_25m_div2_clk>,
348 <&hsls_25m_div2_clk>,
350 clock-names = "timer1", "timer2", "apb_pclk";
353 timer2: timer@50000 {
354 compatible = "arm,sp804", "arm,primecell";
355 reg = <0x00050000 0x1000>;
356 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&hsls_25m_div2_clk>,
358 <&hsls_25m_div2_clk>,
360 clock-names = "timer1", "timer2", "apb_pclk";
364 timer3: timer@60000 {
365 compatible = "arm,sp804", "arm,primecell";
366 reg = <0x00060000 0x1000>;
367 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&hsls_25m_div2_clk>,
369 <&hsls_25m_div2_clk>,
371 clock-names = "timer1", "timer2", "apb_pclk";
375 timer4: timer@70000 {
376 compatible = "arm,sp804", "arm,primecell";
377 reg = <0x00070000 0x1000>;
378 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&hsls_25m_div2_clk>,
380 <&hsls_25m_div2_clk>,
382 clock-names = "timer1", "timer2", "apb_pclk";
386 timer5: timer@80000 {
387 compatible = "arm,sp804", "arm,primecell";
388 reg = <0x00080000 0x1000>;
389 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&hsls_25m_div2_clk>,
391 <&hsls_25m_div2_clk>,
393 clock-names = "timer1", "timer2", "apb_pclk";
397 timer6: timer@90000 {
398 compatible = "arm,sp804", "arm,primecell";
399 reg = <0x00090000 0x1000>;
400 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&hsls_25m_div2_clk>,
402 <&hsls_25m_div2_clk>,
404 clock-names = "timer1", "timer2", "apb_pclk";
408 timer7: timer@a0000 {
409 compatible = "arm,sp804", "arm,primecell";
410 reg = <0x000a0000 0x1000>;
411 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&hsls_25m_div2_clk>,
413 <&hsls_25m_div2_clk>,
415 clock-names = "timer1", "timer2", "apb_pclk";
420 compatible = "brcm,iproc-i2c";
421 reg = <0x000b0000 0x100>;
422 #address-cells = <1>;
424 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
425 clock-frequency = <100000>;
429 wdt0: watchdog@c0000 {
430 compatible = "arm,sp805", "arm,primecell";
431 reg = <0x000c0000 0x1000>;
432 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
434 clock-names = "wdog_clk", "apb_pclk";
438 gpio_hsls: gpio@d0000 {
439 compatible = "brcm,iproc-gpio";
440 reg = <0x000d0000 0x864>;
444 interrupt-controller;
445 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
446 gpio-ranges = <&pinmux 0 0 16>,
464 compatible = "brcm,iproc-i2c";
465 reg = <0x000e0000 0x100>;
466 #address-cells = <1>;
468 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
469 clock-frequency = <100000>;
473 uart0: serial@100000 {
474 device_type = "serial";
475 compatible = "snps,dw-apb-uart";
476 reg = <0x00100000 0x1000>;
478 clock-frequency = <25000000>;
479 interrupt-parent = <&gic>;
480 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
484 uart1: serial@110000 {
485 device_type = "serial";
486 compatible = "snps,dw-apb-uart";
487 reg = <0x00110000 0x1000>;
489 clock-frequency = <25000000>;
490 interrupt-parent = <&gic>;
491 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
495 uart2: serial@120000 {
496 device_type = "serial";
497 compatible = "snps,dw-apb-uart";
498 reg = <0x00120000 0x1000>;
500 clock-frequency = <25000000>;
501 interrupt-parent = <&gic>;
502 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
506 uart3: serial@130000 {
507 device_type = "serial";
508 compatible = "snps,dw-apb-uart";
509 reg = <0x00130000 0x1000>;
511 clock-frequency = <25000000>;
512 interrupt-parent = <&gic>;
513 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
518 compatible = "arm,pl022", "arm,primecell";
519 reg = <0x00180000 0x1000>;
520 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
522 clock-names = "spiclk", "apb_pclk";
524 #address-cells = <1>;
530 compatible = "arm,pl022", "arm,primecell";
531 reg = <0x00190000 0x1000>;
532 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
534 clock-names = "spiclk", "apb_pclk";
536 #address-cells = <1>;
541 hwrng: hwrng@220000 {
542 compatible = "brcm,iproc-rng200";
543 reg = <0x00220000 0x28>;
547 compatible = "arm,pl330", "arm,primecell";
548 reg = <0x00310000 0x1000>;
549 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
560 #dma-requests = <32>;
561 clocks = <&hsls_div2_clk>;
562 clock-names = "apb_pclk";
563 iommus = <&smmu 0x6000 0x0000>;
566 enet: ethernet@340000{
567 compatible = "brcm,amac";
568 reg = <0x00340000 0x1000>;
569 reg-names = "amac_base";
571 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
576 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
577 reg = <0x00360000 0x600>,
580 reg-names = "nand", "iproc-idm", "iproc-ext";
581 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
582 #address-cells = <1>;
588 sdio0: sdhci@3f1000 {
589 compatible = "brcm,sdhci-iproc";
590 reg = <0x003f1000 0x100>;
591 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&sdio0_clk>;
594 iommus = <&smmu 0x6002 0x0000>;
598 sdio1: sdhci@3f2000 {
599 compatible = "brcm,sdhci-iproc";
600 reg = <0x003f2000 0x100>;
601 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&sdio1_clk>;
604 iommus = <&smmu 0x6003 0x0000>;
610 compatible = "simple-bus";
611 #address-cells = <1>;
613 ranges = <0x0 0x0 0x8f100000 0x100>;
616 compatible = "brcm,sr-thermal";
618 brcm,tmon-mask = <0x3f>;
619 #thermal-sensor-cells = <1>;
624 ihost0_thermal: ihost0-thermal {
625 polling-delay-passive = <0>;
626 polling-delay = <1000>;
627 thermal-sensors = <&tmon 0>;
630 temperature = <105000>;
636 ihost1_thermal: ihost1-thermal {
637 polling-delay-passive = <0>;
638 polling-delay = <1000>;
639 thermal-sensors = <&tmon 1>;
642 temperature = <105000>;
648 ihost2_thermal: ihost2-thermal {
649 polling-delay-passive = <0>;
650 polling-delay = <1000>;
651 thermal-sensors = <&tmon 2>;
654 temperature = <105000>;
660 ihost3_thermal: ihost3-thermal {
661 polling-delay-passive = <0>;
662 polling-delay = <1000>;
663 thermal-sensors = <&tmon 3>;
666 temperature = <105000>;
672 crmu_thermal: crmu-thermal {
673 polling-delay-passive = <0>;
674 polling-delay = <1000>;
675 thermal-sensors = <&tmon 4>;
678 temperature = <105000>;
684 nitro_thermal: nitro-thermal {
685 polling-delay-passive = <0>;
686 polling-delay = <1000>;
687 thermal-sensors = <&tmon 5>;
690 temperature = <105000>;
699 compatible = "simple-bus";
700 #address-cells = <1>;
702 ranges = <0x0 0x0 0x0 0x7fffffff>;
704 nic_i2c0: i2c@60826100 {
705 compatible = "brcm,iproc-nic-i2c";
706 #address-cells = <1>;
708 reg = <0x60826100 0x100>,
710 brcm,ape-hsls-addr-mask = <0x03400000>;
711 clock-frequency = <100000>;