arch/arm64/boot/dts/amlogic/meson-axg.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/clock/axg-aoclkc.h>
   7 #include <dt-bindings/clock/axg-audio-clkc.h>
   8 #include <dt-bindings/clock/axg-clkc.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/gpio/meson-axg-gpio.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
  14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
  15 #include <dt-bindings/power/meson-axg-power.h>
  16
  17 / {
  18         compatible = "amlogic,meson-axg";
  19
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         tdmif_a: audio-controller-0 {
  25                 compatible = "amlogic,axg-tdm-iface";
  26                 #sound-dai-cells = <0>;
  27                 sound-name-prefix = "TDM_A";
  28                 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
  29                          <&clkc_audio AUD_CLKID_MST_A_SCLK>,
  30                          <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
  31                 clock-names = "mclk", "sclk", "lrclk";
  32                 status = "disabled";
  33         };
  34
  35         tdmif_b: audio-controller-1 {
  36                 compatible = "amlogic,axg-tdm-iface";
  37                 #sound-dai-cells = <0>;
  38                 sound-name-prefix = "TDM_B";
  39                 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
  40                          <&clkc_audio AUD_CLKID_MST_B_SCLK>,
  41                          <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
  42                 clock-names = "mclk", "sclk", "lrclk";
  43                 status = "disabled";
  44         };
  45
  46         tdmif_c: audio-controller-2 {
  47                 compatible = "amlogic,axg-tdm-iface";
  48                 #sound-dai-cells = <0>;
  49                 sound-name-prefix = "TDM_C";
  50                 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
  51                          <&clkc_audio AUD_CLKID_MST_C_SCLK>,
  52                          <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
  53                 clock-names = "mclk", "sclk", "lrclk";
  54                 status = "disabled";
  55         };
  56
  57         arm-pmu {
  58                 compatible = "arm,cortex-a53-pmu";
  59                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  60                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  61                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  62                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  63                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  64         };
  65
  66         cpus {
  67                 #address-cells = <0x2>;
  68                 #size-cells = <0x0>;
  69
  70                 cpu0: cpu@0 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53";
  73                         reg = <0x0 0x0>;
  74                         enable-method = "psci";
  75                         next-level-cache = <&l2>;
  76                         clocks = <&scpi_dvfs 0>;
  77                 };
  78
  79                 cpu1: cpu@1 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53";
  82                         reg = <0x0 0x1>;
  83                         enable-method = "psci";
  84                         next-level-cache = <&l2>;
  85                         clocks = <&scpi_dvfs 0>;
  86                 };
  87
  88                 cpu2: cpu@2 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a53";
  91                         reg = <0x0 0x2>;
  92                         enable-method = "psci";
  93                         next-level-cache = <&l2>;
  94                         clocks = <&scpi_dvfs 0>;
  95                 };
  96
  97                 cpu3: cpu@3 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a53";
 100                         reg = <0x0 0x3>;
 101                         enable-method = "psci";
 102                         next-level-cache = <&l2>;
 103                         clocks = <&scpi_dvfs 0>;
 104                 };
 105
 106                 l2: l2-cache0 {
 107                         compatible = "cache";
 108                 };
 109         };
 110
 111         sm: secure-monitor {
 112                 compatible = "amlogic,meson-gxbb-sm";
 113         };
 114
 115         efuse: efuse {
 116                 compatible = "amlogic,meson-gxbb-efuse";
 117                 clocks = <&clkc CLKID_EFUSE>;
 118                 #address-cells = <1>;
 119                 #size-cells = <1>;
 120                 read-only;
 121                 secure-monitor = <&sm>;
 122         };
 123
 124         psci {
 125                 compatible = "arm,psci-1.0";
 126                 method = "smc";
 127         };
 128
 129         reserved-memory {
 130                 #address-cells = <2>;
 131                 #size-cells = <2>;
 132                 ranges;
 133
 134                 /* 16 MiB reserved for Hardware ROM Firmware */
 135                 hwrom_reserved: hwrom@0 {
 136                         reg = <0x0 0x0 0x0 0x1000000>;
 137                         no-map;
 138                 };
 139
 140                 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
 141                 secmon_reserved: secmon@5000000 {
 142                         reg = <0x0 0x05000000 0x0 0x300000>;
 143                         no-map;
 144                 };
 145         };
 146
 147         scpi {
 148                 compatible = "arm,scpi-pre-1.0";
 149                 mboxes = <&mailbox 1 &mailbox 2>;
 150                 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
 151
 152                 scpi_clocks: clocks {
 153                         compatible = "arm,scpi-clocks";
 154
 155                         scpi_dvfs: clock-controller {
 156                                 compatible = "arm,scpi-dvfs-clocks";
 157                                 #clock-cells = <1>;
 158                                 clock-indices = <0>;
 159                                 clock-output-names = "vcpu";
 160                         };
 161                 };
 162
 163                 scpi_sensors: sensors {
 164                         compatible = "amlogic,meson-gxbb-scpi-sensors";
 165                         #thermal-sensor-cells = <1>;
 166                 };
 167         };
 168
 169         soc {
 170                 compatible = "simple-bus";
 171                 #address-cells = <2>;
 172                 #size-cells = <2>;
 173                 ranges;
 174
 175                 pcieA: pcie@f9800000 {
 176                         compatible = "amlogic,axg-pcie", "snps,dw-pcie";
 177                         reg = <0x0 0xf9800000 0x0 0x400000>,
 178                               <0x0 0xff646000 0x0 0x2000>,
 179                               <0x0 0xf9f00000 0x0 0x100000>;
 180                         reg-names = "elbi", "cfg", "config";
 181                         interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
 182                         #interrupt-cells = <1>;
 183                         interrupt-map-mask = <0 0 0 0>;
 184                         interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
 185                         bus-range = <0x0 0xff>;
 186                         #address-cells = <3>;
 187                         #size-cells = <2>;
 188                         device_type = "pci";
 189                         ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
 190
 191                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
 192                         clock-names = "general", "pclk", "port";
 193                         resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
 194                         reset-names = "port", "apb";
 195                         num-lanes = <1>;
 196                         phys = <&pcie_phy>;
 197                         phy-names = "pcie";
 198                         status = "disabled";
 199                 };
 200
 201                 pcieB: pcie@fa000000 {
 202                         compatible = "amlogic,axg-pcie", "snps,dw-pcie";
 203                         reg = <0x0 0xfa000000 0x0 0x400000>,
 204                               <0x0 0xff648000 0x0 0x2000>,
 205                               <0x0 0xfa400000 0x0 0x100000>;
 206                         reg-names = "elbi", "cfg", "config";
 207                         interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
 208                         #interrupt-cells = <1>;
 209                         interrupt-map-mask = <0 0 0 0>;
 210                         interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
 211                         bus-range = <0x0 0xff>;
 212                         #address-cells = <3>;
 213                         #size-cells = <2>;
 214                         device_type = "pci";
 215                         ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
 216
 217                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
 218                         clock-names = "general", "pclk", "port";
 219                         resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
 220                         reset-names = "port", "apb";
 221                         num-lanes = <1>;
 222                         phys = <&pcie_phy>;
 223                         phy-names = "pcie";
 224                         status = "disabled";
 225                 };
 226
 227                 usb: usb@ffe09080 {
 228                         compatible = "amlogic,meson-axg-usb-ctrl";
 229                         reg = <0x0 0xffe09080 0x0 0x20>;
 230                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 231                         #address-cells = <2>;
 232                         #size-cells = <2>;
 233                         ranges;
 234
 235                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
 236                         clock-names = "usb_ctrl", "ddr";
 237                         resets = <&reset RESET_USB_OTG>;
 238
 239                         dr_mode = "otg";
 240
 241                         phys = <&usb2_phy1>;
 242                         phy-names = "usb2-phy1";
 243
 244                         dwc2: usb@ff400000 {
 245                                 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
 246                                 reg = <0x0 0xff400000 0x0 0x40000>;
 247                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 248                                 clocks = <&clkc CLKID_USB1>;
 249                                 clock-names = "otg";
 250                                 phys = <&usb2_phy1>;
 251                                 dr_mode = "peripheral";
 252                                 g-rx-fifo-size = <192>;
 253                                 g-np-tx-fifo-size = <128>;
 254                                 g-tx-fifo-size = <128 128 16 16 16>;
 255                         };
 256
 257                         dwc3: usb@ff500000 {
 258                                 compatible = "snps,dwc3";
 259                                 reg = <0x0 0xff500000 0x0 0x100000>;
 260                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 261                                 dr_mode = "host";
 262                                 maximum-speed = "high-speed";
 263                                 snps,dis_u2_susphy_quirk;
 264                         };
 265                 };
 266
 267                 ethmac: ethernet@ff3f0000 {
 268                         compatible = "amlogic,meson-axg-dwmac",
 269                                      "snps,dwmac-3.70a",
 270                                      "snps,dwmac";
 271                         reg = <0x0 0xff3f0000 0x0 0x10000>,
 272                               <0x0 0xff634540 0x0 0x8>;
 273                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 274                         interrupt-names = "macirq";
 275                         clocks = <&clkc CLKID_ETH>,
 276                                  <&clkc CLKID_FCLK_DIV2>,
 277                                  <&clkc CLKID_MPLL2>,
 278                                  <&clkc CLKID_FCLK_DIV2>;
 279                         clock-names = "stmmaceth", "clkin0", "clkin1",
 280                                       "timing-adjustment";
 281                         rx-fifo-depth = <4096>;
 282                         tx-fifo-depth = <2048>;
 283                         resets = <&reset RESET_ETHERNET>;
 284                         reset-names = "stmmaceth";
 285                         power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
 286                         status = "disabled";
 287                 };
 288
 289                 pcie_phy: phy@ff644000 {
 290                         compatible = "amlogic,axg-pcie-phy";
 291                         reg = <0x0 0xff644000 0x0 0x1c>;
 292                         resets = <&reset RESET_PCIE_PHY>;
 293                         phys = <&mipi_pcie_analog_dphy>;
 294                         phy-names = "analog";
 295                         #phy-cells = <0>;
 296                 };
 297
 298                 pdm: audio-controller@ff632000 {
 299                         compatible = "amlogic,axg-pdm";
 300                         reg = <0x0 0xff632000 0x0 0x34>;
 301                         #sound-dai-cells = <0>;
 302                         sound-name-prefix = "PDM";
 303                         clocks = <&clkc_audio AUD_CLKID_PDM>,
 304                                  <&clkc_audio AUD_CLKID_PDM_DCLK>,
 305                                  <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
 306                         clock-names = "pclk", "dclk", "sysclk";
 307                         status = "disabled";
 308                 };
 309
 310                 periphs: bus@ff634000 {
 311                         compatible = "simple-bus";
 312                         reg = <0x0 0xff634000 0x0 0x2000>;
 313                         #address-cells = <2>;
 314                         #size-cells = <2>;
 315                         ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
 316
 317                         hwrng: rng@18 {
 318                                 compatible = "amlogic,meson-rng";
 319                                 reg = <0x0 0x18 0x0 0x4>;
 320                                 clocks = <&clkc CLKID_RNG0>;
 321                                 clock-names = "core";
 322                         };
 323
 324                         pinctrl_periphs: pinctrl@480 {
 325                                 compatible = "amlogic,meson-axg-periphs-pinctrl";
 326                                 #address-cells = <2>;
 327                                 #size-cells = <2>;
 328                                 ranges;
 329
 330                                 gpio: bank@480 {
 331                                         reg = <0x0 0x00480 0x0 0x40>,
 332                                               <0x0 0x004e8 0x0 0x14>,
 333                                               <0x0 0x00520 0x0 0x14>,
 334                                               <0x0 0x00430 0x0 0x3c>;
 335                                         reg-names = "mux", "pull", "pull-enable", "gpio";
 336                                         gpio-controller;
 337                                         #gpio-cells = <2>;
 338                                         gpio-ranges = <&pinctrl_periphs 0 0 86>;
 339                                 };
 340
 341                                 i2c0_pins: i2c0 {
 342                                         mux {
 343                                                 groups = "i2c0_sck",
 344                                                          "i2c0_sda";
 345                                                 function = "i2c0";
 346                                                 bias-disable;
 347                                         };
 348                                 };
 349
 350                                 i2c1_x_pins: i2c1_x {
 351                                         mux {
 352                                                 groups = "i2c1_sck_x",
 353                                                          "i2c1_sda_x";
 354                                                 function = "i2c1";
 355                                                 bias-disable;
 356                                         };
 357                                 };
 358
 359                                 i2c1_z_pins: i2c1_z {
 360                                         mux {
 361                                                 groups = "i2c1_sck_z",
 362                                                          "i2c1_sda_z";
 363                                                 function = "i2c1";
 364                                                 bias-disable;
 365                                         };
 366                                 };
 367
 368                                 i2c2_a_pins: i2c2_a {
 369                                         mux {
 370                                                 groups = "i2c2_sck_a",
 371                                                          "i2c2_sda_a";
 372                                                 function = "i2c2";
 373                                                 bias-disable;
 374                                         };
 375                                 };
 376
 377                                 i2c2_x_pins: i2c2_x {
 378                                         mux {
 379                                                 groups = "i2c2_sck_x",
 380                                                          "i2c2_sda_x";
 381                                                 function = "i2c2";
 382                                                 bias-disable;
 383                                         };
 384                                 };
 385
 386                                 i2c3_a6_pins: i2c3_a6 {
 387                                         mux {
 388                                                 groups = "i2c3_sda_a6",
 389                                                          "i2c3_sck_a7";
 390                                                 function = "i2c3";
 391                                                 bias-disable;
 392                                         };
 393                                 };
 394
 395                                 i2c3_a12_pins: i2c3_a12 {
 396                                         mux {
 397                                                 groups = "i2c3_sda_a12",
 398                                                          "i2c3_sck_a13";
 399                                                 function = "i2c3";
 400                                                 bias-disable;
 401                                         };
 402                                 };
 403
 404                                 i2c3_a19_pins: i2c3_a19 {
 405                                         mux {
 406                                                 groups = "i2c3_sda_a19",
 407                                                          "i2c3_sck_a20";
 408                                                 function = "i2c3";
 409                                                 bias-disable;
 410                                         };
 411                                 };
 412
 413                                 emmc_pins: emmc {
 414                                         mux-0 {
 415                                                 groups = "emmc_nand_d0",
 416                                                          "emmc_nand_d1",
 417                                                          "emmc_nand_d2",
 418                                                          "emmc_nand_d3",
 419                                                          "emmc_nand_d4",
 420                                                          "emmc_nand_d5",
 421                                                          "emmc_nand_d6",
 422                                                          "emmc_nand_d7",
 423                                                          "emmc_cmd";
 424                                                 function = "emmc";
 425                                                 bias-pull-up;
 426                                         };
 427
 428                                         mux-1 {
 429                                                 groups = "emmc_clk";
 430                                                 function = "emmc";
 431                                                 bias-disable;
 432                                         };
 433                                 };
 434
 435                                 emmc_ds_pins: emmc_ds {
 436                                         mux {
 437                                                 groups = "emmc_ds";
 438                                                 function = "emmc";
 439                                                 bias-pull-down;
 440                                         };
 441                                 };
 442
 443                                 emmc_clk_gate_pins: emmc_clk_gate {
 444                                         mux {
 445                                                 groups = "BOOT_8";
 446                                                 function = "gpio_periphs";
 447                                                 bias-pull-down;
 448                                         };
 449                                 };
 450
 451                                 eth_rgmii_x_pins: eth-x-rgmii {
 452                                         mux {
 453                                                 groups = "eth_mdio_x",
 454                                                          "eth_mdc_x",
 455                                                          "eth_rgmii_rx_clk_x",
 456                                                          "eth_rx_dv_x",
 457                                                          "eth_rxd0_x",
 458                                                          "eth_rxd1_x",
 459                                                          "eth_rxd2_rgmii",
 460                                                          "eth_rxd3_rgmii",
 461                                                          "eth_rgmii_tx_clk",
 462                                                          "eth_txen_x",
 463                                                          "eth_txd0_x",
 464                                                          "eth_txd1_x",
 465                                                          "eth_txd2_rgmii",
 466                                                          "eth_txd3_rgmii";
 467                                                 function = "eth";
 468                                                 bias-disable;
 469                                         };
 470                                 };
 471
 472                                 eth_rgmii_y_pins: eth-y-rgmii {
 473                                         mux {
 474                                                 groups = "eth_mdio_y",
 475                                                          "eth_mdc_y",
 476                                                          "eth_rgmii_rx_clk_y",
 477                                                          "eth_rx_dv_y",
 478                                                          "eth_rxd0_y",
 479                                                          "eth_rxd1_y",
 480                                                          "eth_rxd2_rgmii",
 481                                                          "eth_rxd3_rgmii",
 482                                                          "eth_rgmii_tx_clk",
 483                                                          "eth_txen_y",
 484                                                          "eth_txd0_y",
 485                                                          "eth_txd1_y",
 486                                                          "eth_txd2_rgmii",
 487                                                          "eth_txd3_rgmii";
 488                                                 function = "eth";
 489                                                 bias-disable;
 490                                         };
 491                                 };
 492
 493                                 eth_rmii_x_pins: eth-x-rmii {
 494                                         mux {
 495                                                 groups = "eth_mdio_x",
 496                                                          "eth_mdc_x",
 497                                                          "eth_rgmii_rx_clk_x",
 498                                                          "eth_rx_dv_x",
 499                                                          "eth_rxd0_x",
 500                                                          "eth_rxd1_x",
 501                                                          "eth_txen_x",
 502                                                          "eth_txd0_x",
 503                                                          "eth_txd1_x";
 504                                                 function = "eth";
 505                                                 bias-disable;
 506                                         };
 507                                 };
 508
 509                                 eth_rmii_y_pins: eth-y-rmii {
 510                                         mux {
 511                                                 groups = "eth_mdio_y",
 512                                                          "eth_mdc_y",
 513                                                          "eth_rgmii_rx_clk_y",
 514                                                          "eth_rx_dv_y",
 515                                                          "eth_rxd0_y",
 516                                                          "eth_rxd1_y",
 517                                                          "eth_txen_y",
 518                                                          "eth_txd0_y",
 519                                                          "eth_txd1_y";
 520                                                 function = "eth";
 521                                                 bias-disable;
 522                                         };
 523                                 };
 524
 525                                 mclk_b_pins: mclk_b {
 526                                         mux {
 527                                                 groups = "mclk_b";
 528                                                 function = "mclk_b";
 529                                                 bias-disable;
 530                                         };
 531                                 };
 532
 533                                 mclk_c_pins: mclk_c {
 534                                         mux {
 535                                                 groups = "mclk_c";
 536                                                 function = "mclk_c";
 537                                                 bias-disable;
 538                                         };
 539                                 };
 540
 541                                 pdm_dclk_a14_pins: pdm_dclk_a14 {
 542                                         mux {
 543                                                 groups = "pdm_dclk_a14";
 544                                                 function = "pdm";
 545                                                 bias-disable;
 546                                         };
 547                                 };
 548
 549                                 pdm_dclk_a19_pins: pdm_dclk_a19 {
 550                                         mux {
 551                                                 groups = "pdm_dclk_a19";
 552                                                 function = "pdm";
 553                                                 bias-disable;
 554                                         };
 555                                 };
 556
 557                                 pdm_din0_pins: pdm_din0 {
 558                                         mux {
 559                                                 groups = "pdm_din0";
 560                                                 function = "pdm";
 561                                                 bias-disable;
 562                                         };
 563                                 };
 564
 565                                 pdm_din1_pins: pdm_din1 {
 566                                         mux {
 567                                                 groups = "pdm_din1";
 568                                                 function = "pdm";
 569                                                 bias-disable;
 570                                         };
 571                                 };
 572
 573                                 pdm_din2_pins: pdm_din2 {
 574                                         mux {
 575                                                 groups = "pdm_din2";
 576                                                 function = "pdm";
 577                                                 bias-disable;
 578                                         };
 579                                 };
 580
 581                                 pdm_din3_pins: pdm_din3 {
 582                                         mux {
 583                                                 groups = "pdm_din3";
 584                                                 function = "pdm";
 585                                                 bias-disable;
 586                                         };
 587                                 };
 588
 589                                 pwm_a_a_pins: pwm_a_a {
 590                                         mux {
 591                                                 groups = "pwm_a_a";
 592                                                 function = "pwm_a";
 593                                                 bias-disable;
 594                                         };
 595                                 };
 596
 597                                 pwm_a_x18_pins: pwm_a_x18 {
 598                                         mux {
 599                                                 groups = "pwm_a_x18";
 600                                                 function = "pwm_a";
 601                                                 bias-disable;
 602                                         };
 603                                 };
 604
 605                                 pwm_a_x20_pins: pwm_a_x20 {
 606                                         mux {
 607                                                 groups = "pwm_a_x20";
 608                                                 function = "pwm_a";
 609                                                 bias-disable;
 610                                         };
 611                                 };
 612
 613                                 pwm_a_z_pins: pwm_a_z {
 614                                         mux {
 615                                                 groups = "pwm_a_z";
 616                                                 function = "pwm_a";
 617                                                 bias-disable;
 618                                         };
 619                                 };
 620
 621                                 pwm_b_a_pins: pwm_b_a {
 622                                         mux {
 623                                                 groups = "pwm_b_a";
 624                                                 function = "pwm_b";
 625                                                 bias-disable;
 626                                         };
 627                                 };
 628
 629                                 pwm_b_x_pins: pwm_b_x {
 630                                         mux {
 631                                                 groups = "pwm_b_x";
 632                                                 function = "pwm_b";
 633                                                 bias-disable;
 634                                         };
 635                                 };
 636
 637                                 pwm_b_z_pins: pwm_b_z {
 638                                         mux {
 639                                                 groups = "pwm_b_z";
 640                                                 function = "pwm_b";
 641                                                 bias-disable;
 642                                         };
 643                                 };
 644
 645                                 pwm_c_a_pins: pwm_c_a {
 646                                         mux {
 647                                                 groups = "pwm_c_a";
 648                                                 function = "pwm_c";
 649                                                 bias-disable;
 650                                         };
 651                                 };
 652
 653                                 pwm_c_x10_pins: pwm_c_x10 {
 654                                         mux {
 655                                                 groups = "pwm_c_x10";
 656                                                 function = "pwm_c";
 657                                                 bias-disable;
 658                                         };
 659                                 };
 660
 661                                 pwm_c_x17_pins: pwm_c_x17 {
 662                                         mux {
 663                                                 groups = "pwm_c_x17";
 664                                                 function = "pwm_c";
 665                                                 bias-disable;
 666                                         };
 667                                 };
 668
 669                                 pwm_d_x11_pins: pwm_d_x11 {
 670                                         mux {
 671                                                 groups = "pwm_d_x11";
 672                                                 function = "pwm_d";
 673                                                 bias-disable;
 674                                         };
 675                                 };
 676
 677                                 pwm_d_x16_pins: pwm_d_x16 {
 678                                         mux {
 679                                                 groups = "pwm_d_x16";
 680                                                 function = "pwm_d";
 681                                                 bias-disable;
 682                                         };
 683                                 };
 684
 685                                 sdio_pins: sdio {
 686                                         mux-0 {
 687                                                 groups = "sdio_d0",
 688                                                          "sdio_d1",
 689                                                          "sdio_d2",
 690                                                          "sdio_d3",
 691                                                          "sdio_cmd";
 692                                                 function = "sdio";
 693                                                 bias-pull-up;
 694                                         };
 695
 696                                         mux-1 {
 697                                                 groups = "sdio_clk";
 698                                                 function = "sdio";
 699                                                 bias-disable;
 700                                         };
 701                                 };
 702
 703                                 sdio_clk_gate_pins: sdio_clk_gate {
 704                                         mux {
 705                                                 groups = "GPIOX_4";
 706                                                 function = "gpio_periphs";
 707                                                 bias-pull-down;
 708                                         };
 709                                 };
 710
 711                                 spdif_in_z_pins: spdif_in_z {
 712                                         mux {
 713                                                 groups = "spdif_in_z";
 714                                                 function = "spdif_in";
 715                                                 bias-disable;
 716                                         };
 717                                 };
 718
 719                                 spdif_in_a1_pins: spdif_in_a1 {
 720                                         mux {
 721                                                 groups = "spdif_in_a1";
 722                                                 function = "spdif_in";
 723                                                 bias-disable;
 724                                         };
 725                                 };
 726
 727                                 spdif_in_a7_pins: spdif_in_a7 {
 728                                         mux {
 729                                                 groups = "spdif_in_a7";
 730                                                 function = "spdif_in";
 731                                                 bias-disable;
 732                                         };
 733                                 };
 734
 735                                 spdif_in_a19_pins: spdif_in_a19 {
 736                                         mux {
 737                                                 groups = "spdif_in_a19";
 738                                                 function = "spdif_in";
 739                                                 bias-disable;
 740                                         };
 741                                 };
 742
 743                                 spdif_in_a20_pins: spdif_in_a20 {
 744                                         mux {
 745                                                 groups = "spdif_in_a20";
 746                                                 function = "spdif_in";
 747                                                 bias-disable;
 748                                         };
 749                                 };
 750
 751                                 spdif_out_a1_pins: spdif_out_a1 {
 752                                         mux {
 753                                                 groups = "spdif_out_a1";
 754                                                 function = "spdif_out";
 755                                                 bias-disable;
 756                                         };
 757                                 };
 758
 759                                 spdif_out_a11_pins: spdif_out_a11 {
 760                                         mux {
 761                                                 groups = "spdif_out_a11";
 762                                                 function = "spdif_out";
 763                                                 bias-disable;
 764                                         };
 765                                 };
 766
 767                                 spdif_out_a19_pins: spdif_out_a19 {
 768                                         mux {
 769                                                 groups = "spdif_out_a19";
 770                                                 function = "spdif_out";
 771                                                 bias-disable;
 772                                         };
 773                                 };
 774
 775                                 spdif_out_a20_pins: spdif_out_a20 {
 776                                         mux {
 777                                                 groups = "spdif_out_a20";
 778                                                 function = "spdif_out";
 779                                                 bias-disable;
 780                                         };
 781                                 };
 782
 783                                 spdif_out_z_pins: spdif_out_z {
 784                                         mux {
 785                                                 groups = "spdif_out_z";
 786                                                 function = "spdif_out";
 787                                                 bias-disable;
 788                                         };
 789                                 };
 790
 791                                 spi0_pins: spi0 {
 792                                         mux {
 793                                                 groups = "spi0_miso",
 794                                                          "spi0_mosi",
 795                                                          "spi0_clk";
 796                                                 function = "spi0";
 797                                                 bias-disable;
 798                                         };
 799                                 };
 800
 801                                 spi0_ss0_pins: spi0_ss0 {
 802                                         mux {
 803                                                 groups = "spi0_ss0";
 804                                                 function = "spi0";
 805                                                 bias-disable;
 806                                         };
 807                                 };
 808
 809                                 spi0_ss1_pins: spi0_ss1 {
 810                                         mux {
 811                                                 groups = "spi0_ss1";
 812                                                 function = "spi0";
 813                                                 bias-disable;
 814                                         };
 815                                 };
 816
 817                                 spi0_ss2_pins: spi0_ss2 {
 818                                         mux {
 819                                                 groups = "spi0_ss2";
 820                                                 function = "spi0";
 821                                                 bias-disable;
 822                                         };
 823                                 };
 824
 825                                 spi1_a_pins: spi1_a {
 826                                         mux {
 827                                                 groups = "spi1_miso_a",
 828                                                          "spi1_mosi_a",
 829                                                          "spi1_clk_a";
 830                                                 function = "spi1";
 831                                                 bias-disable;
 832                                         };
 833                                 };
 834
 835                                 spi1_ss0_a_pins: spi1_ss0_a {
 836                                         mux {
 837                                                 groups = "spi1_ss0_a";
 838                                                 function = "spi1";
 839                                                 bias-disable;
 840                                         };
 841                                 };
 842
 843                                 spi1_ss1_pins: spi1_ss1 {
 844                                         mux {
 845                                                 groups = "spi1_ss1";
 846                                                 function = "spi1";
 847                                                 bias-disable;
 848                                         };
 849                                 };
 850
 851                                 spi1_x_pins: spi1_x {
 852                                         mux {
 853                                                 groups = "spi1_miso_x",
 854                                                          "spi1_mosi_x",
 855                                                          "spi1_clk_x";
 856                                                 function = "spi1";
 857                                                 bias-disable;
 858                                         };
 859                                 };
 860
 861                                 spi1_ss0_x_pins: spi1_ss0_x {
 862                                         mux {
 863                                                 groups = "spi1_ss0_x";
 864                                                 function = "spi1";
 865                                                 bias-disable;
 866                                         };
 867                                 };
 868
 869                                 tdma_din0_pins: tdma_din0 {
 870                                         mux {
 871                                                 groups = "tdma_din0";
 872                                                 function = "tdma";
 873                                                 bias-disable;
 874                                         };
 875                                 };
 876
 877                                 tdma_dout0_x14_pins: tdma_dout0_x14 {
 878                                         mux {
 879                                                 groups = "tdma_dout0_x14";
 880                                                 function = "tdma";
 881                                                 bias-disable;
 882                                         };
 883                                 };
 884
 885                                 tdma_dout0_x15_pins: tdma_dout0_x15 {
 886                                         mux {
 887                                                 groups = "tdma_dout0_x15";
 888                                                 function = "tdma";
 889                                                 bias-disable;
 890                                         };
 891                                 };
 892
 893                                 tdma_dout1_pins: tdma_dout1 {
 894                                         mux {
 895                                                 groups = "tdma_dout1";
 896                                                 function = "tdma";
 897                                                 bias-disable;
 898                                         };
 899                                 };
 900
 901                                 tdma_din1_pins: tdma_din1 {
 902                                         mux {
 903                                                 groups = "tdma_din1";
 904                                                 function = "tdma";
 905                                                 bias-disable;
 906                                         };
 907                                 };
 908
 909                                 tdma_fs_pins: tdma_fs {
 910                                         mux {
 911                                                 groups = "tdma_fs";
 912                                                 function = "tdma";
 913                                                 bias-disable;
 914                                         };
 915                                 };
 916
 917                                 tdma_fs_slv_pins: tdma_fs_slv {
 918                                         mux {
 919                                                 groups = "tdma_fs_slv";
 920                                                 function = "tdma";
 921                                                 bias-disable;
 922                                         };
 923                                 };
 924
 925                                 tdma_sclk_pins: tdma_sclk {
 926                                         mux {
 927                                                 groups = "tdma_sclk";
 928                                                 function = "tdma";
 929                                                 bias-disable;
 930                                         };
 931                                 };
 932
 933                                 tdma_sclk_slv_pins: tdma_sclk_slv {
 934                                         mux {
 935                                                 groups = "tdma_sclk_slv";
 936                                                 function = "tdma";
 937                                                 bias-disable;
 938                                         };
 939                                 };
 940
 941                                 tdmb_din0_pins: tdmb_din0 {
 942                                         mux {
 943                                                 groups = "tdmb_din0";
 944                                                 function = "tdmb";
 945                                                 bias-disable;
 946                                         };
 947                                 };
 948
 949                                 tdmb_din1_pins: tdmb_din1 {
 950                                         mux {
 951                                                 groups = "tdmb_din1";
 952                                                 function = "tdmb";
 953                                                 bias-disable;
 954                                         };
 955                                 };
 956
 957                                 tdmb_din2_pins: tdmb_din2 {
 958                                         mux {
 959                                                 groups = "tdmb_din2";
 960                                                 function = "tdmb";
 961                                                 bias-disable;
 962                                         };
 963                                 };
 964
 965                                 tdmb_din3_pins: tdmb_din3 {
 966                                         mux {
 967                                                 groups = "tdmb_din3";
 968                                                 function = "tdmb";
 969                                                 bias-disable;
 970                                         };
 971                                 };
 972
 973                                 tdmb_dout0_pins: tdmb_dout0 {
 974                                         mux {
 975                                                 groups = "tdmb_dout0";
 976                                                 function = "tdmb";
 977                                                 bias-disable;
 978                                         };
 979                                 };
 980
 981                                 tdmb_dout1_pins: tdmb_dout1 {
 982                                         mux {
 983                                                 groups = "tdmb_dout1";
 984                                                 function = "tdmb";
 985                                                 bias-disable;
 986                                         };
 987                                 };
 988
 989                                 tdmb_dout2_pins: tdmb_dout2 {
 990                                         mux {
 991                                                 groups = "tdmb_dout2";
 992                                                 function = "tdmb";
 993                                                 bias-disable;
 994                                         };
 995                                 };
 996
 997                                 tdmb_dout3_pins: tdmb_dout3 {
 998                                         mux {
 999                                                 groups = "tdmb_dout3";
1000                                                 function = "tdmb";
1001                                                 bias-disable;
1002                                         };
1003                                 };
1004
1005                                 tdmb_fs_pins: tdmb_fs {
1006                                         mux {
1007                                                 groups = "tdmb_fs";
1008                                                 function = "tdmb";
1009                                                 bias-disable;
1010                                         };
1011                                 };
1012
1013                                 tdmb_fs_slv_pins: tdmb_fs_slv {
1014                                         mux {
1015                                                 groups = "tdmb_fs_slv";
1016                                                 function = "tdmb";
1017                                                 bias-disable;
1018                                         };
1019                                 };
1020
1021                                 tdmb_sclk_pins: tdmb_sclk {
1022                                         mux {
1023                                                 groups = "tdmb_sclk";
1024                                                 function = "tdmb";
1025                                                 bias-disable;
1026                                         };
1027                                 };
1028
1029                                 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1030                                         mux {
1031                                                 groups = "tdmb_sclk_slv";
1032                                                 function = "tdmb";
1033                                                 bias-disable;
1034                                         };
1035                                 };
1036
1037                                 tdmc_fs_pins: tdmc_fs {
1038                                         mux {
1039                                                 groups = "tdmc_fs";
1040                                                 function = "tdmc";
1041                                                 bias-disable;
1042                                         };
1043                                 };
1044
1045                                 tdmc_fs_slv_pins: tdmc_fs_slv {
1046                                         mux {
1047                                                 groups = "tdmc_fs_slv";
1048                                                 function = "tdmc";
1049                                                 bias-disable;
1050                                         };
1051                                 };
1052
1053                                 tdmc_sclk_pins: tdmc_sclk {
1054                                         mux {
1055                                                 groups = "tdmc_sclk";
1056                                                 function = "tdmc";
1057                                                 bias-disable;
1058                                         };
1059                                 };
1060
1061                                 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1062                                         mux {
1063                                                 groups = "tdmc_sclk_slv";
1064                                                 function = "tdmc";
1065                                                 bias-disable;
1066                                         };
1067                                 };
1068
1069                                 tdmc_din0_pins: tdmc_din0 {
1070                                         mux {
1071                                                 groups = "tdmc_din0";
1072                                                 function = "tdmc";
1073                                                 bias-disable;
1074                                         };
1075                                 };
1076
1077                                 tdmc_din1_pins: tdmc_din1 {
1078                                         mux {
1079                                                 groups = "tdmc_din1";
1080                                                 function = "tdmc";
1081                                                 bias-disable;
1082                                         };
1083                                 };
1084
1085                                 tdmc_din2_pins: tdmc_din2 {
1086                                         mux {
1087                                                 groups = "tdmc_din2";
1088                                                 function = "tdmc";
1089                                                 bias-disable;
1090                                         };
1091                                 };
1092
1093                                 tdmc_din3_pins: tdmc_din3 {
1094                                         mux {
1095                                                 groups = "tdmc_din3";
1096                                                 function = "tdmc";
1097                                                 bias-disable;
1098                                         };
1099                                 };
1100
1101                                 tdmc_dout0_pins: tdmc_dout0 {
1102                                         mux {
1103                                                 groups = "tdmc_dout0";
1104                                                 function = "tdmc";
1105                                                 bias-disable;
1106                                         };
1107                                 };
1108
1109                                 tdmc_dout1_pins: tdmc_dout1 {
1110                                         mux {
1111                                                 groups = "tdmc_dout1";
1112                                                 function = "tdmc";
1113                                                 bias-disable;
1114                                         };
1115                                 };
1116
1117                                 tdmc_dout2_pins: tdmc_dout2 {
1118                                         mux {
1119                                                 groups = "tdmc_dout2";
1120                                                 function = "tdmc";
1121                                                 bias-disable;
1122                                         };
1123                                 };
1124
1125                                 tdmc_dout3_pins: tdmc_dout3 {
1126                                         mux {
1127                                                 groups = "tdmc_dout3";
1128                                                 function = "tdmc";
1129                                                 bias-disable;
1130                                         };
1131                                 };
1132
1133                                 uart_a_pins: uart_a {
1134                                         mux {
1135                                                 groups = "uart_tx_a",
1136                                                          "uart_rx_a";
1137                                                 function = "uart_a";
1138                                                 bias-disable;
1139                                         };
1140                                 };
1141
1142                                 uart_a_cts_rts_pins: uart_a_cts_rts {
1143                                         mux {
1144                                                 groups = "uart_cts_a",
1145                                                          "uart_rts_a";
1146                                                 function = "uart_a";
1147                                                 bias-disable;
1148                                         };
1149                                 };
1150
1151                                 uart_b_x_pins: uart_b_x {
1152                                         mux {
1153                                                 groups = "uart_tx_b_x",
1154                                                          "uart_rx_b_x";
1155                                                 function = "uart_b";
1156                                                 bias-disable;
1157                                         };
1158                                 };
1159
1160                                 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1161                                         mux {
1162                                                 groups = "uart_cts_b_x",
1163                                                          "uart_rts_b_x";
1164                                                 function = "uart_b";
1165                                                 bias-disable;
1166                                         };
1167                                 };
1168
1169                                 uart_b_z_pins: uart_b_z {
1170                                         mux {
1171                                                 groups = "uart_tx_b_z",
1172                                                          "uart_rx_b_z";
1173                                                 function = "uart_b";
1174                                                 bias-disable;
1175                                         };
1176                                 };
1177
1178                                 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1179                                         mux {
1180                                                 groups = "uart_cts_b_z",
1181                                                          "uart_rts_b_z";
1182                                                 function = "uart_b";
1183                                                 bias-disable;
1184                                         };
1185                                 };
1186
1187                                 uart_ao_b_z_pins: uart_ao_b_z {
1188                                         mux {
1189                                                 groups = "uart_ao_tx_b_z",
1190                                                          "uart_ao_rx_b_z";
1191                                                 function = "uart_ao_b_z";
1192                                                 bias-disable;
1193                                         };
1194                                 };
1195
1196                                 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1197                                         mux {
1198                                                 groups = "uart_ao_cts_b_z",
1199                                                          "uart_ao_rts_b_z";
1200                                                 function = "uart_ao_b_z";
1201                                                 bias-disable;
1202                                         };
1203                                 };
1204                         };
1205                 };
1206
1207                 hiubus: bus@ff63c000 {
1208                         compatible = "simple-bus";
1209                         reg = <0x0 0xff63c000 0x0 0x1c00>;
1210                         #address-cells = <2>;
1211                         #size-cells = <2>;
1212                         ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1213
1214                         sysctrl: system-controller@0 {
1215                                 compatible = "amlogic,meson-axg-hhi-sysctrl",
1216                                              "simple-mfd", "syscon";
1217                                 reg = <0 0 0 0x400>;
1218
1219                                 clkc: clock-controller {
1220                                         compatible = "amlogic,axg-clkc";
1221                                         #clock-cells = <1>;
1222                                         clocks = <&xtal>;
1223                                         clock-names = "xtal";
1224                                 };
1225
1226                                 pwrc: power-controller {
1227                                         compatible = "amlogic,meson-axg-pwrc";
1228                                         #power-domain-cells = <1>;
1229                                         amlogic,ao-sysctrl = <&sysctrl_AO>;
1230                                         resets = <&reset RESET_VIU>,
1231                                                  <&reset RESET_VENC>,
1232                                                  <&reset RESET_VCBUS>,
1233                                                  <&reset RESET_VENCL>,
1234                                                  <&reset RESET_VID_LOCK>;
1235                                         reset-names = "viu", "venc", "vcbus",
1236                                                       "vencl", "vid_lock";
1237                                         clocks = <&clkc CLKID_VPU>,
1238                                                  <&clkc CLKID_VAPB>;
1239                                         clock-names = "vpu", "vapb";
1240                                         /*
1241                                          * VPU clocking is provided by two identical clock paths
1242                                          * VPU_0 and VPU_1 muxed to a single clock by a glitch
1243                                          * free mux to safely change frequency while running.
1244                                          * Same for VAPB but with a final gate after the glitch free mux.
1245                                          */
1246                                         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1247                                                           <&clkc CLKID_VPU_0>,
1248                                                           <&clkc CLKID_VPU>, /* Glitch free mux */
1249                                                           <&clkc CLKID_VAPB_0_SEL>,
1250                                                           <&clkc CLKID_VAPB_0>,
1251                                                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1252                                         assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
1253                                                                  <0>, /* Do Nothing */
1254                                                                  <&clkc CLKID_VPU_0>,
1255                                                                  <&clkc CLKID_FCLK_DIV4>,
1256                                                                  <0>, /* Do Nothing */
1257                                                                  <&clkc CLKID_VAPB_0>;
1258                                         assigned-clock-rates = <0>, /* Do Nothing */
1259                                                                <250000000>,
1260                                                                <0>, /* Do Nothing */
1261                                                                <0>, /* Do Nothing */
1262                                                                <250000000>,
1263                                                                <0>; /* Do Nothing */
1264                                 };
1265
1266                                 mipi_pcie_analog_dphy: phy {
1267                                         compatible = "amlogic,axg-mipi-pcie-analog-phy";
1268                                         #phy-cells = <0>;
1269                                         status = "disabled";
1270                                 };
1271                         };
1272                 };
1273
1274                 mailbox: mailbox@ff63c404 {
1275                         compatible = "amlogic,meson-gxbb-mhu";
1276                         reg = <0 0xff63c404 0 0x4c>;
1277                         interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1278                                      <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1279                                      <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1280                         #mbox-cells = <1>;
1281                 };
1282
1283                 mipi_dphy: phy@ff640000 {
1284                         compatible = "amlogic,axg-mipi-dphy";
1285                         reg = <0x0 0xff640000 0x0 0x100>;
1286                         clocks = <&clkc CLKID_MIPI_DSI_PHY>;
1287                         clock-names = "pclk";
1288                         resets = <&reset RESET_MIPI_PHY>;
1289                         reset-names = "phy";
1290                         phys = <&mipi_pcie_analog_dphy>;
1291                         phy-names = "analog";
1292                         #phy-cells = <0>;
1293                         status = "disabled";
1294                 };
1295
1296                 audio: bus@ff642000 {
1297                         compatible = "simple-bus";
1298                         reg = <0x0 0xff642000 0x0 0x2000>;
1299                         #address-cells = <2>;
1300                         #size-cells = <2>;
1301                         ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1302
1303                         clkc_audio: clock-controller@0 {
1304                                 compatible = "amlogic,axg-audio-clkc";
1305                                 reg = <0x0 0x0 0x0 0xb4>;
1306                                 #clock-cells = <1>;
1307
1308                                 clocks = <&clkc CLKID_AUDIO>,
1309                                          <&clkc CLKID_MPLL0>,
1310                                          <&clkc CLKID_MPLL1>,
1311                                          <&clkc CLKID_MPLL2>,
1312                                          <&clkc CLKID_MPLL3>,
1313                                          <&clkc CLKID_HIFI_PLL>,
1314                                          <&clkc CLKID_FCLK_DIV3>,
1315                                          <&clkc CLKID_FCLK_DIV4>,
1316                                          <&clkc CLKID_GP0_PLL>;
1317                                 clock-names = "pclk",
1318                                               "mst_in0",
1319                                               "mst_in1",
1320                                               "mst_in2",
1321                                               "mst_in3",
1322                                               "mst_in4",
1323                                               "mst_in5",
1324                                               "mst_in6",
1325                                               "mst_in7";
1326
1327                                 resets = <&reset RESET_AUDIO>;
1328                         };
1329
1330                         toddr_a: audio-controller@100 {
1331                                 compatible = "amlogic,axg-toddr";
1332                                 reg = <0x0 0x100 0x0 0x2c>;
1333                                 #sound-dai-cells = <0>;
1334                                 sound-name-prefix = "TODDR_A";
1335                                 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1336                                 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1337                                 resets = <&arb AXG_ARB_TODDR_A>;
1338                                 amlogic,fifo-depth = <512>;
1339                                 status = "disabled";
1340                         };
1341
1342                         toddr_b: audio-controller@140 {
1343                                 compatible = "amlogic,axg-toddr";
1344                                 reg = <0x0 0x140 0x0 0x2c>;
1345                                 #sound-dai-cells = <0>;
1346                                 sound-name-prefix = "TODDR_B";
1347                                 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1348                                 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1349                                 resets = <&arb AXG_ARB_TODDR_B>;
1350                                 amlogic,fifo-depth = <256>;
1351                                 status = "disabled";
1352                         };
1353
1354                         toddr_c: audio-controller@180 {
1355                                 compatible = "amlogic,axg-toddr";
1356                                 reg = <0x0 0x180 0x0 0x2c>;
1357                                 #sound-dai-cells = <0>;
1358                                 sound-name-prefix = "TODDR_C";
1359                                 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1360                                 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1361                                 resets = <&arb AXG_ARB_TODDR_C>;
1362                                 amlogic,fifo-depth = <256>;
1363                                 status = "disabled";
1364                         };
1365
1366                         frddr_a: audio-controller@1c0 {
1367                                 compatible = "amlogic,axg-frddr";
1368                                 reg = <0x0 0x1c0 0x0 0x2c>;
1369                                 #sound-dai-cells = <0>;
1370                                 sound-name-prefix = "FRDDR_A";
1371                                 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1372                                 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1373                                 resets = <&arb AXG_ARB_FRDDR_A>;
1374                                 amlogic,fifo-depth = <512>;
1375                                 status = "disabled";
1376                         };
1377
1378                         frddr_b: audio-controller@200 {
1379                                 compatible = "amlogic,axg-frddr";
1380                                 reg = <0x0 0x200 0x0 0x2c>;
1381                                 #sound-dai-cells = <0>;
1382                                 sound-name-prefix = "FRDDR_B";
1383                                 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1384                                 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1385                                 resets = <&arb AXG_ARB_FRDDR_B>;
1386                                 amlogic,fifo-depth = <256>;
1387                                 status = "disabled";
1388                         };
1389
1390                         frddr_c: audio-controller@240 {
1391                                 compatible = "amlogic,axg-frddr";
1392                                 reg = <0x0 0x240 0x0 0x2c>;
1393                                 #sound-dai-cells = <0>;
1394                                 sound-name-prefix = "FRDDR_C";
1395                                 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1396                                 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1397                                 resets = <&arb AXG_ARB_FRDDR_C>;
1398                                 amlogic,fifo-depth = <256>;
1399                                 status = "disabled";
1400                         };
1401
1402                         arb: reset-controller@280 {
1403                                 compatible = "amlogic,meson-axg-audio-arb";
1404                                 reg = <0x0 0x280 0x0 0x4>;
1405                                 #reset-cells = <1>;
1406                                 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1407                         };
1408
1409                         tdmin_a: audio-controller@300 {
1410                                 compatible = "amlogic,axg-tdmin";
1411                                 reg = <0x0 0x300 0x0 0x40>;
1412                                 sound-name-prefix = "TDMIN_A";
1413                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1414                                          <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1415                                          <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1416                                          <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1417                                          <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1418                                 clock-names = "pclk", "sclk", "sclk_sel",
1419                                               "lrclk", "lrclk_sel";
1420                                 status = "disabled";
1421                         };
1422
1423                         tdmin_b: audio-controller@340 {
1424                                 compatible = "amlogic,axg-tdmin";
1425                                 reg = <0x0 0x340 0x0 0x40>;
1426                                 sound-name-prefix = "TDMIN_B";
1427                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1428                                          <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1429                                          <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1430                                          <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1431                                          <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1432                                 clock-names = "pclk", "sclk", "sclk_sel",
1433                                               "lrclk", "lrclk_sel";
1434                                 status = "disabled";
1435                         };
1436
1437                         tdmin_c: audio-controller@380 {
1438                                 compatible = "amlogic,axg-tdmin";
1439                                 reg = <0x0 0x380 0x0 0x40>;
1440                                 sound-name-prefix = "TDMIN_C";
1441                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1442                                          <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1443                                          <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1444                                          <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1445                                          <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1446                                 clock-names = "pclk", "sclk", "sclk_sel",
1447                                               "lrclk", "lrclk_sel";
1448                                 status = "disabled";
1449                         };
1450
1451                         tdmin_lb: audio-controller@3c0 {
1452                                 compatible = "amlogic,axg-tdmin";
1453                                 reg = <0x0 0x3c0 0x0 0x40>;
1454                                 sound-name-prefix = "TDMIN_LB";
1455                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1456                                          <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1457                                          <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1458                                          <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1459                                          <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1460                                 clock-names = "pclk", "sclk", "sclk_sel",
1461                                               "lrclk", "lrclk_sel";
1462                                 status = "disabled";
1463                         };
1464
1465                         spdifin: audio-controller@400 {
1466                                 compatible = "amlogic,axg-spdifin";
1467                                 reg = <0x0 0x400 0x0 0x30>;
1468                                 #sound-dai-cells = <0>;
1469                                 sound-name-prefix = "SPDIFIN";
1470                                 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1471                                 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1472                                          <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1473                                 clock-names = "pclk", "refclk";
1474                                 status = "disabled";
1475                         };
1476
1477                         spdifout: audio-controller@480 {
1478                                 compatible = "amlogic,axg-spdifout";
1479                                 reg = <0x0 0x480 0x0 0x50>;
1480                                 #sound-dai-cells = <0>;
1481                                 sound-name-prefix = "SPDIFOUT";
1482                                 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1483                                          <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1484                                 clock-names = "pclk", "mclk";
1485                                 status = "disabled";
1486                         };
1487
1488                         tdmout_a: audio-controller@500 {
1489                                 compatible = "amlogic,axg-tdmout";
1490                                 reg = <0x0 0x500 0x0 0x40>;
1491                                 sound-name-prefix = "TDMOUT_A";
1492                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1493                                          <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1494                                          <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1495                                          <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1496                                          <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1497                                 clock-names = "pclk", "sclk", "sclk_sel",
1498                                               "lrclk", "lrclk_sel";
1499                                 status = "disabled";
1500                         };
1501
1502                         tdmout_b: audio-controller@540 {
1503                                 compatible = "amlogic,axg-tdmout";
1504                                 reg = <0x0 0x540 0x0 0x40>;
1505                                 sound-name-prefix = "TDMOUT_B";
1506                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1507                                          <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1508                                          <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1509                                          <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1510                                          <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1511                                 clock-names = "pclk", "sclk", "sclk_sel",
1512                                               "lrclk", "lrclk_sel";
1513                                 status = "disabled";
1514                         };
1515
1516                         tdmout_c: audio-controller@580 {
1517                                 compatible = "amlogic,axg-tdmout";
1518                                 reg = <0x0 0x580 0x0 0x40>;
1519                                 sound-name-prefix = "TDMOUT_C";
1520                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1521                                          <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1522                                          <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1523                                          <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1524                                          <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1525                                 clock-names = "pclk", "sclk", "sclk_sel",
1526                                               "lrclk", "lrclk_sel";
1527                                 status = "disabled";
1528                         };
1529                 };
1530
1531                 aobus: bus@ff800000 {
1532                         compatible = "simple-bus";
1533                         reg = <0x0 0xff800000 0x0 0x100000>;
1534                         #address-cells = <2>;
1535                         #size-cells = <2>;
1536                         ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1537
1538                         sysctrl_AO: sys-ctrl@0 {
1539                                 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1540                                 reg =  <0x0 0x0 0x0 0x100>;
1541
1542                                 clkc_AO: clock-controller {
1543                                         compatible = "amlogic,meson-axg-aoclkc";
1544                                         #clock-cells = <1>;
1545                                         #reset-cells = <1>;
1546                                         clocks = <&xtal>, <&clkc CLKID_CLK81>;
1547                                         clock-names = "xtal", "mpeg-clk";
1548                                 };
1549                         };
1550
1551                         pinctrl_aobus: pinctrl@14 {
1552                                 compatible = "amlogic,meson-axg-aobus-pinctrl";
1553                                 #address-cells = <2>;
1554                                 #size-cells = <2>;
1555                                 ranges;
1556
1557                                 gpio_ao: bank@14 {
1558                                         reg = <0x0 0x00014 0x0 0x8>,
1559                                               <0x0 0x0002c 0x0 0x4>,
1560                                               <0x0 0x00024 0x0 0x8>;
1561                                         reg-names = "mux", "pull", "gpio";
1562                                         gpio-controller;
1563                                         #gpio-cells = <2>;
1564                                         gpio-ranges = <&pinctrl_aobus 0 0 15>;
1565                                 };
1566
1567                                 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1568                                         mux {
1569                                                 groups = "i2c_ao_sck_4";
1570                                                 function = "i2c_ao";
1571                                                 bias-disable;
1572                                         };
1573                                 };
1574
1575                                 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1576                                         mux {
1577                                                 groups = "i2c_ao_sck_8";
1578                                                 function = "i2c_ao";
1579                                                 bias-disable;
1580                                         };
1581                                 };
1582
1583                                 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1584                                         mux {
1585                                                 groups = "i2c_ao_sck_10";
1586                                                 function = "i2c_ao";
1587                                                 bias-disable;
1588                                         };
1589                                 };
1590
1591                                 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1592                                         mux {
1593                                                 groups = "i2c_ao_sda_5";
1594                                                 function = "i2c_ao";
1595                                                 bias-disable;
1596                                         };
1597                                 };
1598
1599                                 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1600                                         mux {
1601                                                 groups = "i2c_ao_sda_9";
1602                                                 function = "i2c_ao";
1603                                                 bias-disable;
1604                                         };
1605                                 };
1606
1607                                 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1608                                         mux {
1609                                                 groups = "i2c_ao_sda_11";
1610                                                 function = "i2c_ao";
1611                                                 bias-disable;
1612                                         };
1613                                 };
1614
1615                                 remote_input_ao_pins: remote_input_ao {
1616                                         mux {
1617                                                 groups = "remote_input_ao";
1618                                                 function = "remote_input_ao";
1619                                                 bias-disable;
1620                                         };
1621                                 };
1622
1623                                 uart_ao_a_pins: uart_ao_a {
1624                                         mux {
1625                                                 groups = "uart_ao_tx_a",
1626                                                          "uart_ao_rx_a";
1627                                                 function = "uart_ao_a";
1628                                                 bias-disable;
1629                                         };
1630                                 };
1631
1632                                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1633                                         mux {
1634                                                 groups = "uart_ao_cts_a",
1635                                                          "uart_ao_rts_a";
1636                                                 function = "uart_ao_a";
1637                                                 bias-disable;
1638                                         };
1639                                 };
1640
1641                                 uart_ao_b_pins: uart_ao_b {
1642                                         mux {
1643                                                 groups = "uart_ao_tx_b",
1644                                                          "uart_ao_rx_b";
1645                                                 function = "uart_ao_b";
1646                                                 bias-disable;
1647                                         };
1648                                 };
1649
1650                                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1651                                         mux {
1652                                                 groups = "uart_ao_cts_b",
1653                                                          "uart_ao_rts_b";
1654                                                 function = "uart_ao_b";
1655                                                 bias-disable;
1656                                         };
1657                                 };
1658                         };
1659
1660                         sec_AO: ao-secure@140 {
1661                                 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1662                                 reg = <0x0 0x140 0x0 0x140>;
1663                                 amlogic,has-chip-id;
1664                         };
1665
1666                         pwm_AO_cd: pwm@2000 {
1667                                 compatible = "amlogic,meson-axg-ao-pwm";
1668                                 reg = <0x0 0x02000  0x0 0x20>;
1669                                 #pwm-cells = <3>;
1670                                 status = "disabled";
1671                         };
1672
1673                         uart_AO: serial@3000 {
1674                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1675                                 reg = <0x0 0x3000 0x0 0x18>;
1676                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1677                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1678                                 clock-names = "xtal", "pclk", "baud";
1679                                 status = "disabled";
1680                         };
1681
1682                         uart_AO_B: serial@4000 {
1683                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1684                                 reg = <0x0 0x4000 0x0 0x18>;
1685                                 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1686                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1687                                 clock-names = "xtal", "pclk", "baud";
1688                                 status = "disabled";
1689                         };
1690
1691                         i2c_AO: i2c@5000 {
1692                                 compatible = "amlogic,meson-axg-i2c";
1693                                 reg = <0x0 0x05000 0x0 0x20>;
1694                                 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1695                                 clocks = <&clkc CLKID_AO_I2C>;
1696                                 #address-cells = <1>;
1697                                 #size-cells = <0>;
1698                                 status = "disabled";
1699                         };
1700
1701                         pwm_AO_ab: pwm@7000 {
1702                                 compatible = "amlogic,meson-axg-ao-pwm";
1703                                 reg = <0x0 0x07000 0x0 0x20>;
1704                                 #pwm-cells = <3>;
1705                                 status = "disabled";
1706                         };
1707
1708                         ir: ir@8000 {
1709                                 compatible = "amlogic,meson-gxbb-ir";
1710                                 reg = <0x0 0x8000 0x0 0x20>;
1711                                 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1712                                 status = "disabled";
1713                         };
1714
1715                         saradc: adc@9000 {
1716                                 compatible = "amlogic,meson-axg-saradc",
1717                                         "amlogic,meson-saradc";
1718                                 reg = <0x0 0x9000 0x0 0x38>;
1719                                 #io-channel-cells = <1>;
1720                                 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1721                                 clocks = <&xtal>,
1722                                          <&clkc_AO CLKID_AO_SAR_ADC>,
1723                                          <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1724                                          <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1725                                 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1726                                 status = "disabled";
1727                         };
1728                 };
1729
1730                 ge2d: ge2d@ff940000 {
1731                         compatible = "amlogic,axg-ge2d";
1732                         reg = <0x0 0xff940000 0x0 0x10000>;
1733                         interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
1734                         clocks = <&clkc CLKID_VAPB>;
1735                         resets = <&reset RESET_GE2D>;
1736                         reset-names = "core";
1737                 };
1738
1739                 gic: interrupt-controller@ffc01000 {
1740                         compatible = "arm,gic-400";
1741                         reg = <0x0 0xffc01000 0 0x1000>,
1742                               <0x0 0xffc02000 0 0x2000>,
1743                               <0x0 0xffc04000 0 0x2000>,
1744                               <0x0 0xffc06000 0 0x2000>;
1745                         interrupt-controller;
1746                         interrupts = <GIC_PPI 9
1747                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1748                         #interrupt-cells = <3>;
1749                         #address-cells = <0>;
1750                 };
1751
1752                 cbus: bus@ffd00000 {
1753                         compatible = "simple-bus";
1754                         reg = <0x0 0xffd00000 0x0 0x25000>;
1755                         #address-cells = <2>;
1756                         #size-cells = <2>;
1757                         ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1758
1759                         reset: reset-controller@1004 {
1760                                 compatible = "amlogic,meson-axg-reset";
1761                                 reg = <0x0 0x01004 0x0 0x9c>;
1762                                 #reset-cells = <1>;
1763                         };
1764
1765                         gpio_intc: interrupt-controller@f080 {
1766                                 compatible = "amlogic,meson-axg-gpio-intc",
1767                                              "amlogic,meson-gpio-intc";
1768                                 reg = <0x0 0xf080 0x0 0x10>;
1769                                 interrupt-controller;
1770                                 #interrupt-cells = <2>;
1771                                 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1772                         };
1773
1774                         watchdog@f0d0 {
1775                                 compatible = "amlogic,meson-gxbb-wdt";
1776                                 reg = <0x0 0xf0d0 0x0 0x10>;
1777                                 clocks = <&xtal>;
1778                         };
1779
1780                         pwm_ab: pwm@1b000 {
1781                                 compatible = "amlogic,meson-axg-ee-pwm";
1782                                 reg = <0x0 0x1b000 0x0 0x20>;
1783                                 #pwm-cells = <3>;
1784                                 status = "disabled";
1785                         };
1786
1787                         pwm_cd: pwm@1a000 {
1788                                 compatible = "amlogic,meson-axg-ee-pwm";
1789                                 reg = <0x0 0x1a000 0x0 0x20>;
1790                                 #pwm-cells = <3>;
1791                                 status = "disabled";
1792                         };
1793
1794                         spicc0: spi@13000 {
1795                                 compatible = "amlogic,meson-axg-spicc";
1796                                 reg = <0x0 0x13000 0x0 0x3c>;
1797                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1798                                 clocks = <&clkc CLKID_SPICC0>;
1799                                 clock-names = "core";
1800                                 #address-cells = <1>;
1801                                 #size-cells = <0>;
1802                                 status = "disabled";
1803                         };
1804
1805                         spicc1: spi@15000 {
1806                                 compatible = "amlogic,meson-axg-spicc";
1807                                 reg = <0x0 0x15000 0x0 0x3c>;
1808                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1809                                 clocks = <&clkc CLKID_SPICC1>;
1810                                 clock-names = "core";
1811                                 #address-cells = <1>;
1812                                 #size-cells = <0>;
1813                                 status = "disabled";
1814                         };
1815
1816                         clk_msr: clock-measure@18000 {
1817                                 compatible = "amlogic,meson-axg-clk-measure";
1818                                 reg = <0x0 0x18000 0x0 0x10>;
1819                         };
1820
1821                         i2c3: i2c@1c000 {
1822                                 compatible = "amlogic,meson-axg-i2c";
1823                                 reg = <0x0 0x1c000 0x0 0x20>;
1824                                 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1825                                 clocks = <&clkc CLKID_I2C>;
1826                                 #address-cells = <1>;
1827                                 #size-cells = <0>;
1828                                 status = "disabled";
1829                         };
1830
1831                         i2c2: i2c@1d000 {
1832                                 compatible = "amlogic,meson-axg-i2c";
1833                                 reg = <0x0 0x1d000 0x0 0x20>;
1834                                 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1835                                 clocks = <&clkc CLKID_I2C>;
1836                                 #address-cells = <1>;
1837                                 #size-cells = <0>;
1838                                 status = "disabled";
1839                         };
1840
1841                         i2c1: i2c@1e000 {
1842                                 compatible = "amlogic,meson-axg-i2c";
1843                                 reg = <0x0 0x1e000 0x0 0x20>;
1844                                 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1845                                 clocks = <&clkc CLKID_I2C>;
1846                                 #address-cells = <1>;
1847                                 #size-cells = <0>;
1848                                 status = "disabled";
1849                         };
1850
1851                         i2c0: i2c@1f000 {
1852                                 compatible = "amlogic,meson-axg-i2c";
1853                                 reg = <0x0 0x1f000 0x0 0x20>;
1854                                 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1855                                 clocks = <&clkc CLKID_I2C>;
1856                                 #address-cells = <1>;
1857                                 #size-cells = <0>;
1858                                 status = "disabled";
1859                         };
1860
1861                         uart_B: serial@23000 {
1862                                 compatible = "amlogic,meson-gx-uart";
1863                                 reg = <0x0 0x23000 0x0 0x18>;
1864                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1865                                 status = "disabled";
1866                                 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1867                                 clock-names = "xtal", "pclk", "baud";
1868                         };
1869
1870                         uart_A: serial@24000 {
1871                                 compatible = "amlogic,meson-gx-uart";
1872                                 reg = <0x0 0x24000 0x0 0x18>;
1873                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1874                                 status = "disabled";
1875                                 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1876                                 clock-names = "xtal", "pclk", "baud";
1877                         };
1878                 };
1879
1880                 apb: bus@ffe00000 {
1881                         compatible = "simple-bus";
1882                         reg = <0x0 0xffe00000 0x0 0x200000>;
1883                         #address-cells = <2>;
1884                         #size-cells = <2>;
1885                         ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1886
1887                         sd_emmc_b: sd@5000 {
1888                                 compatible = "amlogic,meson-axg-mmc";
1889                                 reg = <0x0 0x5000 0x0 0x800>;
1890                                 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1891                                 status = "disabled";
1892                                 clocks = <&clkc CLKID_SD_EMMC_B>,
1893                                         <&clkc CLKID_SD_EMMC_B_CLK0>,
1894                                         <&clkc CLKID_FCLK_DIV2>;
1895                                 clock-names = "core", "clkin0", "clkin1";
1896                                 resets = <&reset RESET_SD_EMMC_B>;
1897                         };
1898
1899                         sd_emmc_c: mmc@7000 {
1900                                 compatible = "amlogic,meson-axg-mmc";
1901                                 reg = <0x0 0x7000 0x0 0x800>;
1902                                 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1903                                 status = "disabled";
1904                                 clocks = <&clkc CLKID_SD_EMMC_C>,
1905                                         <&clkc CLKID_SD_EMMC_C_CLK0>,
1906                                         <&clkc CLKID_FCLK_DIV2>;
1907                                 clock-names = "core", "clkin0", "clkin1";
1908                                 resets = <&reset RESET_SD_EMMC_C>;
1909                         };
1910
1911                         usb2_phy1: phy@9020 {
1912                                 compatible = "amlogic,meson-gxl-usb2-phy";
1913                                 #phy-cells = <0>;
1914                                 reg = <0x0 0x9020 0x0 0x20>;
1915                                 clocks = <&clkc CLKID_USB>;
1916                                 clock-names = "phy";
1917                                 resets = <&reset RESET_USB_OTG>;
1918                                 reset-names = "phy";
1919                         };
1920                 };
1921
1922                 sram: sram@fffc0000 {
1923                         compatible = "mmio-sram";
1924                         reg = <0x0 0xfffc0000 0x0 0x20000>;
1925                         #address-cells = <1>;
1926                         #size-cells = <1>;
1927                         ranges = <0 0x0 0xfffc0000 0x20000>;
1928
1929                         cpu_scp_lpri: scp-sram@13000 {
1930                                 compatible = "amlogic,meson-axg-scp-shmem";
1931                                 reg = <0x13000 0x400>;
1932                         };
1933
1934                         cpu_scp_hpri: scp-sram@13400 {
1935                                 compatible = "amlogic,meson-axg-scp-shmem";
1936                                 reg = <0x13400 0x400>;
1937                         };
1938                 };
1939         };
1940
1941         timer {
1942                 compatible = "arm,armv8-timer";
1943                 interrupts = <GIC_PPI 13
1944                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1945                              <GIC_PPI 14
1946                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1947                              <GIC_PPI 11
1948                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1949                              <GIC_PPI 10
1950                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1951         };
1952
1953         xtal: xtal-clk {
1954                 compatible = "fixed-clock";
1955                 clock-frequency = <24000000>;
1956                 clock-output-names = "xtal";
1957                 #clock-cells = <0>;
1958         };
1959 };