arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
   6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
   7 #include <dt-bindings/clock/sun8i-de2.h>
   8 #include <dt-bindings/clock/sun8i-tcon-top.h>
   9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
  10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
  11 #include <dt-bindings/reset/sun8i-de2.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         interrupt-parent = <&gic>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu0: cpu@0 {
  24                         compatible = "arm,cortex-a53";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         enable-method = "psci";
  28                         clocks = <&ccu CLK_CPUX>;
  29                         clock-latency-ns = <244144>; /* 8 32k periods */
  30                         #cooling-cells = <2>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         compatible = "arm,cortex-a53";
  35                         device_type = "cpu";
  36                         reg = <1>;
  37                         enable-method = "psci";
  38                         clocks = <&ccu CLK_CPUX>;
  39                         clock-latency-ns = <244144>; /* 8 32k periods */
  40                         #cooling-cells = <2>;
  41                 };
  42
  43                 cpu2: cpu@2 {
  44                         compatible = "arm,cortex-a53";
  45                         device_type = "cpu";
  46                         reg = <2>;
  47                         enable-method = "psci";
  48                         clocks = <&ccu CLK_CPUX>;
  49                         clock-latency-ns = <244144>; /* 8 32k periods */
  50                         #cooling-cells = <2>;
  51                 };
  52
  53                 cpu3: cpu@3 {
  54                         compatible = "arm,cortex-a53";
  55                         device_type = "cpu";
  56                         reg = <3>;
  57                         enable-method = "psci";
  58                         clocks = <&ccu CLK_CPUX>;
  59                         clock-latency-ns = <244144>; /* 8 32k periods */
  60                         #cooling-cells = <2>;
  61                 };
  62         };
  63
  64         de: display-engine {
  65                 compatible = "allwinner,sun50i-h6-display-engine";
  66                 allwinner,pipelines = <&mixer0>;
  67                 status = "disabled";
  68         };
  69
  70         osc24M: osc24M_clk {
  71                 #clock-cells = <0>;
  72                 compatible = "fixed-clock";
  73                 clock-frequency = <24000000>;
  74                 clock-output-names = "osc24M";
  75         };
  76
  77         pmu {
  78                 compatible = "arm,cortex-a53-pmu";
  79                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         psci {
  87                 compatible = "arm,psci-0.2";
  88                 method = "smc";
  89         };
  90
  91         timer {
  92                 compatible = "arm,armv8-timer";
  93                 arm,no-tick-in-suspend;
  94                 interrupts = <GIC_PPI 13
  95                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  96                              <GIC_PPI 14
  97                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  98                              <GIC_PPI 11
  99                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 100                              <GIC_PPI 10
 101                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 102         };
 103
 104         soc {
 105                 compatible = "simple-bus";
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 bus@1000000 {
 111                         compatible = "allwinner,sun50i-h6-de3",
 112                                      "allwinner,sun50i-a64-de2";
 113                         reg = <0x1000000 0x400000>;
 114                         allwinner,sram = <&de2_sram 1>;
 115                         #address-cells = <1>;
 116                         #size-cells = <1>;
 117                         ranges = <0 0x1000000 0x400000>;
 118
 119                         display_clocks: clock@0 {
 120                                 compatible = "allwinner,sun50i-h6-de3-clk";
 121                                 reg = <0x0 0x10000>;
 122                                 clocks = <&ccu CLK_DE>,
 123                                          <&ccu CLK_BUS_DE>;
 124                                 clock-names = "mod",
 125                                               "bus";
 126                                 resets = <&ccu RST_BUS_DE>;
 127                                 #clock-cells = <1>;
 128                                 #reset-cells = <1>;
 129                         };
 130
 131                         mixer0: mixer@100000 {
 132                                 compatible = "allwinner,sun50i-h6-de3-mixer-0";
 133                                 reg = <0x100000 0x100000>;
 134                                 clocks = <&display_clocks CLK_BUS_MIXER0>,
 135                                          <&display_clocks CLK_MIXER0>;
 136                                 clock-names = "bus",
 137                                               "mod";
 138                                 resets = <&display_clocks RST_MIXER0>;
 139                                 iommus = <&iommu 0>;
 140
 141                                 ports {
 142                                         #address-cells = <1>;
 143                                         #size-cells = <0>;
 144
 145                                         mixer0_out: port@1 {
 146                                                 reg = <1>;
 147
 148                                                 mixer0_out_tcon_top_mixer0: endpoint {
 149                                                         remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 150                                                 };
 151                                         };
 152                                 };
 153                         };
 154                 };
 155
 156                 video-codec@1c0e000 {
 157                         compatible = "allwinner,sun50i-h6-video-engine";
 158                         reg = <0x01c0e000 0x2000>;
 159                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 160                                  <&ccu CLK_MBUS_VE>;
 161                         clock-names = "ahb", "mod", "ram";
 162                         resets = <&ccu RST_BUS_VE>;
 163                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 164                         allwinner,sram = <&ve_sram 1>;
 165                         iommus = <&iommu 3>;
 166                 };
 167
 168                 gpu: gpu@1800000 {
 169                         compatible = "allwinner,sun50i-h6-mali",
 170                                      "arm,mali-t720";
 171                         reg = <0x01800000 0x4000>;
 172                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 173                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 174                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 175                         interrupt-names = "job", "mmu", "gpu";
 176                         clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
 177                         clock-names = "core", "bus";
 178                         resets = <&ccu RST_BUS_GPU>;
 179                         status = "disabled";
 180                 };
 181
 182                 crypto: crypto@1904000 {
 183                         compatible = "allwinner,sun50i-h6-crypto";
 184                         reg = <0x01904000 0x1000>;
 185                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 186                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
 187                         clock-names = "bus", "mod", "ram";
 188                         resets = <&ccu RST_BUS_CE>;
 189                 };
 190
 191                 syscon: syscon@3000000 {
 192                         compatible = "allwinner,sun50i-h6-system-control",
 193                                      "allwinner,sun50i-a64-system-control";
 194                         reg = <0x03000000 0x1000>;
 195                         #address-cells = <1>;
 196                         #size-cells = <1>;
 197                         ranges;
 198
 199                         sram_c: sram@28000 {
 200                                 compatible = "mmio-sram";
 201                                 reg = <0x00028000 0x1e000>;
 202                                 #address-cells = <1>;
 203                                 #size-cells = <1>;
 204                                 ranges = <0 0x00028000 0x1e000>;
 205
 206                                 de2_sram: sram-section@0 {
 207                                         compatible = "allwinner,sun50i-h6-sram-c",
 208                                                      "allwinner,sun50i-a64-sram-c";
 209                                         reg = <0x0000 0x1e000>;
 210                                 };
 211                         };
 212
 213                         sram_c1: sram@1a00000 {
 214                                 compatible = "mmio-sram";
 215                                 reg = <0x01a00000 0x200000>;
 216                                 #address-cells = <1>;
 217                                 #size-cells = <1>;
 218                                 ranges = <0 0x01a00000 0x200000>;
 219
 220                                 ve_sram: sram-section@0 {
 221                                         compatible = "allwinner,sun50i-h6-sram-c1",
 222                                                      "allwinner,sun4i-a10-sram-c1";
 223                                         reg = <0x000000 0x200000>;
 224                                 };
 225                         };
 226                 };
 227
 228                 ccu: clock@3001000 {
 229                         compatible = "allwinner,sun50i-h6-ccu";
 230                         reg = <0x03001000 0x1000>;
 231                         clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
 232                         clock-names = "hosc", "losc", "iosc";
 233                         #clock-cells = <1>;
 234                         #reset-cells = <1>;
 235                 };
 236
 237                 dma: dma-controller@3002000 {
 238                         compatible = "allwinner,sun50i-h6-dma";
 239                         reg = <0x03002000 0x1000>;
 240                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
 242                         clock-names = "bus", "mbus";
 243                         dma-channels = <16>;
 244                         dma-requests = <46>;
 245                         resets = <&ccu RST_BUS_DMA>;
 246                         #dma-cells = <1>;
 247                 };
 248
 249                 msgbox: mailbox@3003000 {
 250                         compatible = "allwinner,sun50i-h6-msgbox",
 251                                      "allwinner,sun6i-a31-msgbox";
 252                         reg = <0x03003000 0x1000>;
 253                         clocks = <&ccu CLK_BUS_MSGBOX>;
 254                         resets = <&ccu RST_BUS_MSGBOX>;
 255                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 256                         #mbox-cells = <1>;
 257                 };
 258
 259                 sid: efuse@3006000 {
 260                         compatible = "allwinner,sun50i-h6-sid";
 261                         reg = <0x03006000 0x400>;
 262                         #address-cells = <1>;
 263                         #size-cells = <1>;
 264
 265                         ths_calibration: thermal-sensor-calibration@14 {
 266                                 reg = <0x14 0x8>;
 267                         };
 268
 269                         cpu_speed_grade: cpu-speed-grade@1c {
 270                                 reg = <0x1c 0x4>;
 271                         };
 272                 };
 273
 274                 watchdog: watchdog@30090a0 {
 275                         compatible = "allwinner,sun50i-h6-wdt",
 276                                      "allwinner,sun6i-a31-wdt";
 277                         reg = <0x030090a0 0x20>;
 278                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&osc24M>;
 280                         /* Broken on some H6 boards */
 281                         status = "disabled";
 282                 };
 283
 284                 pwm: pwm@300a000 {
 285                         compatible = "allwinner,sun50i-h6-pwm";
 286                         reg = <0x0300a000 0x400>;
 287                         clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
 288                         clock-names = "mod", "bus";
 289                         resets = <&ccu RST_BUS_PWM>;
 290                         #pwm-cells = <3>;
 291                         status = "disabled";
 292                 };
 293
 294                 pio: pinctrl@300b000 {
 295                         compatible = "allwinner,sun50i-h6-pinctrl";
 296                         reg = <0x0300b000 0x400>;
 297                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 298                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 299                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 300                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 301                         clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
 302                         clock-names = "apb", "hosc", "losc";
 303                         gpio-controller;
 304                         #gpio-cells = <3>;
 305                         interrupt-controller;
 306                         #interrupt-cells = <3>;
 307
 308                         ext_rgmii_pins: rgmii-pins {
 309                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 310                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 311                                        "PD11", "PD12", "PD13", "PD19", "PD20";
 312                                 function = "emac";
 313                                 drive-strength = <40>;
 314                         };
 315
 316                         hdmi_pins: hdmi-pins {
 317                                 pins = "PH8", "PH9", "PH10";
 318                                 function = "hdmi";
 319                         };
 320
 321                         i2c0_pins: i2c0-pins {
 322                                 pins = "PD25", "PD26";
 323                                 function = "i2c0";
 324                         };
 325
 326                         i2c1_pins: i2c1-pins {
 327                                 pins = "PH5", "PH6";
 328                                 function = "i2c1";
 329                         };
 330
 331                         i2c2_pins: i2c2-pins {
 332                                 pins = "PD23", "PD24";
 333                                 function = "i2c2";
 334                         };
 335
 336                         mmc0_pins: mmc0-pins {
 337                                 pins = "PF0", "PF1", "PF2", "PF3",
 338                                        "PF4", "PF5";
 339                                 function = "mmc0";
 340                                 drive-strength = <30>;
 341                                 bias-pull-up;
 342                         };
 343
 344                         /omit-if-no-ref/
 345                         mmc1_pins: mmc1-pins {
 346                                 pins = "PG0", "PG1", "PG2", "PG3",
 347                                        "PG4", "PG5";
 348                                 function = "mmc1";
 349                                 drive-strength = <30>;
 350                                 bias-pull-up;
 351                         };
 352
 353                         mmc2_pins: mmc2-pins {
 354                                 pins = "PC1", "PC4", "PC5", "PC6",
 355                                        "PC7", "PC8", "PC9", "PC10",
 356                                        "PC11", "PC12", "PC13", "PC14";
 357                                 function = "mmc2";
 358                                 drive-strength = <30>;
 359                                 bias-pull-up;
 360                         };
 361
 362                         /omit-if-no-ref/
 363                         spi0_pins: spi0-pins {
 364                                 pins = "PC0", "PC2", "PC3";
 365                                 function = "spi0";
 366                         };
 367
 368                         /* pin shared with MMC2-CMD (eMMC) */
 369                         /omit-if-no-ref/
 370                         spi0_cs_pin: spi0-cs-pin {
 371                                 pins = "PC5";
 372                                 function = "spi0";
 373                         };
 374
 375                         /omit-if-no-ref/
 376                         spi1_pins: spi1-pins {
 377                                 pins = "PH4", "PH5", "PH6";
 378                                 function = "spi1";
 379                         };
 380
 381                         /omit-if-no-ref/
 382                         spi1_cs_pin: spi1-cs-pin {
 383                                 pins = "PH3";
 384                                 function = "spi1";
 385                         };
 386
 387                         spdif_tx_pin: spdif-tx-pin {
 388                                 pins = "PH7";
 389                                 function = "spdif";
 390                         };
 391
 392                         uart0_ph_pins: uart0-ph-pins {
 393                                 pins = "PH0", "PH1";
 394                                 function = "uart0";
 395                         };
 396
 397                         uart1_pins: uart1-pins {
 398                                 pins = "PG6", "PG7";
 399                                 function = "uart1";
 400                         };
 401
 402                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 403                                 pins = "PG8", "PG9";
 404                                 function = "uart1";
 405                         };
 406                 };
 407
 408                 gic: interrupt-controller@3021000 {
 409                         compatible = "arm,gic-400";
 410                         reg = <0x03021000 0x1000>,
 411                               <0x03022000 0x2000>,
 412                               <0x03024000 0x2000>,
 413                               <0x03026000 0x2000>;
 414                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 415                         interrupt-controller;
 416                         #interrupt-cells = <3>;
 417                 };
 418
 419                 iommu: iommu@30f0000 {
 420                         compatible = "allwinner,sun50i-h6-iommu";
 421                         reg = <0x030f0000 0x10000>;
 422                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 423                         clocks = <&ccu CLK_BUS_IOMMU>;
 424                         resets = <&ccu RST_BUS_IOMMU>;
 425                         #iommu-cells = <1>;
 426                 };
 427
 428                 mmc0: mmc@4020000 {
 429                         compatible = "allwinner,sun50i-h6-mmc",
 430                                      "allwinner,sun50i-a64-mmc";
 431                         reg = <0x04020000 0x1000>;
 432                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 433                         clock-names = "ahb", "mmc";
 434                         resets = <&ccu RST_BUS_MMC0>;
 435                         reset-names = "ahb";
 436                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 437                         pinctrl-names = "default";
 438                         pinctrl-0 = <&mmc0_pins>;
 439                         status = "disabled";
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                 };
 443
 444                 mmc1: mmc@4021000 {
 445                         compatible = "allwinner,sun50i-h6-mmc",
 446                                      "allwinner,sun50i-a64-mmc";
 447                         reg = <0x04021000 0x1000>;
 448                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 449                         clock-names = "ahb", "mmc";
 450                         resets = <&ccu RST_BUS_MMC1>;
 451                         reset-names = "ahb";
 452                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 453                         pinctrl-names = "default";
 454                         pinctrl-0 = <&mmc1_pins>;
 455                         status = "disabled";
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                 };
 459
 460                 mmc2: mmc@4022000 {
 461                         compatible = "allwinner,sun50i-h6-emmc",
 462                                      "allwinner,sun50i-a64-emmc";
 463                         reg = <0x04022000 0x1000>;
 464                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 465                         clock-names = "ahb", "mmc";
 466                         resets = <&ccu RST_BUS_MMC2>;
 467                         reset-names = "ahb";
 468                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 469                         pinctrl-names = "default";
 470                         pinctrl-0 = <&mmc2_pins>;
 471                         status = "disabled";
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                 };
 475
 476                 uart0: serial@5000000 {
 477                         compatible = "snps,dw-apb-uart";
 478                         reg = <0x05000000 0x400>;
 479                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 480                         reg-shift = <2>;
 481                         reg-io-width = <4>;
 482                         clocks = <&ccu CLK_BUS_UART0>;
 483                         resets = <&ccu RST_BUS_UART0>;
 484                         status = "disabled";
 485                 };
 486
 487                 uart1: serial@5000400 {
 488                         compatible = "snps,dw-apb-uart";
 489                         reg = <0x05000400 0x400>;
 490                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 491                         reg-shift = <2>;
 492                         reg-io-width = <4>;
 493                         clocks = <&ccu CLK_BUS_UART1>;
 494                         resets = <&ccu RST_BUS_UART1>;
 495                         status = "disabled";
 496                 };
 497
 498                 uart2: serial@5000800 {
 499                         compatible = "snps,dw-apb-uart";
 500                         reg = <0x05000800 0x400>;
 501                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 502                         reg-shift = <2>;
 503                         reg-io-width = <4>;
 504                         clocks = <&ccu CLK_BUS_UART2>;
 505                         resets = <&ccu RST_BUS_UART2>;
 506                         status = "disabled";
 507                 };
 508
 509                 uart3: serial@5000c00 {
 510                         compatible = "snps,dw-apb-uart";
 511                         reg = <0x05000c00 0x400>;
 512                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 513                         reg-shift = <2>;
 514                         reg-io-width = <4>;
 515                         clocks = <&ccu CLK_BUS_UART3>;
 516                         resets = <&ccu RST_BUS_UART3>;
 517                         status = "disabled";
 518                 };
 519
 520                 i2c0: i2c@5002000 {
 521                         compatible = "allwinner,sun50i-h6-i2c",
 522                                      "allwinner,sun6i-a31-i2c";
 523                         reg = <0x05002000 0x400>;
 524                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&ccu CLK_BUS_I2C0>;
 526                         resets = <&ccu RST_BUS_I2C0>;
 527                         pinctrl-names = "default";
 528                         pinctrl-0 = <&i2c0_pins>;
 529                         status = "disabled";
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                 };
 533
 534                 i2c1: i2c@5002400 {
 535                         compatible = "allwinner,sun50i-h6-i2c",
 536                                      "allwinner,sun6i-a31-i2c";
 537                         reg = <0x05002400 0x400>;
 538                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 539                         clocks = <&ccu CLK_BUS_I2C1>;
 540                         resets = <&ccu RST_BUS_I2C1>;
 541                         pinctrl-names = "default";
 542                         pinctrl-0 = <&i2c1_pins>;
 543                         status = "disabled";
 544                         #address-cells = <1>;
 545                         #size-cells = <0>;
 546                 };
 547
 548                 i2c2: i2c@5002800 {
 549                         compatible = "allwinner,sun50i-h6-i2c",
 550                                      "allwinner,sun6i-a31-i2c";
 551                         reg = <0x05002800 0x400>;
 552                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 553                         clocks = <&ccu CLK_BUS_I2C2>;
 554                         resets = <&ccu RST_BUS_I2C2>;
 555                         pinctrl-names = "default";
 556                         pinctrl-0 = <&i2c2_pins>;
 557                         status = "disabled";
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                 };
 561
 562                 spi0: spi@5010000 {
 563                         compatible = "allwinner,sun50i-h6-spi",
 564                                      "allwinner,sun8i-h3-spi";
 565                         reg = <0x05010000 0x1000>;
 566                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 567                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 568                         clock-names = "ahb", "mod";
 569                         dmas = <&dma 22>, <&dma 22>;
 570                         dma-names = "rx", "tx";
 571                         resets = <&ccu RST_BUS_SPI0>;
 572                         status = "disabled";
 573                         #address-cells = <1>;
 574                         #size-cells = <0>;
 575                 };
 576
 577                 spi1: spi@5011000 {
 578                         compatible = "allwinner,sun50i-h6-spi",
 579                                      "allwinner,sun8i-h3-spi";
 580                         reg = <0x05011000 0x1000>;
 581                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 582                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 583                         clock-names = "ahb", "mod";
 584                         dmas = <&dma 23>, <&dma 23>;
 585                         dma-names = "rx", "tx";
 586                         resets = <&ccu RST_BUS_SPI1>;
 587                         status = "disabled";
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                 };
 591
 592                 emac: ethernet@5020000 {
 593                         compatible = "allwinner,sun50i-h6-emac",
 594                                      "allwinner,sun50i-a64-emac";
 595                         syscon = <&syscon>;
 596                         reg = <0x05020000 0x10000>;
 597                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 598                         interrupt-names = "macirq";
 599                         resets = <&ccu RST_BUS_EMAC>;
 600                         reset-names = "stmmaceth";
 601                         clocks = <&ccu CLK_BUS_EMAC>;
 602                         clock-names = "stmmaceth";
 603                         status = "disabled";
 604
 605                         mdio: mdio {
 606                                 compatible = "snps,dwmac-mdio";
 607                                 #address-cells = <1>;
 608                                 #size-cells = <0>;
 609                         };
 610                 };
 611
 612                 i2s1: i2s@5091000 {
 613                         #sound-dai-cells = <0>;
 614                         compatible = "allwinner,sun50i-h6-i2s";
 615                         reg = <0x05091000 0x1000>;
 616                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 617                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 618                         clock-names = "apb", "mod";
 619                         dmas = <&dma 4>, <&dma 4>;
 620                         resets = <&ccu RST_BUS_I2S1>;
 621                         dma-names = "rx", "tx";
 622                         status = "disabled";
 623                 };
 624
 625                 spdif: spdif@5093000 {
 626                         #sound-dai-cells = <0>;
 627                         compatible = "allwinner,sun50i-h6-spdif";
 628                         reg = <0x05093000 0x400>;
 629                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 630                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 631                         clock-names = "apb", "spdif";
 632                         resets = <&ccu RST_BUS_SPDIF>;
 633                         dmas = <&dma 2>;
 634                         dma-names = "tx";
 635                         pinctrl-names = "default";
 636                         pinctrl-0 = <&spdif_tx_pin>;
 637                         status = "disabled";
 638                 };
 639
 640                 usb2otg: usb@5100000 {
 641                         compatible = "allwinner,sun50i-h6-musb",
 642                                      "allwinner,sun8i-a33-musb";
 643                         reg = <0x05100000 0x0400>;
 644                         clocks = <&ccu CLK_BUS_OTG>;
 645                         resets = <&ccu RST_BUS_OTG>;
 646                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 647                         interrupt-names = "mc";
 648                         phys = <&usb2phy 0>;
 649                         phy-names = "usb";
 650                         extcon = <&usb2phy 0>;
 651                         status = "disabled";
 652                 };
 653
 654                 usb2phy: phy@5100400 {
 655                         compatible = "allwinner,sun50i-h6-usb-phy";
 656                         reg = <0x05100400 0x24>,
 657                               <0x05101800 0x4>,
 658                               <0x05311800 0x4>;
 659                         reg-names = "phy_ctrl",
 660                                     "pmu0",
 661                                     "pmu3";
 662                         clocks = <&ccu CLK_USB_PHY0>,
 663                                  <&ccu CLK_USB_PHY3>;
 664                         clock-names = "usb0_phy",
 665                                       "usb3_phy";
 666                         resets = <&ccu RST_USB_PHY0>,
 667                                  <&ccu RST_USB_PHY3>;
 668                         reset-names = "usb0_reset",
 669                                       "usb3_reset";
 670                         status = "disabled";
 671                         #phy-cells = <1>;
 672                 };
 673
 674                 ehci0: usb@5101000 {
 675                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 676                         reg = <0x05101000 0x100>;
 677                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 678                         clocks = <&ccu CLK_BUS_OHCI0>,
 679                                  <&ccu CLK_BUS_EHCI0>,
 680                                  <&ccu CLK_USB_OHCI0>;
 681                         resets = <&ccu RST_BUS_OHCI0>,
 682                                  <&ccu RST_BUS_EHCI0>;
 683                         status = "disabled";
 684                 };
 685
 686                 ohci0: usb@5101400 {
 687                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 688                         reg = <0x05101400 0x100>;
 689                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 690                         clocks = <&ccu CLK_BUS_OHCI0>,
 691                                  <&ccu CLK_USB_OHCI0>;
 692                         resets = <&ccu RST_BUS_OHCI0>;
 693                         status = "disabled";
 694                 };
 695
 696                 dwc3: usb@5200000 {
 697                         compatible = "snps,dwc3";
 698                         reg = <0x05200000 0x10000>;
 699                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 700                         clocks = <&ccu CLK_BUS_XHCI>,
 701                                  <&ccu CLK_BUS_XHCI>,
 702                                  <&rtc 0>;
 703                         clock-names = "ref", "bus_early", "suspend";
 704                         resets = <&ccu RST_BUS_XHCI>;
 705                         /*
 706                          * The datasheet of the chip doesn't declare the
 707                          * peripheral function, and there's no boards known
 708                          * to have a USB Type-B port routed to the port.
 709                          * In addition, no one has tested the peripheral
 710                          * function yet.
 711                          * So set the dr_mode to "host" in the DTSI file.
 712                          */
 713                         dr_mode = "host";
 714                         phys = <&usb3phy>;
 715                         phy-names = "usb3-phy";
 716                         status = "disabled";
 717                 };
 718
 719                 usb3phy: phy@5210000 {
 720                         compatible = "allwinner,sun50i-h6-usb3-phy";
 721                         reg = <0x5210000 0x10000>;
 722                         clocks = <&ccu CLK_USB_PHY1>;
 723                         resets = <&ccu RST_USB_PHY1>;
 724                         #phy-cells = <0>;
 725                         status = "disabled";
 726                 };
 727
 728                 ehci3: usb@5311000 {
 729                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 730                         reg = <0x05311000 0x100>;
 731                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 732                         clocks = <&ccu CLK_BUS_OHCI3>,
 733                                  <&ccu CLK_BUS_EHCI3>,
 734                                  <&ccu CLK_USB_OHCI3>;
 735                         resets = <&ccu RST_BUS_OHCI3>,
 736                                  <&ccu RST_BUS_EHCI3>;
 737                         phys = <&usb2phy 3>;
 738                         phy-names = "usb";
 739                         status = "disabled";
 740                 };
 741
 742                 ohci3: usb@5311400 {
 743                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 744                         reg = <0x05311400 0x100>;
 745                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 746                         clocks = <&ccu CLK_BUS_OHCI3>,
 747                                  <&ccu CLK_USB_OHCI3>;
 748                         resets = <&ccu RST_BUS_OHCI3>;
 749                         phys = <&usb2phy 3>;
 750                         phy-names = "usb";
 751                         status = "disabled";
 752                 };
 753
 754                 hdmi: hdmi@6000000 {
 755                         compatible = "allwinner,sun50i-h6-dw-hdmi";
 756                         reg = <0x06000000 0x10000>;
 757                         reg-io-width = <1>;
 758                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 759                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
 760                                  <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
 761                                  <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
 762                         clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
 763                                       "hdcp-bus";
 764                         resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
 765                         reset-names = "ctrl", "hdcp";
 766                         phys = <&hdmi_phy>;
 767                         phy-names = "phy";
 768                         pinctrl-names = "default";
 769                         pinctrl-0 = <&hdmi_pins>;
 770                         status = "disabled";
 771
 772                         ports {
 773                                 #address-cells = <1>;
 774                                 #size-cells = <0>;
 775
 776                                 hdmi_in: port@0 {
 777                                         reg = <0>;
 778
 779                                         hdmi_in_tcon_top: endpoint {
 780                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
 781                                         };
 782                                 };
 783
 784                                 hdmi_out: port@1 {
 785                                         reg = <1>;
 786                                 };
 787                         };
 788                 };
 789
 790                 hdmi_phy: hdmi-phy@6010000 {
 791                         compatible = "allwinner,sun50i-h6-hdmi-phy";
 792                         reg = <0x06010000 0x10000>;
 793                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
 794                         clock-names = "bus", "mod";
 795                         resets = <&ccu RST_BUS_HDMI>;
 796                         reset-names = "phy";
 797                         #phy-cells = <0>;
 798                 };
 799
 800                 tcon_top: tcon-top@6510000 {
 801                         compatible = "allwinner,sun50i-h6-tcon-top";
 802                         reg = <0x06510000 0x1000>;
 803                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 804                                  <&ccu CLK_TCON_TV0>;
 805                         clock-names = "bus",
 806                                       "tcon-tv0";
 807                         clock-output-names = "tcon-top-tv0";
 808                         resets = <&ccu RST_BUS_TCON_TOP>;
 809                         #clock-cells = <1>;
 810
 811                         ports {
 812                                 #address-cells = <1>;
 813                                 #size-cells = <0>;
 814
 815                                 tcon_top_mixer0_in: port@0 {
 816                                         #address-cells = <1>;
 817                                         #size-cells = <0>;
 818                                         reg = <0>;
 819
 820                                         tcon_top_mixer0_in_mixer0: endpoint@0 {
 821                                                 reg = <0>;
 822                                                 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
 823                                         };
 824                                 };
 825
 826                                 tcon_top_mixer0_out: port@1 {
 827                                         #address-cells = <1>;
 828                                         #size-cells = <0>;
 829                                         reg = <1>;
 830
 831                                         tcon_top_mixer0_out_tcon_tv: endpoint@2 {
 832                                                 reg = <2>;
 833                                                 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
 834                                         };
 835                                 };
 836
 837                                 tcon_top_hdmi_in: port@4 {
 838                                         #address-cells = <1>;
 839                                         #size-cells = <0>;
 840                                         reg = <4>;
 841
 842                                         tcon_top_hdmi_in_tcon_tv: endpoint@0 {
 843                                                 reg = <0>;
 844                                                 remote-endpoint = <&tcon_tv_out_tcon_top>;
 845                                         };
 846                                 };
 847
 848                                 tcon_top_hdmi_out: port@5 {
 849                                         reg = <5>;
 850
 851                                         tcon_top_hdmi_out_hdmi: endpoint {
 852                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 853                                         };
 854                                 };
 855                         };
 856                 };
 857
 858                 tcon_tv: lcd-controller@6515000 {
 859                         compatible = "allwinner,sun50i-h6-tcon-tv",
 860                                      "allwinner,sun8i-r40-tcon-tv";
 861                         reg = <0x06515000 0x1000>;
 862                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 863                         clocks = <&ccu CLK_BUS_TCON_TV0>,
 864                                  <&tcon_top CLK_TCON_TOP_TV0>;
 865                         clock-names = "ahb",
 866                                       "tcon-ch1";
 867                         resets = <&ccu RST_BUS_TCON_TV0>;
 868                         reset-names = "lcd";
 869
 870                         ports {
 871                                 #address-cells = <1>;
 872                                 #size-cells = <0>;
 873
 874                                 tcon_tv_in: port@0 {
 875                                         reg = <0>;
 876
 877                                         tcon_tv_in_tcon_top_mixer0: endpoint {
 878                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
 879                                         };
 880                                 };
 881
 882                                 tcon_tv_out: port@1 {
 883                                         #address-cells = <1>;
 884                                         #size-cells = <0>;
 885                                         reg = <1>;
 886
 887                                         tcon_tv_out_tcon_top: endpoint@1 {
 888                                                 reg = <1>;
 889                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
 890                                         };
 891                                 };
 892                         };
 893                 };
 894
 895                 rtc: rtc@7000000 {
 896                         compatible = "allwinner,sun50i-h6-rtc";
 897                         reg = <0x07000000 0x400>;
 898                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 899                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 900                         clock-output-names = "osc32k", "osc32k-out", "iosc";
 901                         #clock-cells = <1>;
 902                 };
 903
 904                 r_ccu: clock@7010000 {
 905                         compatible = "allwinner,sun50i-h6-r-ccu";
 906                         reg = <0x07010000 0x400>;
 907                         clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
 908                                  <&ccu CLK_PLL_PERIPH0>;
 909                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 910                         #clock-cells = <1>;
 911                         #reset-cells = <1>;
 912                 };
 913
 914                 r_watchdog: watchdog@7020400 {
 915                         compatible = "allwinner,sun50i-h6-wdt",
 916                                      "allwinner,sun6i-a31-wdt";
 917                         reg = <0x07020400 0x20>;
 918                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 919                         clocks = <&osc24M>;
 920                 };
 921
 922                 r_intc: interrupt-controller@7021000 {
 923                         compatible = "allwinner,sun50i-h6-r-intc",
 924                                      "allwinner,sun6i-a31-r-intc";
 925                         interrupt-controller;
 926                         #interrupt-cells = <2>;
 927                         reg = <0x07021000 0x400>;
 928                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 929                 };
 930
 931                 r_pio: pinctrl@7022000 {
 932                         compatible = "allwinner,sun50i-h6-r-pinctrl";
 933                         reg = <0x07022000 0x400>;
 934                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 935                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 936                         clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
 937                         clock-names = "apb", "hosc", "losc";
 938                         gpio-controller;
 939                         #gpio-cells = <3>;
 940                         interrupt-controller;
 941                         #interrupt-cells = <3>;
 942
 943                         r_i2c_pins: r-i2c-pins {
 944                                 pins = "PL0", "PL1";
 945                                 function = "s_i2c";
 946                         };
 947
 948                         r_ir_rx_pin: r-ir-rx-pin {
 949                                 pins = "PL9";
 950                                 function = "s_cir_rx";
 951                         };
 952                 };
 953
 954                 r_ir: ir@7040000 {
 955                                 compatible = "allwinner,sun50i-h6-ir",
 956                                              "allwinner,sun6i-a31-ir";
 957                                 reg = <0x07040000 0x400>;
 958                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 959                                 clocks = <&r_ccu CLK_R_APB1_IR>,
 960                                          <&r_ccu CLK_IR>;
 961                                 clock-names = "apb", "ir";
 962                                 resets = <&r_ccu RST_R_APB1_IR>;
 963                                 pinctrl-names = "default";
 964                                 pinctrl-0 = <&r_ir_rx_pin>;
 965                                 status = "disabled";
 966                 };
 967
 968                 r_i2c: i2c@7081400 {
 969                         compatible = "allwinner,sun50i-h6-i2c",
 970                                      "allwinner,sun6i-a31-i2c";
 971                         reg = <0x07081400 0x400>;
 972                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 973                         clocks = <&r_ccu CLK_R_APB2_I2C>;
 974                         resets = <&r_ccu RST_R_APB2_I2C>;
 975                         pinctrl-names = "default";
 976                         pinctrl-0 = <&r_i2c_pins>;
 977                         status = "disabled";
 978                         #address-cells = <1>;
 979                         #size-cells = <0>;
 980                 };
 981
 982                 ths: thermal-sensor@5070400 {
 983                         compatible = "allwinner,sun50i-h6-ths";
 984                         reg = <0x05070400 0x100>;
 985                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 986                         clocks = <&ccu CLK_BUS_THS>;
 987                         clock-names = "bus";
 988                         resets = <&ccu RST_BUS_THS>;
 989                         nvmem-cells = <&ths_calibration>;
 990                         nvmem-cell-names = "calibration";
 991                         #thermal-sensor-cells = <1>;
 992                 };
 993         };
 994
 995         thermal-zones {
 996                 cpu-thermal {
 997                         polling-delay-passive = <0>;
 998                         polling-delay = <0>;
 999                         thermal-sensors = <&ths 0>;
1000
1001                         trips {
1002                                 cpu_alert: cpu-alert {
1003                                         temperature = <85000>;
1004                                         hysteresis = <2000>;
1005                                         type = "passive";
1006                                 };
1007
1008                                 cpu-crit {
1009                                         temperature = <100000>;
1010                                         hysteresis = <0>;
1011                                         type = "critical";
1012                                 };
1013                         };
1014
1015                         cooling-maps {
1016                                 map0 {
1017                                         trip = <&cpu_alert>;
1018                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1019                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1020                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1021                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1022                                 };
1023                         };
1024                 };
1025
1026                 gpu-thermal {
1027                         polling-delay-passive = <0>;
1028                         polling-delay = <0>;
1029                         thermal-sensors = <&ths 1>;
1030                 };
1031         };
1032 };