arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
   6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
   7 #include <dt-bindings/clock/sun8i-de2.h>
   8 #include <dt-bindings/clock/sun8i-tcon-top.h>
   9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
  10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
  11 #include <dt-bindings/reset/sun8i-de2.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         interrupt-parent = <&gic>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu0: cpu@0 {
  24                         compatible = "arm,cortex-a53";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         enable-method = "psci";
  28                         clocks = <&ccu CLK_CPUX>;
  29                         clock-latency-ns = <244144>; /* 8 32k periods */
  30                         #cooling-cells = <2>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         compatible = "arm,cortex-a53";
  35                         device_type = "cpu";
  36                         reg = <1>;
  37                         enable-method = "psci";
  38                         clocks = <&ccu CLK_CPUX>;
  39                         clock-latency-ns = <244144>; /* 8 32k periods */
  40                         #cooling-cells = <2>;
  41                 };
  42
  43                 cpu2: cpu@2 {
  44                         compatible = "arm,cortex-a53";
  45                         device_type = "cpu";
  46                         reg = <2>;
  47                         enable-method = "psci";
  48                         clocks = <&ccu CLK_CPUX>;
  49                         clock-latency-ns = <244144>; /* 8 32k periods */
  50                         #cooling-cells = <2>;
  51                 };
  52
  53                 cpu3: cpu@3 {
  54                         compatible = "arm,cortex-a53";
  55                         device_type = "cpu";
  56                         reg = <3>;
  57                         enable-method = "psci";
  58                         clocks = <&ccu CLK_CPUX>;
  59                         clock-latency-ns = <244144>; /* 8 32k periods */
  60                         #cooling-cells = <2>;
  61                 };
  62         };
  63
  64         de: display-engine {
  65                 compatible = "allwinner,sun50i-h6-display-engine";
  66                 allwinner,pipelines = <&mixer0>;
  67                 status = "disabled";
  68         };
  69
  70         osc24M: osc24M_clk {
  71                 #clock-cells = <0>;
  72                 compatible = "fixed-clock";
  73                 clock-frequency = <24000000>;
  74                 clock-output-names = "osc24M";
  75         };
  76
  77         pmu {
  78                 compatible = "arm,cortex-a53-pmu";
  79                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         psci {
  87                 compatible = "arm,psci-0.2";
  88                 method = "smc";
  89         };
  90
  91         timer {
  92                 compatible = "arm,armv8-timer";
  93                 arm,no-tick-in-suspend;
  94                 interrupts = <GIC_PPI 13
  95                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  96                              <GIC_PPI 14
  97                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  98                              <GIC_PPI 11
  99                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 100                              <GIC_PPI 10
 101                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 102         };
 103
 104         soc {
 105                 compatible = "simple-bus";
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 bus@1000000 {
 111                         compatible = "allwinner,sun50i-h6-de3",
 112                                      "allwinner,sun50i-a64-de2";
 113                         reg = <0x1000000 0x400000>;
 114                         allwinner,sram = <&de2_sram 1>;
 115                         #address-cells = <1>;
 116                         #size-cells = <1>;
 117                         ranges = <0 0x1000000 0x400000>;
 118
 119                         display_clocks: clock@0 {
 120                                 compatible = "allwinner,sun50i-h6-de3-clk";
 121                                 reg = <0x0 0x10000>;
 122                                 clocks = <&ccu CLK_DE>,
 123                                          <&ccu CLK_BUS_DE>;
 124                                 clock-names = "mod",
 125                                               "bus";
 126                                 resets = <&ccu RST_BUS_DE>;
 127                                 #clock-cells = <1>;
 128                                 #reset-cells = <1>;
 129                         };
 130
 131                         mixer0: mixer@100000 {
 132                                 compatible = "allwinner,sun50i-h6-de3-mixer-0";
 133                                 reg = <0x100000 0x100000>;
 134                                 clocks = <&display_clocks CLK_BUS_MIXER0>,
 135                                          <&display_clocks CLK_MIXER0>;
 136                                 clock-names = "bus",
 137                                               "mod";
 138                                 resets = <&display_clocks RST_MIXER0>;
 139                                 iommus = <&iommu 0>;
 140
 141                                 ports {
 142                                         #address-cells = <1>;
 143                                         #size-cells = <0>;
 144
 145                                         mixer0_out: port@1 {
 146                                                 reg = <1>;
 147
 148                                                 mixer0_out_tcon_top_mixer0: endpoint {
 149                                                         remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 150                                                 };
 151                                         };
 152                                 };
 153                         };
 154                 };
 155
 156                 video-codec@1c0e000 {
 157                         compatible = "allwinner,sun50i-h6-video-engine";
 158                         reg = <0x01c0e000 0x2000>;
 159                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 160                                  <&ccu CLK_MBUS_VE>;
 161                         clock-names = "ahb", "mod", "ram";
 162                         resets = <&ccu RST_BUS_VE>;
 163                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 164                         allwinner,sram = <&ve_sram 1>;
 165                         iommus = <&iommu 3>;
 166                 };
 167
 168                 gpu: gpu@1800000 {
 169                         compatible = "allwinner,sun50i-h6-mali",
 170                                      "arm,mali-t720";
 171                         reg = <0x01800000 0x4000>;
 172                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 173                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 174                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 175                         interrupt-names = "job", "mmu", "gpu";
 176                         clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
 177                         clock-names = "core", "bus";
 178                         resets = <&ccu RST_BUS_GPU>;
 179                         status = "disabled";
 180                 };
 181
 182                 crypto: crypto@1904000 {
 183                         compatible = "allwinner,sun50i-h6-crypto";
 184                         reg = <0x01904000 0x1000>;
 185                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 186                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
 187                         clock-names = "bus", "mod", "ram";
 188                         resets = <&ccu RST_BUS_CE>;
 189                 };
 190
 191                 syscon: syscon@3000000 {
 192                         compatible = "allwinner,sun50i-h6-system-control",
 193                                      "allwinner,sun50i-a64-system-control";
 194                         reg = <0x03000000 0x1000>;
 195                         #address-cells = <1>;
 196                         #size-cells = <1>;
 197                         ranges;
 198
 199                         sram_c: sram@28000 {
 200                                 compatible = "mmio-sram";
 201                                 reg = <0x00028000 0x1e000>;
 202                                 #address-cells = <1>;
 203                                 #size-cells = <1>;
 204                                 ranges = <0 0x00028000 0x1e000>;
 205
 206                                 de2_sram: sram-section@0 {
 207                                         compatible = "allwinner,sun50i-h6-sram-c",
 208                                                      "allwinner,sun50i-a64-sram-c";
 209                                         reg = <0x0000 0x1e000>;
 210                                 };
 211                         };
 212
 213                         sram_c1: sram@1a00000 {
 214                                 compatible = "mmio-sram";
 215                                 reg = <0x01a00000 0x200000>;
 216                                 #address-cells = <1>;
 217                                 #size-cells = <1>;
 218                                 ranges = <0 0x01a00000 0x200000>;
 219
 220                                 ve_sram: sram-section@0 {
 221                                         compatible = "allwinner,sun50i-h6-sram-c1",
 222                                                      "allwinner,sun4i-a10-sram-c1";
 223                                         reg = <0x000000 0x200000>;
 224                                 };
 225                         };
 226                 };
 227
 228                 ccu: clock@3001000 {
 229                         compatible = "allwinner,sun50i-h6-ccu";
 230                         reg = <0x03001000 0x1000>;
 231                         clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
 232                         clock-names = "hosc", "losc", "iosc";
 233                         #clock-cells = <1>;
 234                         #reset-cells = <1>;
 235                 };
 236
 237                 dma: dma-controller@3002000 {
 238                         compatible = "allwinner,sun50i-h6-dma";
 239                         reg = <0x03002000 0x1000>;
 240                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
 242                         clock-names = "bus", "mbus";
 243                         dma-channels = <16>;
 244                         dma-requests = <46>;
 245                         resets = <&ccu RST_BUS_DMA>;
 246                         #dma-cells = <1>;
 247                 };
 248
 249                 msgbox: mailbox@3003000 {
 250                         compatible = "allwinner,sun50i-h6-msgbox",
 251                                      "allwinner,sun6i-a31-msgbox";
 252                         reg = <0x03003000 0x1000>;
 253                         clocks = <&ccu CLK_BUS_MSGBOX>;
 254                         resets = <&ccu RST_BUS_MSGBOX>;
 255                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 256                         #mbox-cells = <1>;
 257                 };
 258
 259                 sid: efuse@3006000 {
 260                         compatible = "allwinner,sun50i-h6-sid";
 261                         reg = <0x03006000 0x400>;
 262                         #address-cells = <1>;
 263                         #size-cells = <1>;
 264
 265                         ths_calibration: thermal-sensor-calibration@14 {
 266                                 reg = <0x14 0x8>;
 267                         };
 268
 269                         cpu_speed_grade: cpu-speed-grade@1c {
 270                                 reg = <0x1c 0x4>;
 271                         };
 272                 };
 273
 274                 timer@3009000 {
 275                         compatible = "allwinner,sun50i-h6-timer",
 276                                      "allwinner,sun8i-a23-timer";
 277                         reg = <0x03009000 0xa0>;
 278                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 279                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&osc24M>;
 281                 };
 282
 283                 watchdog: watchdog@30090a0 {
 284                         compatible = "allwinner,sun50i-h6-wdt",
 285                                      "allwinner,sun6i-a31-wdt";
 286                         reg = <0x030090a0 0x20>;
 287                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&osc24M>;
 289                         /* Broken on some H6 boards */
 290                         status = "disabled";
 291                 };
 292
 293                 pwm: pwm@300a000 {
 294                         compatible = "allwinner,sun50i-h6-pwm";
 295                         reg = <0x0300a000 0x400>;
 296                         clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
 297                         clock-names = "mod", "bus";
 298                         resets = <&ccu RST_BUS_PWM>;
 299                         #pwm-cells = <3>;
 300                         status = "disabled";
 301                 };
 302
 303                 pio: pinctrl@300b000 {
 304                         compatible = "allwinner,sun50i-h6-pinctrl";
 305                         reg = <0x0300b000 0x400>;
 306                         interrupt-parent = <&r_intc>;
 307                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 308                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 309                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 310                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 311                         clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
 312                         clock-names = "apb", "hosc", "losc";
 313                         gpio-controller;
 314                         #gpio-cells = <3>;
 315                         interrupt-controller;
 316                         #interrupt-cells = <3>;
 317
 318                         ext_rgmii_pins: rgmii-pins {
 319                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 320                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 321                                        "PD11", "PD12", "PD13", "PD19", "PD20";
 322                                 function = "emac";
 323                                 drive-strength = <40>;
 324                         };
 325
 326                         hdmi_pins: hdmi-pins {
 327                                 pins = "PH8", "PH9", "PH10";
 328                                 function = "hdmi";
 329                         };
 330
 331                         i2c0_pins: i2c0-pins {
 332                                 pins = "PD25", "PD26";
 333                                 function = "i2c0";
 334                         };
 335
 336                         i2c1_pins: i2c1-pins {
 337                                 pins = "PH5", "PH6";
 338                                 function = "i2c1";
 339                         };
 340
 341                         i2c2_pins: i2c2-pins {
 342                                 pins = "PD23", "PD24";
 343                                 function = "i2c2";
 344                         };
 345
 346                         mmc0_pins: mmc0-pins {
 347                                 pins = "PF0", "PF1", "PF2", "PF3",
 348                                        "PF4", "PF5";
 349                                 function = "mmc0";
 350                                 drive-strength = <30>;
 351                                 bias-pull-up;
 352                         };
 353
 354                         /omit-if-no-ref/
 355                         mmc1_pins: mmc1-pins {
 356                                 pins = "PG0", "PG1", "PG2", "PG3",
 357                                        "PG4", "PG5";
 358                                 function = "mmc1";
 359                                 drive-strength = <30>;
 360                                 bias-pull-up;
 361                         };
 362
 363                         mmc2_pins: mmc2-pins {
 364                                 pins = "PC1", "PC4", "PC5", "PC6",
 365                                        "PC7", "PC8", "PC9", "PC10",
 366                                        "PC11", "PC12", "PC13", "PC14";
 367                                 function = "mmc2";
 368                                 drive-strength = <30>;
 369                                 bias-pull-up;
 370                         };
 371
 372                         /omit-if-no-ref/
 373                         spi0_pins: spi0-pins {
 374                                 pins = "PC0", "PC2", "PC3";
 375                                 function = "spi0";
 376                         };
 377
 378                         /* pin shared with MMC2-CMD (eMMC) */
 379                         /omit-if-no-ref/
 380                         spi0_cs_pin: spi0-cs-pin {
 381                                 pins = "PC5";
 382                                 function = "spi0";
 383                         };
 384
 385                         /omit-if-no-ref/
 386                         spi1_pins: spi1-pins {
 387                                 pins = "PH4", "PH5", "PH6";
 388                                 function = "spi1";
 389                         };
 390
 391                         /omit-if-no-ref/
 392                         spi1_cs_pin: spi1-cs-pin {
 393                                 pins = "PH3";
 394                                 function = "spi1";
 395                         };
 396
 397                         spdif_tx_pin: spdif-tx-pin {
 398                                 pins = "PH7";
 399                                 function = "spdif";
 400                         };
 401
 402                         uart0_ph_pins: uart0-ph-pins {
 403                                 pins = "PH0", "PH1";
 404                                 function = "uart0";
 405                         };
 406
 407                         uart1_pins: uart1-pins {
 408                                 pins = "PG6", "PG7";
 409                                 function = "uart1";
 410                         };
 411
 412                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 413                                 pins = "PG8", "PG9";
 414                                 function = "uart1";
 415                         };
 416                 };
 417
 418                 gic: interrupt-controller@3021000 {
 419                         compatible = "arm,gic-400";
 420                         reg = <0x03021000 0x1000>,
 421                               <0x03022000 0x2000>,
 422                               <0x03024000 0x2000>,
 423                               <0x03026000 0x2000>;
 424                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 425                         interrupt-controller;
 426                         #interrupt-cells = <3>;
 427                 };
 428
 429                 iommu: iommu@30f0000 {
 430                         compatible = "allwinner,sun50i-h6-iommu";
 431                         reg = <0x030f0000 0x10000>;
 432                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 433                         clocks = <&ccu CLK_BUS_IOMMU>;
 434                         resets = <&ccu RST_BUS_IOMMU>;
 435                         #iommu-cells = <1>;
 436                 };
 437
 438                 mmc0: mmc@4020000 {
 439                         compatible = "allwinner,sun50i-h6-mmc",
 440                                      "allwinner,sun50i-a64-mmc";
 441                         reg = <0x04020000 0x1000>;
 442                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 443                         clock-names = "ahb", "mmc";
 444                         resets = <&ccu RST_BUS_MMC0>;
 445                         reset-names = "ahb";
 446                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 447                         pinctrl-names = "default";
 448                         pinctrl-0 = <&mmc0_pins>;
 449                         max-frequency = <150000000>;
 450                         status = "disabled";
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                 };
 454
 455                 mmc1: mmc@4021000 {
 456                         compatible = "allwinner,sun50i-h6-mmc",
 457                                      "allwinner,sun50i-a64-mmc";
 458                         reg = <0x04021000 0x1000>;
 459                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 460                         clock-names = "ahb", "mmc";
 461                         resets = <&ccu RST_BUS_MMC1>;
 462                         reset-names = "ahb";
 463                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 464                         pinctrl-names = "default";
 465                         pinctrl-0 = <&mmc1_pins>;
 466                         max-frequency = <150000000>;
 467                         status = "disabled";
 468                         #address-cells = <1>;
 469                         #size-cells = <0>;
 470                 };
 471
 472                 mmc2: mmc@4022000 {
 473                         compatible = "allwinner,sun50i-h6-emmc",
 474                                      "allwinner,sun50i-a64-emmc";
 475                         reg = <0x04022000 0x1000>;
 476                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 477                         clock-names = "ahb", "mmc";
 478                         resets = <&ccu RST_BUS_MMC2>;
 479                         reset-names = "ahb";
 480                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 481                         pinctrl-names = "default";
 482                         pinctrl-0 = <&mmc2_pins>;
 483                         max-frequency = <150000000>;
 484                         status = "disabled";
 485                         #address-cells = <1>;
 486                         #size-cells = <0>;
 487                 };
 488
 489                 uart0: serial@5000000 {
 490                         compatible = "snps,dw-apb-uart";
 491                         reg = <0x05000000 0x400>;
 492                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 493                         reg-shift = <2>;
 494                         reg-io-width = <4>;
 495                         clocks = <&ccu CLK_BUS_UART0>;
 496                         resets = <&ccu RST_BUS_UART0>;
 497                         status = "disabled";
 498                 };
 499
 500                 uart1: serial@5000400 {
 501                         compatible = "snps,dw-apb-uart";
 502                         reg = <0x05000400 0x400>;
 503                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 504                         reg-shift = <2>;
 505                         reg-io-width = <4>;
 506                         clocks = <&ccu CLK_BUS_UART1>;
 507                         resets = <&ccu RST_BUS_UART1>;
 508                         status = "disabled";
 509                 };
 510
 511                 uart2: serial@5000800 {
 512                         compatible = "snps,dw-apb-uart";
 513                         reg = <0x05000800 0x400>;
 514                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 515                         reg-shift = <2>;
 516                         reg-io-width = <4>;
 517                         clocks = <&ccu CLK_BUS_UART2>;
 518                         resets = <&ccu RST_BUS_UART2>;
 519                         status = "disabled";
 520                 };
 521
 522                 uart3: serial@5000c00 {
 523                         compatible = "snps,dw-apb-uart";
 524                         reg = <0x05000c00 0x400>;
 525                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 526                         reg-shift = <2>;
 527                         reg-io-width = <4>;
 528                         clocks = <&ccu CLK_BUS_UART3>;
 529                         resets = <&ccu RST_BUS_UART3>;
 530                         status = "disabled";
 531                 };
 532
 533                 i2c0: i2c@5002000 {
 534                         compatible = "allwinner,sun50i-h6-i2c",
 535                                      "allwinner,sun6i-a31-i2c";
 536                         reg = <0x05002000 0x400>;
 537                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 538                         clocks = <&ccu CLK_BUS_I2C0>;
 539                         resets = <&ccu RST_BUS_I2C0>;
 540                         pinctrl-names = "default";
 541                         pinctrl-0 = <&i2c0_pins>;
 542                         status = "disabled";
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                 };
 546
 547                 i2c1: i2c@5002400 {
 548                         compatible = "allwinner,sun50i-h6-i2c",
 549                                      "allwinner,sun6i-a31-i2c";
 550                         reg = <0x05002400 0x400>;
 551                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 552                         clocks = <&ccu CLK_BUS_I2C1>;
 553                         resets = <&ccu RST_BUS_I2C1>;
 554                         pinctrl-names = "default";
 555                         pinctrl-0 = <&i2c1_pins>;
 556                         status = "disabled";
 557                         #address-cells = <1>;
 558                         #size-cells = <0>;
 559                 };
 560
 561                 i2c2: i2c@5002800 {
 562                         compatible = "allwinner,sun50i-h6-i2c",
 563                                      "allwinner,sun6i-a31-i2c";
 564                         reg = <0x05002800 0x400>;
 565                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 566                         clocks = <&ccu CLK_BUS_I2C2>;
 567                         resets = <&ccu RST_BUS_I2C2>;
 568                         pinctrl-names = "default";
 569                         pinctrl-0 = <&i2c2_pins>;
 570                         status = "disabled";
 571                         #address-cells = <1>;
 572                         #size-cells = <0>;
 573                 };
 574
 575                 spi0: spi@5010000 {
 576                         compatible = "allwinner,sun50i-h6-spi",
 577                                      "allwinner,sun8i-h3-spi";
 578                         reg = <0x05010000 0x1000>;
 579                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 580                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 581                         clock-names = "ahb", "mod";
 582                         dmas = <&dma 22>, <&dma 22>;
 583                         dma-names = "rx", "tx";
 584                         resets = <&ccu RST_BUS_SPI0>;
 585                         status = "disabled";
 586                         #address-cells = <1>;
 587                         #size-cells = <0>;
 588                 };
 589
 590                 spi1: spi@5011000 {
 591                         compatible = "allwinner,sun50i-h6-spi",
 592                                      "allwinner,sun8i-h3-spi";
 593                         reg = <0x05011000 0x1000>;
 594                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 595                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 596                         clock-names = "ahb", "mod";
 597                         dmas = <&dma 23>, <&dma 23>;
 598                         dma-names = "rx", "tx";
 599                         resets = <&ccu RST_BUS_SPI1>;
 600                         status = "disabled";
 601                         #address-cells = <1>;
 602                         #size-cells = <0>;
 603                 };
 604
 605                 emac: ethernet@5020000 {
 606                         compatible = "allwinner,sun50i-h6-emac",
 607                                      "allwinner,sun50i-a64-emac";
 608                         syscon = <&syscon>;
 609                         reg = <0x05020000 0x10000>;
 610                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 611                         interrupt-names = "macirq";
 612                         resets = <&ccu RST_BUS_EMAC>;
 613                         reset-names = "stmmaceth";
 614                         clocks = <&ccu CLK_BUS_EMAC>;
 615                         clock-names = "stmmaceth";
 616                         status = "disabled";
 617
 618                         mdio: mdio {
 619                                 compatible = "snps,dwmac-mdio";
 620                                 #address-cells = <1>;
 621                                 #size-cells = <0>;
 622                         };
 623                 };
 624
 625                 i2s1: i2s@5091000 {
 626                         #sound-dai-cells = <0>;
 627                         compatible = "allwinner,sun50i-h6-i2s";
 628                         reg = <0x05091000 0x1000>;
 629                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 630                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 631                         clock-names = "apb", "mod";
 632                         dmas = <&dma 4>, <&dma 4>;
 633                         resets = <&ccu RST_BUS_I2S1>;
 634                         dma-names = "rx", "tx";
 635                         status = "disabled";
 636                 };
 637
 638                 spdif: spdif@5093000 {
 639                         #sound-dai-cells = <0>;
 640                         compatible = "allwinner,sun50i-h6-spdif";
 641                         reg = <0x05093000 0x400>;
 642                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 643                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 644                         clock-names = "apb", "spdif";
 645                         resets = <&ccu RST_BUS_SPDIF>;
 646                         dmas = <&dma 2>;
 647                         dma-names = "tx";
 648                         pinctrl-names = "default";
 649                         pinctrl-0 = <&spdif_tx_pin>;
 650                         status = "disabled";
 651                 };
 652
 653                 usb2otg: usb@5100000 {
 654                         compatible = "allwinner,sun50i-h6-musb",
 655                                      "allwinner,sun8i-a33-musb";
 656                         reg = <0x05100000 0x0400>;
 657                         clocks = <&ccu CLK_BUS_OTG>;
 658                         resets = <&ccu RST_BUS_OTG>;
 659                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 660                         interrupt-names = "mc";
 661                         phys = <&usb2phy 0>;
 662                         phy-names = "usb";
 663                         extcon = <&usb2phy 0>;
 664                         status = "disabled";
 665                 };
 666
 667                 usb2phy: phy@5100400 {
 668                         compatible = "allwinner,sun50i-h6-usb-phy";
 669                         reg = <0x05100400 0x24>,
 670                               <0x05101800 0x4>,
 671                               <0x05311800 0x4>;
 672                         reg-names = "phy_ctrl",
 673                                     "pmu0",
 674                                     "pmu3";
 675                         clocks = <&ccu CLK_USB_PHY0>,
 676                                  <&ccu CLK_USB_PHY3>;
 677                         clock-names = "usb0_phy",
 678                                       "usb3_phy";
 679                         resets = <&ccu RST_USB_PHY0>,
 680                                  <&ccu RST_USB_PHY3>;
 681                         reset-names = "usb0_reset",
 682                                       "usb3_reset";
 683                         status = "disabled";
 684                         #phy-cells = <1>;
 685                 };
 686
 687                 ehci0: usb@5101000 {
 688                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 689                         reg = <0x05101000 0x100>;
 690                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 691                         clocks = <&ccu CLK_BUS_OHCI0>,
 692                                  <&ccu CLK_BUS_EHCI0>,
 693                                  <&ccu CLK_USB_OHCI0>;
 694                         resets = <&ccu RST_BUS_OHCI0>,
 695                                  <&ccu RST_BUS_EHCI0>;
 696                         phys = <&usb2phy 0>;
 697                         phy-names = "usb";
 698                         status = "disabled";
 699                 };
 700
 701                 ohci0: usb@5101400 {
 702                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 703                         reg = <0x05101400 0x100>;
 704                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 705                         clocks = <&ccu CLK_BUS_OHCI0>,
 706                                  <&ccu CLK_USB_OHCI0>;
 707                         resets = <&ccu RST_BUS_OHCI0>;
 708                         phys = <&usb2phy 0>;
 709                         phy-names = "usb";
 710                         status = "disabled";
 711                 };
 712
 713                 dwc3: usb@5200000 {
 714                         compatible = "snps,dwc3";
 715                         reg = <0x05200000 0x10000>;
 716                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 717                         clocks = <&ccu CLK_BUS_XHCI>,
 718                                  <&ccu CLK_BUS_XHCI>,
 719                                  <&rtc 0>;
 720                         clock-names = "ref", "bus_early", "suspend";
 721                         resets = <&ccu RST_BUS_XHCI>;
 722                         /*
 723                          * The datasheet of the chip doesn't declare the
 724                          * peripheral function, and there's no boards known
 725                          * to have a USB Type-B port routed to the port.
 726                          * In addition, no one has tested the peripheral
 727                          * function yet.
 728                          * So set the dr_mode to "host" in the DTSI file.
 729                          */
 730                         dr_mode = "host";
 731                         phys = <&usb3phy>;
 732                         phy-names = "usb3-phy";
 733                         status = "disabled";
 734                 };
 735
 736                 usb3phy: phy@5210000 {
 737                         compatible = "allwinner,sun50i-h6-usb3-phy";
 738                         reg = <0x5210000 0x10000>;
 739                         clocks = <&ccu CLK_USB_PHY1>;
 740                         resets = <&ccu RST_USB_PHY1>;
 741                         #phy-cells = <0>;
 742                         status = "disabled";
 743                 };
 744
 745                 ehci3: usb@5311000 {
 746                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 747                         reg = <0x05311000 0x100>;
 748                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 749                         clocks = <&ccu CLK_BUS_OHCI3>,
 750                                  <&ccu CLK_BUS_EHCI3>,
 751                                  <&ccu CLK_USB_OHCI3>;
 752                         resets = <&ccu RST_BUS_OHCI3>,
 753                                  <&ccu RST_BUS_EHCI3>;
 754                         phys = <&usb2phy 3>;
 755                         phy-names = "usb";
 756                         status = "disabled";
 757                 };
 758
 759                 ohci3: usb@5311400 {
 760                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 761                         reg = <0x05311400 0x100>;
 762                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 763                         clocks = <&ccu CLK_BUS_OHCI3>,
 764                                  <&ccu CLK_USB_OHCI3>;
 765                         resets = <&ccu RST_BUS_OHCI3>;
 766                         phys = <&usb2phy 3>;
 767                         phy-names = "usb";
 768                         status = "disabled";
 769                 };
 770
 771                 hdmi: hdmi@6000000 {
 772                         compatible = "allwinner,sun50i-h6-dw-hdmi";
 773                         reg = <0x06000000 0x10000>;
 774                         reg-io-width = <1>;
 775                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 776                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
 777                                  <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
 778                                  <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
 779                         clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
 780                                       "hdcp-bus";
 781                         resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
 782                         reset-names = "ctrl", "hdcp";
 783                         phys = <&hdmi_phy>;
 784                         phy-names = "phy";
 785                         pinctrl-names = "default";
 786                         pinctrl-0 = <&hdmi_pins>;
 787                         status = "disabled";
 788
 789                         ports {
 790                                 #address-cells = <1>;
 791                                 #size-cells = <0>;
 792
 793                                 hdmi_in: port@0 {
 794                                         reg = <0>;
 795
 796                                         hdmi_in_tcon_top: endpoint {
 797                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
 798                                         };
 799                                 };
 800
 801                                 hdmi_out: port@1 {
 802                                         reg = <1>;
 803                                 };
 804                         };
 805                 };
 806
 807                 hdmi_phy: hdmi-phy@6010000 {
 808                         compatible = "allwinner,sun50i-h6-hdmi-phy";
 809                         reg = <0x06010000 0x10000>;
 810                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
 811                         clock-names = "bus", "mod";
 812                         resets = <&ccu RST_BUS_HDMI>;
 813                         reset-names = "phy";
 814                         #phy-cells = <0>;
 815                 };
 816
 817                 tcon_top: tcon-top@6510000 {
 818                         compatible = "allwinner,sun50i-h6-tcon-top";
 819                         reg = <0x06510000 0x1000>;
 820                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 821                                  <&ccu CLK_TCON_TV0>;
 822                         clock-names = "bus",
 823                                       "tcon-tv0";
 824                         clock-output-names = "tcon-top-tv0";
 825                         resets = <&ccu RST_BUS_TCON_TOP>;
 826                         #clock-cells = <1>;
 827
 828                         ports {
 829                                 #address-cells = <1>;
 830                                 #size-cells = <0>;
 831
 832                                 tcon_top_mixer0_in: port@0 {
 833                                         #address-cells = <1>;
 834                                         #size-cells = <0>;
 835                                         reg = <0>;
 836
 837                                         tcon_top_mixer0_in_mixer0: endpoint@0 {
 838                                                 reg = <0>;
 839                                                 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
 840                                         };
 841                                 };
 842
 843                                 tcon_top_mixer0_out: port@1 {
 844                                         #address-cells = <1>;
 845                                         #size-cells = <0>;
 846                                         reg = <1>;
 847
 848                                         tcon_top_mixer0_out_tcon_tv: endpoint@2 {
 849                                                 reg = <2>;
 850                                                 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
 851                                         };
 852                                 };
 853
 854                                 tcon_top_hdmi_in: port@4 {
 855                                         #address-cells = <1>;
 856                                         #size-cells = <0>;
 857                                         reg = <4>;
 858
 859                                         tcon_top_hdmi_in_tcon_tv: endpoint@0 {
 860                                                 reg = <0>;
 861                                                 remote-endpoint = <&tcon_tv_out_tcon_top>;
 862                                         };
 863                                 };
 864
 865                                 tcon_top_hdmi_out: port@5 {
 866                                         reg = <5>;
 867
 868                                         tcon_top_hdmi_out_hdmi: endpoint {
 869                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 870                                         };
 871                                 };
 872                         };
 873                 };
 874
 875                 tcon_tv: lcd-controller@6515000 {
 876                         compatible = "allwinner,sun50i-h6-tcon-tv",
 877                                      "allwinner,sun8i-r40-tcon-tv";
 878                         reg = <0x06515000 0x1000>;
 879                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 880                         clocks = <&ccu CLK_BUS_TCON_TV0>,
 881                                  <&tcon_top CLK_TCON_TOP_TV0>;
 882                         clock-names = "ahb",
 883                                       "tcon-ch1";
 884                         resets = <&ccu RST_BUS_TCON_TV0>;
 885                         reset-names = "lcd";
 886
 887                         ports {
 888                                 #address-cells = <1>;
 889                                 #size-cells = <0>;
 890
 891                                 tcon_tv_in: port@0 {
 892                                         reg = <0>;
 893
 894                                         tcon_tv_in_tcon_top_mixer0: endpoint {
 895                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
 896                                         };
 897                                 };
 898
 899                                 tcon_tv_out: port@1 {
 900                                         #address-cells = <1>;
 901                                         #size-cells = <0>;
 902                                         reg = <1>;
 903
 904                                         tcon_tv_out_tcon_top: endpoint@1 {
 905                                                 reg = <1>;
 906                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
 907                                         };
 908                                 };
 909                         };
 910                 };
 911
 912                 rtc: rtc@7000000 {
 913                         compatible = "allwinner,sun50i-h6-rtc";
 914                         reg = <0x07000000 0x400>;
 915                         interrupt-parent = <&r_intc>;
 916                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 917                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 918                         clock-output-names = "osc32k", "osc32k-out", "iosc";
 919                         #clock-cells = <1>;
 920                 };
 921
 922                 r_ccu: clock@7010000 {
 923                         compatible = "allwinner,sun50i-h6-r-ccu";
 924                         reg = <0x07010000 0x400>;
 925                         clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
 926                                  <&ccu CLK_PLL_PERIPH0>;
 927                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 928                         #clock-cells = <1>;
 929                         #reset-cells = <1>;
 930                 };
 931
 932                 r_watchdog: watchdog@7020400 {
 933                         compatible = "allwinner,sun50i-h6-wdt",
 934                                      "allwinner,sun6i-a31-wdt";
 935                         reg = <0x07020400 0x20>;
 936                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 937                         clocks = <&osc24M>;
 938                 };
 939
 940                 r_intc: interrupt-controller@7021000 {
 941                         compatible = "allwinner,sun50i-h6-r-intc";
 942                         interrupt-controller;
 943                         #interrupt-cells = <3>;
 944                         reg = <0x07021000 0x400>;
 945                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 946                 };
 947
 948                 r_pio: pinctrl@7022000 {
 949                         compatible = "allwinner,sun50i-h6-r-pinctrl";
 950                         reg = <0x07022000 0x400>;
 951                         interrupt-parent = <&r_intc>;
 952                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 953                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 954                         clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
 955                         clock-names = "apb", "hosc", "losc";
 956                         gpio-controller;
 957                         #gpio-cells = <3>;
 958                         interrupt-controller;
 959                         #interrupt-cells = <3>;
 960
 961                         r_i2c_pins: r-i2c-pins {
 962                                 pins = "PL0", "PL1";
 963                                 function = "s_i2c";
 964                         };
 965
 966                         r_ir_rx_pin: r-ir-rx-pin {
 967                                 pins = "PL9";
 968                                 function = "s_cir_rx";
 969                         };
 970
 971                         r_rsb_pins: r-rsb-pins {
 972                                 pins = "PL0", "PL1";
 973                                 function = "s_rsb";
 974                         };
 975                 };
 976
 977                 r_ir: ir@7040000 {
 978                                 compatible = "allwinner,sun50i-h6-ir",
 979                                              "allwinner,sun6i-a31-ir";
 980                                 reg = <0x07040000 0x400>;
 981                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 982                                 clocks = <&r_ccu CLK_R_APB1_IR>,
 983                                          <&r_ccu CLK_IR>;
 984                                 clock-names = "apb", "ir";
 985                                 resets = <&r_ccu RST_R_APB1_IR>;
 986                                 pinctrl-names = "default";
 987                                 pinctrl-0 = <&r_ir_rx_pin>;
 988                                 status = "disabled";
 989                 };
 990
 991                 r_i2c: i2c@7081400 {
 992                         compatible = "allwinner,sun50i-h6-i2c",
 993                                      "allwinner,sun6i-a31-i2c";
 994                         reg = <0x07081400 0x400>;
 995                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 996                         clocks = <&r_ccu CLK_R_APB2_I2C>;
 997                         resets = <&r_ccu RST_R_APB2_I2C>;
 998                         pinctrl-names = "default";
 999                         pinctrl-0 = <&r_i2c_pins>;
1000                         status = "disabled";
1001                         #address-cells = <1>;
1002                         #size-cells = <0>;
1003                 };
1004
1005                 r_rsb: rsb@7083000 {
1006                         compatible = "allwinner,sun8i-a23-rsb";
1007                         reg = <0x07083000 0x400>;
1008                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1009                         clocks = <&r_ccu CLK_R_APB2_RSB>;
1010                         clock-frequency = <3000000>;
1011                         resets = <&r_ccu RST_R_APB2_RSB>;
1012                         pinctrl-names = "default";
1013                         pinctrl-0 = <&r_rsb_pins>;
1014                         status = "disabled";
1015                         #address-cells = <1>;
1016                         #size-cells = <0>;
1017                 };
1018
1019                 ths: thermal-sensor@5070400 {
1020                         compatible = "allwinner,sun50i-h6-ths";
1021                         reg = <0x05070400 0x100>;
1022                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1023                         clocks = <&ccu CLK_BUS_THS>;
1024                         clock-names = "bus";
1025                         resets = <&ccu RST_BUS_THS>;
1026                         nvmem-cells = <&ths_calibration>;
1027                         nvmem-cell-names = "calibration";
1028                         #thermal-sensor-cells = <1>;
1029                 };
1030         };
1031
1032         thermal-zones {
1033                 cpu-thermal {
1034                         polling-delay-passive = <0>;
1035                         polling-delay = <0>;
1036                         thermal-sensors = <&ths 0>;
1037
1038                         trips {
1039                                 cpu_alert: cpu-alert {
1040                                         temperature = <85000>;
1041                                         hysteresis = <2000>;
1042                                         type = "passive";
1043                                 };
1044
1045                                 cpu-crit {
1046                                         temperature = <100000>;
1047                                         hysteresis = <0>;
1048                                         type = "critical";
1049                                 };
1050                         };
1051
1052                         cooling-maps {
1053                                 map0 {
1054                                         trip = <&cpu_alert>;
1055                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1056                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1057                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1058                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1059                                 };
1060                         };
1061                 };
1062
1063                 gpu-thermal {
1064                         polling-delay-passive = <0>;
1065                         polling-delay = <0>;
1066                         thermal-sensors = <&ths 1>;
1067                 };
1068         };
1069 };