arch/arm/mach-s3c/mach-rx3715.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (c) 2003-2004 Simtec Electronics
   4 //      Ben Dooks <ben@simtec.co.uk>
   5 //
   6 // https://www.handhelds.org/projects/rx3715.html
   7
   8 #include <linux/kernel.h>
   9 #include <linux/types.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/list.h>
  12 #include <linux/memblock.h>
  13 #include <linux/timer.h>
  14 #include <linux/init.h>
  15 #include <linux/tty.h>
  16 #include <linux/console.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/serial_s3c.h>
  21 #include <linux/serial.h>
  22 #include <linux/io.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/rawnand.h>
  25 #include <linux/mtd/nand-ecc-sw-hamming.h>
  26 #include <linux/mtd/partitions.h>
  27
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/irq.h>
  30 #include <asm/mach/map.h>
  31
  32 #include <linux/platform_data/mtd-nand-s3c2410.h>
  33 #include <linux/platform_data/fb-s3c2410.h>
  34
  35 #include <asm/irq.h>
  36 #include <asm/mach-types.h>
  37
  38 #include "regs-gpio.h"
  39 #include "gpio-samsung.h"
  40 #include "gpio-cfg.h"
  41
  42 #include "cpu.h"
  43 #include "devs.h"
  44 #include "pm.h"
  45
  46 #include "s3c24xx.h"
  47 #include "h1940.h"
  48
  49 static struct map_desc rx3715_iodesc[] __initdata = {
  50         /* dump ISA space somewhere unused */
  51
  52         {
  53                 .virtual        = (u32)S3C24XX_VA_ISA_WORD,
  54                 .pfn            = __phys_to_pfn(S3C2410_CS3),
  55                 .length         = SZ_1M,
  56                 .type           = MT_DEVICE,
  57         }, {
  58                 .virtual        = (u32)S3C24XX_VA_ISA_BYTE,
  59                 .pfn            = __phys_to_pfn(S3C2410_CS3),
  60                 .length         = SZ_1M,
  61                 .type           = MT_DEVICE,
  62         },
  63 };
  64
  65 static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
  66         [0] = {
  67                 .hwport      = 0,
  68                 .flags       = 0,
  69                 .ucon        = 0x3c5,
  70                 .ulcon       = 0x03,
  71                 .ufcon       = 0x51,
  72                 .clk_sel        = S3C2410_UCON_CLKSEL3,
  73         },
  74         [1] = {
  75                 .hwport      = 1,
  76                 .flags       = 0,
  77                 .ucon        = 0x3c5,
  78                 .ulcon       = 0x03,
  79                 .ufcon       = 0x00,
  80                 .clk_sel        = S3C2410_UCON_CLKSEL3,
  81         },
  82         /* IR port */
  83         [2] = {
  84                 .hwport      = 2,
  85                 .uart_flags  = UPF_CONS_FLOW,
  86                 .ucon        = 0x3c5,
  87                 .ulcon       = 0x43,
  88                 .ufcon       = 0x51,
  89                 .clk_sel        = S3C2410_UCON_CLKSEL3,
  90         }
  91 };
  92
  93 /* framebuffer lcd controller information */
  94
  95 static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
  96         .lcdcon5 =      S3C2410_LCDCON5_INVVLINE |
  97                         S3C2410_LCDCON5_FRM565 |
  98                         S3C2410_LCDCON5_HWSWP,
  99
 100         .type           = S3C2410_LCDCON1_TFT,
 101         .width          = 240,
 102         .height         = 320,
 103
 104         .pixclock       = 260000,
 105         .xres           = 240,
 106         .yres           = 320,
 107         .bpp            = 16,
 108         .left_margin    = 36,
 109         .right_margin   = 36,
 110         .hsync_len      = 8,
 111         .upper_margin   = 6,
 112         .lower_margin   = 7,
 113         .vsync_len      = 3,
 114 };
 115
 116 static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
 117
 118         .displays =     &rx3715_lcdcfg,
 119         .num_displays = 1,
 120         .default_display = 0,
 121
 122         .lpcsel =       0xf82,
 123
 124         .gpccon =       0xaa955699,
 125         .gpccon_mask =  0xffc003cc,
 126         .gpccon_reg =   S3C2410_GPCCON,
 127         .gpcup =        0x0000ffff,
 128         .gpcup_mask =   0xffffffff,
 129         .gpcup_reg =    S3C2410_GPCUP,
 130
 131         .gpdcon =       0xaa95aaa1,
 132         .gpdcon_mask =  0xffc0fff0,
 133         .gpdcon_reg =   S3C2410_GPDCON,
 134         .gpdup =        0x0000faff,
 135         .gpdup_mask =   0xffffffff,
 136         .gpdup_reg =    S3C2410_GPDUP,
 137 };
 138
 139 static struct mtd_partition __initdata rx3715_nand_part[] = {
 140         [0] = {
 141                 .name           = "Whole Flash",
 142                 .offset         = 0,
 143                 .size           = MTDPART_SIZ_FULL,
 144                 .mask_flags     = MTD_WRITEABLE,
 145         }
 146 };
 147
 148 static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
 149         [0] = {
 150                 .name           = "Internal",
 151                 .nr_chips       = 1,
 152                 .nr_partitions  = ARRAY_SIZE(rx3715_nand_part),
 153                 .partitions     = rx3715_nand_part,
 154         },
 155 };
 156
 157 static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
 158         .tacls          = 25,
 159         .twrph0         = 50,
 160         .twrph1         = 15,
 161         .nr_sets        = ARRAY_SIZE(rx3715_nand_sets),
 162         .sets           = rx3715_nand_sets,
 163         .engine_type    = NAND_ECC_ENGINE_TYPE_SOFT,
 164 };
 165
 166 static struct platform_device *rx3715_devices[] __initdata = {
 167         &s3c_device_ohci,
 168         &s3c_device_lcd,
 169         &s3c_device_wdt,
 170         &s3c_device_i2c0,
 171         &s3c_device_iis,
 172         &s3c_device_nand,
 173 };
 174
 175 static void __init rx3715_map_io(void)
 176 {
 177         s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
 178         s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
 179         s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
 180 }
 181
 182 static void __init rx3715_init_time(void)
 183 {
 184         s3c2440_init_clocks(16934000);
 185         s3c24xx_timer_init();
 186 }
 187
 188 /* H1940 and RX3715 need to reserve this for suspend */
 189 static void __init rx3715_reserve(void)
 190 {
 191         memblock_reserve(0x30003000, 0x1000);
 192         memblock_reserve(0x30081000, 0x1000);
 193 }
 194
 195 static void __init rx3715_init_machine(void)
 196 {
 197 #ifdef CONFIG_PM_H1940
 198         memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
 199 #endif
 200         s3c_pm_init();
 201
 202         s3c_nand_set_platdata(&rx3715_nand_info);
 203         s3c24xx_fb_set_platdata(&rx3715_fb_info);
 204         /* Configure the I2S pins (GPE0...GPE4) in correct mode */
 205         s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
 206                               S3C_GPIO_PULL_NONE);
 207         platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
 208 }
 209
 210 MACHINE_START(RX3715, "IPAQ-RX3715")
 211         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
 212         .atag_offset    = 0x100,
 213         .map_io         = rx3715_map_io,
 214         .reserve        = rx3715_reserve,
 215         .init_irq       = s3c2440_init_irq,
 216         .init_machine   = rx3715_init_machine,
 217         .init_time      = rx3715_init_time,
 218 MACHINE_END