arch/arm/boot/dts/vexpress-v2m-rs1.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ARM Ltd. Versatile Express
   4  *
   5  * Motherboard Express uATX
   6  * V2M-P1
   7  *
   8  * HBI-0190D
   9  *
  10  * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
  11  * Technical Reference Manual)
  12  *
  13  * WARNING! The hardware described in this file is independent from the
  14  * original variant (vexpress-v2m.dtsi), but there is a strong
  15  * correspondence between the two configurations.
  16  *
  17  * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
  18  * CHANGES TO vexpress-v2m.dtsi!
  19  */
  20
  21 / {
  22         v2m_fixed_3v3: fixed-regulator-0 {
  23                 compatible = "regulator-fixed";
  24                 regulator-name = "3V3";
  25                 regulator-min-microvolt = <3300000>;
  26                 regulator-max-microvolt = <3300000>;
  27                 regulator-always-on;
  28         };
  29
  30         v2m_clk24mhz: clk24mhz {
  31                 compatible = "fixed-clock";
  32                 #clock-cells = <0>;
  33                 clock-frequency = <24000000>;
  34                 clock-output-names = "v2m:clk24mhz";
  35         };
  36
  37         v2m_refclk1mhz: refclk1mhz {
  38                 compatible = "fixed-clock";
  39                 #clock-cells = <0>;
  40                 clock-frequency = <1000000>;
  41                 clock-output-names = "v2m:refclk1mhz";
  42         };
  43
  44         v2m_refclk32khz: refclk32khz {
  45                 compatible = "fixed-clock";
  46                 #clock-cells = <0>;
  47                 clock-frequency = <32768>;
  48                 clock-output-names = "v2m:refclk32khz";
  49         };
  50
  51         leds {
  52                 compatible = "gpio-leds";
  53
  54                 led-1 {
  55                         label = "v2m:green:user1";
  56                         gpios = <&v2m_led_gpios 0 0>;
  57                         linux,default-trigger = "heartbeat";
  58                 };
  59
  60                 led-2 {
  61                         label = "v2m:green:user2";
  62                         gpios = <&v2m_led_gpios 1 0>;
  63                         linux,default-trigger = "disk-activity";
  64                 };
  65
  66                 led-3 {
  67                         label = "v2m:green:user3";
  68                         gpios = <&v2m_led_gpios 2 0>;
  69                         linux,default-trigger = "cpu0";
  70                 };
  71
  72                 led-4 {
  73                         label = "v2m:green:user4";
  74                         gpios = <&v2m_led_gpios 3 0>;
  75                         linux,default-trigger = "cpu1";
  76                 };
  77
  78                 led-5 {
  79                         label = "v2m:green:user5";
  80                         gpios = <&v2m_led_gpios 4 0>;
  81                         linux,default-trigger = "cpu2";
  82                 };
  83
  84                 led-6 {
  85                         label = "v2m:green:user6";
  86                         gpios = <&v2m_led_gpios 5 0>;
  87                         linux,default-trigger = "cpu3";
  88                 };
  89
  90                 led-7 {
  91                         label = "v2m:green:user7";
  92                         gpios = <&v2m_led_gpios 6 0>;
  93                         linux,default-trigger = "cpu4";
  94                 };
  95
  96                 led-8 {
  97                         label = "v2m:green:user8";
  98                         gpios = <&v2m_led_gpios 7 0>;
  99                         linux,default-trigger = "cpu5";
 100                 };
 101         };
 102
 103         bus@8000000 {
 104                 motherboard-bus {
 105                         model = "V2M-P1";
 106                         arm,hbi = <0x190>;
 107                         arm,vexpress,site = <0>;
 108                         arm,v2m-memory-map = "rs1";
 109                         compatible = "arm,vexpress,v2m-p1", "simple-bus";
 110                         #address-cells = <2>; /* SMB chipselect number and offset */
 111                         #size-cells = <1>;
 112                         #interrupt-cells = <1>;
 113                         ranges;
 114
 115                         nor_flash: flash@0 {
 116                                 compatible = "arm,vexpress-flash", "cfi-flash";
 117                                 reg = <0 0x00000000 0x04000000>,
 118                                       <4 0x00000000 0x04000000>;
 119                                 bank-width = <4>;
 120                                 partitions {
 121                                         compatible = "arm,arm-firmware-suite";
 122                                 };
 123                         };
 124
 125                         psram@100000000 {
 126                                 compatible = "arm,vexpress-psram", "mtd-ram";
 127                                 reg = <1 0x00000000 0x02000000>;
 128                                 bank-width = <4>;
 129                         };
 130
 131                         ethernet@202000000 {
 132                                 compatible = "smsc,lan9118", "smsc,lan9115";
 133                                 reg = <2 0x02000000 0x10000>;
 134                                 interrupts = <15>;
 135                                 phy-mode = "mii";
 136                                 reg-io-width = <4>;
 137                                 smsc,irq-active-high;
 138                                 smsc,irq-push-pull;
 139                                 vdd33a-supply = <&v2m_fixed_3v3>;
 140                                 vddvario-supply = <&v2m_fixed_3v3>;
 141                         };
 142
 143                         usb@203000000 {
 144                                 compatible = "nxp,usb-isp1761";
 145                                 reg = <2 0x03000000 0x20000>;
 146                                 interrupts = <16>;
 147                                 dr_mode = "peripheral";
 148                         };
 149
 150                         iofpga-bus@300000000 {
 151                                 compatible = "simple-bus";
 152                                 #address-cells = <1>;
 153                                 #size-cells = <1>;
 154                                 ranges = <0 3 0 0x200000>;
 155
 156                                 v2m_sysreg: sysreg@10000 {
 157                                         compatible = "arm,vexpress-sysreg";
 158                                         reg = <0x010000 0x1000>;
 159                                         #address-cells = <1>;
 160                                         #size-cells = <1>;
 161                                         ranges = <0 0x10000 0x1000>;
 162
 163                                         v2m_led_gpios: gpio@8 {
 164                                                 compatible = "arm,vexpress-sysreg,sys_led";
 165                                                 reg = <0x008 4>;
 166                                                 gpio-controller;
 167                                                 #gpio-cells = <2>;
 168                                         };
 169
 170                                         v2m_mmc_gpios: gpio@48 {
 171                                                 compatible = "arm,vexpress-sysreg,sys_mci";
 172                                                 reg = <0x048 4>;
 173                                                 gpio-controller;
 174                                                 #gpio-cells = <2>;
 175                                         };
 176
 177                                         v2m_flash_gpios: gpio@4c {
 178                                                 compatible = "arm,vexpress-sysreg,sys_flash";
 179                                                 reg = <0x04c 4>;
 180                                                 gpio-controller;
 181                                                 #gpio-cells = <2>;
 182                                         };
 183                                 };
 184
 185                                 v2m_sysctl: sysctl@20000 {
 186                                         compatible = "arm,sp810", "arm,primecell";
 187                                         reg = <0x020000 0x1000>;
 188                                         clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
 189                                         clock-names = "refclk", "timclk", "apb_pclk";
 190                                         #clock-cells = <1>;
 191                                         clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
 192                                         assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
 193                                         assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
 194                                 };
 195
 196                                 /* PCI-E I2C bus */
 197                                 v2m_i2c_pcie: i2c@30000 {
 198                                         compatible = "arm,versatile-i2c";
 199                                         reg = <0x030000 0x1000>;
 200
 201                                         #address-cells = <1>;
 202                                         #size-cells = <0>;
 203
 204                                         pcie-switch@60 {
 205                                                 compatible = "idt,89hpes32h8";
 206                                                 reg = <0x60>;
 207                                         };
 208                                 };
 209
 210                                 aaci@40000 {
 211                                         compatible = "arm,pl041", "arm,primecell";
 212                                         reg = <0x040000 0x1000>;
 213                                         interrupts = <11>;
 214                                         clocks = <&smbclk>;
 215                                         clock-names = "apb_pclk";
 216                                 };
 217
 218                                 mmci@50000 {
 219                                         compatible = "arm,pl180", "arm,primecell";
 220                                         reg = <0x050000 0x1000>;
 221                                         interrupts = <9>, <10>;
 222                                         cd-gpios = <&v2m_mmc_gpios 0 0>;
 223                                         wp-gpios = <&v2m_mmc_gpios 1 0>;
 224                                         max-frequency = <12000000>;
 225                                         vmmc-supply = <&v2m_fixed_3v3>;
 226                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 227                                         clock-names = "mclk", "apb_pclk";
 228                                 };
 229
 230                                 kmi@60000 {
 231                                         compatible = "arm,pl050", "arm,primecell";
 232                                         reg = <0x060000 0x1000>;
 233                                         interrupts = <12>;
 234                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 235                                         clock-names = "KMIREFCLK", "apb_pclk";
 236                                 };
 237
 238                                 kmi@70000 {
 239                                         compatible = "arm,pl050", "arm,primecell";
 240                                         reg = <0x070000 0x1000>;
 241                                         interrupts = <13>;
 242                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 243                                         clock-names = "KMIREFCLK", "apb_pclk";
 244                                 };
 245
 246                                 v2m_serial0: serial@90000 {
 247                                         compatible = "arm,pl011", "arm,primecell";
 248                                         reg = <0x090000 0x1000>;
 249                                         interrupts = <5>;
 250                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 251                                         clock-names = "uartclk", "apb_pclk";
 252                                 };
 253
 254                                 v2m_serial1: serial@a0000 {
 255                                         compatible = "arm,pl011", "arm,primecell";
 256                                         reg = <0x0a0000 0x1000>;
 257                                         interrupts = <6>;
 258                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 259                                         clock-names = "uartclk", "apb_pclk";
 260                                 };
 261
 262                                 v2m_serial2: serial@b0000 {
 263                                         compatible = "arm,pl011", "arm,primecell";
 264                                         reg = <0x0b0000 0x1000>;
 265                                         interrupts = <7>;
 266                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 267                                         clock-names = "uartclk", "apb_pclk";
 268                                 };
 269
 270                                 v2m_serial3: serial@c0000 {
 271                                         compatible = "arm,pl011", "arm,primecell";
 272                                         reg = <0x0c0000 0x1000>;
 273                                         interrupts = <8>;
 274                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 275                                         clock-names = "uartclk", "apb_pclk";
 276                                 };
 277
 278                                 wdt@f0000 {
 279                                         compatible = "arm,sp805", "arm,primecell";
 280                                         reg = <0x0f0000 0x1000>;
 281                                         interrupts = <0>;
 282                                         clocks = <&v2m_refclk32khz>, <&smbclk>;
 283                                         clock-names = "wdog_clk", "apb_pclk";
 284                                 };
 285
 286                                 v2m_timer01: timer@110000 {
 287                                         compatible = "arm,sp804", "arm,primecell";
 288                                         reg = <0x110000 0x1000>;
 289                                         interrupts = <2>;
 290                                         clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
 291                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 292                                 };
 293
 294                                 v2m_timer23: timer@120000 {
 295                                         compatible = "arm,sp804", "arm,primecell";
 296                                         reg = <0x120000 0x1000>;
 297                                         interrupts = <3>;
 298                                         clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
 299                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 300                                 };
 301
 302                                 /* DVI I2C bus */
 303                                 v2m_i2c_dvi: i2c@160000 {
 304                                         compatible = "arm,versatile-i2c";
 305                                         reg = <0x160000 0x1000>;
 306                                         #address-cells = <1>;
 307                                         #size-cells = <0>;
 308
 309                                         dvi-transmitter@39 {
 310                                                 compatible = "sil,sii9022-tpi", "sil,sii9022";
 311                                                 reg = <0x39>;
 312
 313                                                 ports {
 314                                                         #address-cells = <1>;
 315                                                         #size-cells = <0>;
 316
 317                                                         port@0 {
 318                                                                 reg = <0>;
 319                                                                 dvi_bridge_in: endpoint {
 320                                                                         remote-endpoint = <&clcd_pads>;
 321                                                                 };
 322                                                         };
 323                                                 };
 324                                         };
 325
 326                                         dvi-transmitter@60 {
 327                                                 compatible = "sil,sii9022-cpi", "sil,sii9022";
 328                                                 reg = <0x60>;
 329                                         };
 330                                 };
 331
 332                                 rtc@170000 {
 333                                         compatible = "arm,pl031", "arm,primecell";
 334                                         reg = <0x170000 0x1000>;
 335                                         interrupts = <4>;
 336                                         clocks = <&smbclk>;
 337                                         clock-names = "apb_pclk";
 338                                 };
 339
 340                                 compact-flash@1a0000 {
 341                                         compatible = "arm,vexpress-cf", "ata-generic";
 342                                         reg = <0x1a0000 0x100
 343                                                0x1a0100 0xf00>;
 344                                         reg-shift = <2>;
 345                                 };
 346
 347                                 clcd@1f0000 {
 348                                         compatible = "arm,pl111", "arm,primecell";
 349                                         reg = <0x1f0000 0x1000>;
 350                                         interrupt-names = "combined";
 351                                         interrupts = <14>;
 352                                         clocks = <&v2m_oscclk1>, <&smbclk>;
 353                                         clock-names = "clcdclk", "apb_pclk";
 354                                         /* 800x600 16bpp @36MHz works fine */
 355                                         max-memory-bandwidth = <54000000>;
 356                                         memory-region = <&vram>;
 357
 358                                         port {
 359                                                 clcd_pads: endpoint {
 360                                                         remote-endpoint = <&dvi_bridge_in>;
 361                                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 362                                                 };
 363                                         };
 364                                 };
 365
 366                                 mcc {
 367                                         compatible = "arm,vexpress,config-bus";
 368                                         arm,vexpress,config-bridge = <&v2m_sysreg>;
 369
 370                                         oscclk0 {
 371                                                 /* MCC static memory clock */
 372                                                 compatible = "arm,vexpress-osc";
 373                                                 arm,vexpress-sysreg,func = <1 0>;
 374                                                 freq-range = <25000000 60000000>;
 375                                                 #clock-cells = <0>;
 376                                                 clock-output-names = "v2m:oscclk0";
 377                                         };
 378
 379                                         v2m_oscclk1: oscclk1 {
 380                                                 /* CLCD clock */
 381                                                 compatible = "arm,vexpress-osc";
 382                                                 arm,vexpress-sysreg,func = <1 1>;
 383                                                 freq-range = <23750000 65000000>;
 384                                                 #clock-cells = <0>;
 385                                                 clock-output-names = "v2m:oscclk1";
 386                                         };
 387
 388                                         v2m_oscclk2: oscclk2 {
 389                                                 /* IO FPGA peripheral clock */
 390                                                 compatible = "arm,vexpress-osc";
 391                                                 arm,vexpress-sysreg,func = <1 2>;
 392                                                 freq-range = <24000000 24000000>;
 393                                                 #clock-cells = <0>;
 394                                                 clock-output-names = "v2m:oscclk2";
 395                                         };
 396
 397                                         volt-vio {
 398                                                 /* Logic level voltage */
 399                                                 compatible = "arm,vexpress-volt";
 400                                                 arm,vexpress-sysreg,func = <2 0>;
 401                                                 regulator-name = "VIO";
 402                                                 regulator-always-on;
 403                                                 label = "VIO";
 404                                         };
 405
 406                                         temp-mcc {
 407                                                 /* MCC internal operating temperature */
 408                                                 compatible = "arm,vexpress-temp";
 409                                                 arm,vexpress-sysreg,func = <4 0>;
 410                                                 label = "MCC";
 411                                         };
 412
 413                                         reset {
 414                                                 compatible = "arm,vexpress-reset";
 415                                                 arm,vexpress-sysreg,func = <5 0>;
 416                                         };
 417
 418                                         muxfpga {
 419                                                 compatible = "arm,vexpress-muxfpga";
 420                                                 arm,vexpress-sysreg,func = <7 0>;
 421                                         };
 422
 423                                         shutdown {
 424                                                 compatible = "arm,vexpress-shutdown";
 425                                                 arm,vexpress-sysreg,func = <8 0>;
 426                                         };
 427
 428                                         reboot {
 429                                                 compatible = "arm,vexpress-reboot";
 430                                                 arm,vexpress-sysreg,func = <9 0>;
 431                                         };
 432
 433                                         dvimode {
 434                                                 compatible = "arm,vexpress-dvimode";
 435                                                 arm,vexpress-sysreg,func = <11 0>;
 436                                         };
 437                                 };
 438                         };
 439                 };
 440         };
 441 };