arch/arm/boot/dts/tegra30.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra30-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra30-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/soc/tegra-pmc.h>
   8 #include <dt-bindings/thermal/thermal.h>
   9
  10 #include "tegra30-peripherals-opp.dtsi"
  11
  12 / {
  13         compatible = "nvidia,tegra30";
  14         interrupt-parent = <&lic>;
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         memory@80000000 {
  19                 device_type = "memory";
  20                 reg = <0x80000000 0x0>;
  21         };
  22
  23         pcie@3000 {
  24                 compatible = "nvidia,tegra30-pcie";
  25                 device_type = "pci";
  26                 reg = <0x00003000 0x00000800>, /* PADS registers */
  27                       <0x00003800 0x00000200>, /* AFI registers */
  28                       <0x10000000 0x10000000>; /* configuration space */
  29                 reg-names = "pads", "afi", "cs";
  30                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  31                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  32                 interrupt-names = "intr", "msi";
  33
  34                 #interrupt-cells = <1>;
  35                 interrupt-map-mask = <0 0 0 0>;
  36                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  37
  38                 bus-range = <0x00 0xff>;
  39                 #address-cells = <3>;
  40                 #size-cells = <2>;
  41
  42                 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
  43                          <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
  44                          <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
  45                          <0x01000000 0 0          0x02000000 0 0x00010000>, /* downstream I/O */
  46                          <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
  47                          <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  48
  49                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  50                          <&tegra_car TEGRA30_CLK_AFI>,
  51                          <&tegra_car TEGRA30_CLK_PLL_E>,
  52                          <&tegra_car TEGRA30_CLK_CML0>;
  53                 clock-names = "pex", "afi", "pll_e", "cml";
  54                 resets = <&tegra_car 70>,
  55                          <&tegra_car 72>,
  56                          <&tegra_car 74>;
  57                 reset-names = "pex", "afi", "pcie_x";
  58                 status = "disabled";
  59
  60                 pci@1,0 {
  61                         device_type = "pci";
  62                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  63                         reg = <0x000800 0 0 0 0>;
  64                         bus-range = <0x00 0xff>;
  65                         status = "disabled";
  66
  67                         #address-cells = <3>;
  68                         #size-cells = <2>;
  69                         ranges;
  70
  71                         nvidia,num-lanes = <2>;
  72                 };
  73
  74                 pci@2,0 {
  75                         device_type = "pci";
  76                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  77                         reg = <0x001000 0 0 0 0>;
  78                         bus-range = <0x00 0xff>;
  79                         status = "disabled";
  80
  81                         #address-cells = <3>;
  82                         #size-cells = <2>;
  83                         ranges;
  84
  85                         nvidia,num-lanes = <2>;
  86                 };
  87
  88                 pci@3,0 {
  89                         device_type = "pci";
  90                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  91                         reg = <0x001800 0 0 0 0>;
  92                         bus-range = <0x00 0xff>;
  93                         status = "disabled";
  94
  95                         #address-cells = <3>;
  96                         #size-cells = <2>;
  97                         ranges;
  98
  99                         nvidia,num-lanes = <2>;
 100                 };
 101         };
 102
 103         sram@40000000 {
 104                 compatible = "mmio-sram";
 105                 reg = <0x40000000 0x40000>;
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges = <0 0x40000000 0x40000>;
 109
 110                 vde_pool: sram@400 {
 111                         reg = <0x400 0x3fc00>;
 112                         pool;
 113                 };
 114         };
 115
 116         host1x@50000000 {
 117                 compatible = "nvidia,tegra30-host1x";
 118                 reg = <0x50000000 0x00024000>;
 119                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 120                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 121                 interrupt-names = "syncpt", "host1x";
 122                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
 123                 clock-names = "host1x";
 124                 resets = <&tegra_car 28>;
 125                 reset-names = "host1x";
 126                 iommus = <&mc TEGRA_SWGROUP_HC>;
 127
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130
 131                 ranges = <0x54000000 0x54000000 0x04000000>;
 132
 133                 mpe@54040000 {
 134                         compatible = "nvidia,tegra30-mpe";
 135                         reg = <0x54040000 0x00040000>;
 136                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 137                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 138                         resets = <&tegra_car 60>;
 139                         reset-names = "mpe";
 140
 141                         iommus = <&mc TEGRA_SWGROUP_MPE>;
 142                 };
 143
 144                 vi@54080000 {
 145                         compatible = "nvidia,tegra30-vi";
 146                         reg = <0x54080000 0x00040000>;
 147                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 148                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 149                         resets = <&tegra_car 20>;
 150                         reset-names = "vi";
 151
 152                         iommus = <&mc TEGRA_SWGROUP_VI>;
 153                 };
 154
 155                 epp@540c0000 {
 156                         compatible = "nvidia,tegra30-epp";
 157                         reg = <0x540c0000 0x00040000>;
 158                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 160                         resets = <&tegra_car 19>;
 161                         reset-names = "epp";
 162
 163                         iommus = <&mc TEGRA_SWGROUP_EPP>;
 164                 };
 165
 166                 isp@54100000 {
 167                         compatible = "nvidia,tegra30-isp";
 168                         reg = <0x54100000 0x00040000>;
 169                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 170                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 171                         resets = <&tegra_car 23>;
 172                         reset-names = "isp";
 173
 174                         iommus = <&mc TEGRA_SWGROUP_ISP>;
 175                 };
 176
 177                 gr2d@54140000 {
 178                         compatible = "nvidia,tegra30-gr2d";
 179                         reg = <0x54140000 0x00040000>;
 180                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 181                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 182                         resets = <&tegra_car 21>;
 183                         reset-names = "2d";
 184
 185                         iommus = <&mc TEGRA_SWGROUP_G2>;
 186                 };
 187
 188                 gr3d@54180000 {
 189                         compatible = "nvidia,tegra30-gr3d";
 190                         reg = <0x54180000 0x00040000>;
 191                         clocks = <&tegra_car TEGRA30_CLK_GR3D>,
 192                                  <&tegra_car TEGRA30_CLK_GR3D2>;
 193                         clock-names = "3d", "3d2";
 194                         resets = <&tegra_car 24>,
 195                                  <&tegra_car 98>;
 196                         reset-names = "3d", "3d2";
 197
 198                         iommus = <&mc TEGRA_SWGROUP_NV>,
 199                                  <&mc TEGRA_SWGROUP_NV2>;
 200                 };
 201
 202                 dc@54200000 {
 203                         compatible = "nvidia,tegra30-dc";
 204                         reg = <0x54200000 0x00040000>;
 205                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 206                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 207                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 208                         clock-names = "dc", "parent";
 209                         resets = <&tegra_car 27>;
 210                         reset-names = "dc";
 211
 212                         iommus = <&mc TEGRA_SWGROUP_DC>;
 213
 214                         nvidia,head = <0>;
 215
 216                         interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>,
 217                                         <&mc TEGRA30_MC_DISPLAY0B &emc>,
 218                                         <&mc TEGRA30_MC_DISPLAY1B &emc>,
 219                                         <&mc TEGRA30_MC_DISPLAY0C &emc>,
 220                                         <&mc TEGRA30_MC_DISPLAYHC &emc>;
 221                         interconnect-names = "wina",
 222                                              "winb",
 223                                              "winb-vfilter",
 224                                              "winc",
 225                                              "cursor";
 226
 227                         rgb {
 228                                 status = "disabled";
 229                         };
 230                 };
 231
 232                 dc@54240000 {
 233                         compatible = "nvidia,tegra30-dc";
 234                         reg = <0x54240000 0x00040000>;
 235                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 236                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 237                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 238                         clock-names = "dc", "parent";
 239                         resets = <&tegra_car 26>;
 240                         reset-names = "dc";
 241
 242                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 243
 244                         nvidia,head = <1>;
 245
 246                         interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>,
 247                                         <&mc TEGRA30_MC_DISPLAY0BB &emc>,
 248                                         <&mc TEGRA30_MC_DISPLAY1BB &emc>,
 249                                         <&mc TEGRA30_MC_DISPLAY0CB &emc>,
 250                                         <&mc TEGRA30_MC_DISPLAYHCB &emc>;
 251                         interconnect-names = "wina",
 252                                              "winb",
 253                                              "winb-vfilter",
 254                                              "winc",
 255                                              "cursor";
 256
 257                         rgb {
 258                                 status = "disabled";
 259                         };
 260                 };
 261
 262                 hdmi@54280000 {
 263                         compatible = "nvidia,tegra30-hdmi";
 264                         reg = <0x54280000 0x00040000>;
 265                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 266                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 267                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 268                         clock-names = "hdmi", "parent";
 269                         resets = <&tegra_car 51>;
 270                         reset-names = "hdmi";
 271                         status = "disabled";
 272                 };
 273
 274                 tvo@542c0000 {
 275                         compatible = "nvidia,tegra30-tvo";
 276                         reg = <0x542c0000 0x00040000>;
 277                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 278                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 279                         status = "disabled";
 280                 };
 281
 282                 dsi@54300000 {
 283                         compatible = "nvidia,tegra30-dsi";
 284                         reg = <0x54300000 0x00040000>;
 285                         clocks = <&tegra_car TEGRA30_CLK_DSIA>,
 286                                  <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
 287                         clock-names = "dsi", "parent";
 288                         resets = <&tegra_car 48>;
 289                         reset-names = "dsi";
 290                         status = "disabled";
 291                 };
 292
 293                 dsi@54400000 {
 294                         compatible = "nvidia,tegra30-dsi";
 295                         reg = <0x54400000 0x00040000>;
 296                         clocks = <&tegra_car TEGRA30_CLK_DSIB>,
 297                                  <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
 298                         clock-names = "dsi", "parent";
 299                         resets = <&tegra_car 84>;
 300                         reset-names = "dsi";
 301                         status = "disabled";
 302                 };
 303         };
 304
 305         timer@50040600 {
 306                 compatible = "arm,cortex-a9-twd-timer";
 307                 reg = <0x50040600 0x20>;
 308                 interrupt-parent = <&intc>;
 309                 interrupts = <GIC_PPI 13
 310                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 311                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 312         };
 313
 314         intc: interrupt-controller@50041000 {
 315                 compatible = "arm,cortex-a9-gic";
 316                 reg = <0x50041000 0x1000>,
 317                       <0x50040100 0x0100>;
 318                 interrupt-controller;
 319                 #interrupt-cells = <3>;
 320                 interrupt-parent = <&intc>;
 321         };
 322
 323         cache-controller@50043000 {
 324                 compatible = "arm,pl310-cache";
 325                 reg = <0x50043000 0x1000>;
 326                 arm,data-latency = <6 6 2>;
 327                 arm,tag-latency = <5 5 2>;
 328                 cache-unified;
 329                 cache-level = <2>;
 330         };
 331
 332         lic: interrupt-controller@60004000 {
 333                 compatible = "nvidia,tegra30-ictlr";
 334                 reg = <0x60004000 0x100>,
 335                       <0x60004100 0x50>,
 336                       <0x60004200 0x50>,
 337                       <0x60004300 0x50>,
 338                       <0x60004400 0x50>;
 339                 interrupt-controller;
 340                 #interrupt-cells = <3>;
 341                 interrupt-parent = <&intc>;
 342         };
 343
 344         timer@60005000 {
 345                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 346                 reg = <0x60005000 0x400>;
 347                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 348                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 349                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 350                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 351                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 352                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 354         };
 355
 356         tegra_car: clock@60006000 {
 357                 compatible = "nvidia,tegra30-car";
 358                 reg = <0x60006000 0x1000>;
 359                 #clock-cells = <1>;
 360                 #reset-cells = <1>;
 361         };
 362
 363         flow-controller@60007000 {
 364                 compatible = "nvidia,tegra30-flowctrl";
 365                 reg = <0x60007000 0x1000>;
 366         };
 367
 368         apbdma: dma@6000a000 {
 369                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 370                 reg = <0x6000a000 0x1400>;
 371                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 372                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 373                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 374                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 375                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 376                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 377                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 378                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 379                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 380                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 381                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 382                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 383                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 384                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 385                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 386                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 387                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 388                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 389                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 390                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 391                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 392                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 393                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 394                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 395                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 396                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 397                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 398                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 399                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 400                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 401                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 402                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 403                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 404                 resets = <&tegra_car 34>;
 405                 reset-names = "dma";
 406                 #dma-cells = <1>;
 407         };
 408
 409         ahb: ahb@6000c000 {
 410                 compatible = "nvidia,tegra30-ahb";
 411                 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
 412         };
 413
 414         actmon: actmon@6000c800 {
 415                 compatible = "nvidia,tegra30-actmon";
 416                 reg = <0x6000c800 0x400>;
 417                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 418                 clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
 419                          <&tegra_car TEGRA30_CLK_EMC>;
 420                 clock-names = "actmon", "emc";
 421                 resets = <&tegra_car TEGRA30_CLK_ACTMON>;
 422                 reset-names = "actmon";
 423                 operating-points-v2 = <&emc_bw_dfs_opp_table>;
 424                 interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
 425                 interconnect-names = "cpu-read";
 426                 #cooling-cells = <2>;
 427         };
 428
 429         gpio: gpio@6000d000 {
 430                 compatible = "nvidia,tegra30-gpio";
 431                 reg = <0x6000d000 0x1000>;
 432                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 433                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 434                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 435                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 436                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 437                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 438                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 439                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 440                 #gpio-cells = <2>;
 441                 gpio-controller;
 442                 #interrupt-cells = <2>;
 443                 interrupt-controller;
 444                 /*
 445                 gpio-ranges = <&pinmux 0 0 248>;
 446                 */
 447         };
 448
 449         vde@6001a000 {
 450                 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
 451                 reg = <0x6001a000 0x1000>, /* Syntax Engine */
 452                       <0x6001b000 0x1000>, /* Video Bitstream Engine */
 453                       <0x6001c000  0x100>, /* Macroblock Engine */
 454                       <0x6001c200  0x100>, /* Post-processing Engine */
 455                       <0x6001c400  0x100>, /* Motion Compensation Engine */
 456                       <0x6001c600  0x100>, /* Transform Engine */
 457                       <0x6001c800  0x100>, /* Pixel prediction block */
 458                       <0x6001ca00  0x100>, /* Video DMA */
 459                       <0x6001d800  0x400>; /* Video frame controls */
 460                 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
 461                             "tfe", "ppb", "vdma", "frameid";
 462                 iram = <&vde_pool>; /* IRAM region */
 463                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
 464                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
 465                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
 466                 interrupt-names = "sync-token", "bsev", "sxe";
 467                 clocks = <&tegra_car TEGRA30_CLK_VDE>;
 468                 reset-names = "vde", "mc";
 469                 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
 470                 iommus = <&mc TEGRA_SWGROUP_VDE>;
 471         };
 472
 473         apbmisc@70000800 {
 474                 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
 475                 reg = <0x70000800 0x64>, /* Chip revision */
 476                       <0x70000008 0x04>; /* Strapping options */
 477         };
 478
 479         pinmux: pinmux@70000868 {
 480                 compatible = "nvidia,tegra30-pinmux";
 481                 reg = <0x70000868 0x0d4>, /* Pad control registers */
 482                       <0x70003000 0x3e4>; /* Mux registers */
 483         };
 484
 485         /*
 486          * There are two serial driver i.e. 8250 based simple serial
 487          * driver and APB DMA based serial driver for higher baudrate
 488          * and performace. To enable the 8250 based driver, the compatible
 489          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 490          * the APB DMA based serial driver, the compatible is
 491          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 492          */
 493         uarta: serial@70006000 {
 494                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 495                 reg = <0x70006000 0x40>;
 496                 reg-shift = <2>;
 497                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 498                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 499                 resets = <&tegra_car 6>;
 500                 reset-names = "serial";
 501                 dmas = <&apbdma 8>, <&apbdma 8>;
 502                 dma-names = "rx", "tx";
 503                 status = "disabled";
 504         };
 505
 506         uartb: serial@70006040 {
 507                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 508                 reg = <0x70006040 0x40>;
 509                 reg-shift = <2>;
 510                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 511                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 512                 resets = <&tegra_car 7>;
 513                 reset-names = "serial";
 514                 dmas = <&apbdma 9>, <&apbdma 9>;
 515                 dma-names = "rx", "tx";
 516                 status = "disabled";
 517         };
 518
 519         uartc: serial@70006200 {
 520                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 521                 reg = <0x70006200 0x100>;
 522                 reg-shift = <2>;
 523                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 524                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 525                 resets = <&tegra_car 55>;
 526                 reset-names = "serial";
 527                 dmas = <&apbdma 10>, <&apbdma 10>;
 528                 dma-names = "rx", "tx";
 529                 status = "disabled";
 530         };
 531
 532         uartd: serial@70006300 {
 533                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 534                 reg = <0x70006300 0x100>;
 535                 reg-shift = <2>;
 536                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 537                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 538                 resets = <&tegra_car 65>;
 539                 reset-names = "serial";
 540                 dmas = <&apbdma 19>, <&apbdma 19>;
 541                 dma-names = "rx", "tx";
 542                 status = "disabled";
 543         };
 544
 545         uarte: serial@70006400 {
 546                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 547                 reg = <0x70006400 0x100>;
 548                 reg-shift = <2>;
 549                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 550                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 551                 resets = <&tegra_car 66>;
 552                 reset-names = "serial";
 553                 dmas = <&apbdma 20>, <&apbdma 20>;
 554                 dma-names = "rx", "tx";
 555                 status = "disabled";
 556         };
 557
 558         gmi@70009000 {
 559                 compatible = "nvidia,tegra30-gmi";
 560                 reg = <0x70009000 0x1000>;
 561                 #address-cells = <2>;
 562                 #size-cells = <1>;
 563                 ranges = <0 0 0x48000000 0x7ffffff>;
 564                 clocks = <&tegra_car TEGRA30_CLK_NOR>;
 565                 clock-names = "gmi";
 566                 resets = <&tegra_car 42>;
 567                 reset-names = "gmi";
 568                 status = "disabled";
 569         };
 570
 571         pwm: pwm@7000a000 {
 572                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 573                 reg = <0x7000a000 0x100>;
 574                 #pwm-cells = <2>;
 575                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 576                 resets = <&tegra_car 17>;
 577                 reset-names = "pwm";
 578                 status = "disabled";
 579         };
 580
 581         rtc@7000e000 {
 582                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 583                 reg = <0x7000e000 0x100>;
 584                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 585                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 586         };
 587
 588         i2c@7000c000 {
 589                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 590                 reg = <0x7000c000 0x100>;
 591                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 592                 #address-cells = <1>;
 593                 #size-cells = <0>;
 594                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 595                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 596                 clock-names = "div-clk", "fast-clk";
 597                 resets = <&tegra_car 12>;
 598                 reset-names = "i2c";
 599                 dmas = <&apbdma 21>, <&apbdma 21>;
 600                 dma-names = "rx", "tx";
 601                 status = "disabled";
 602         };
 603
 604         i2c@7000c400 {
 605                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 606                 reg = <0x7000c400 0x100>;
 607                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 608                 #address-cells = <1>;
 609                 #size-cells = <0>;
 610                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 611                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 612                 clock-names = "div-clk", "fast-clk";
 613                 resets = <&tegra_car 54>;
 614                 reset-names = "i2c";
 615                 dmas = <&apbdma 22>, <&apbdma 22>;
 616                 dma-names = "rx", "tx";
 617                 status = "disabled";
 618         };
 619
 620         i2c@7000c500 {
 621                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 622                 reg = <0x7000c500 0x100>;
 623                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 624                 #address-cells = <1>;
 625                 #size-cells = <0>;
 626                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 627                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 628                 clock-names = "div-clk", "fast-clk";
 629                 resets = <&tegra_car 67>;
 630                 reset-names = "i2c";
 631                 dmas = <&apbdma 23>, <&apbdma 23>;
 632                 dma-names = "rx", "tx";
 633                 status = "disabled";
 634         };
 635
 636         i2c@7000c700 {
 637                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 638                 reg = <0x7000c700 0x100>;
 639                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 640                 #address-cells = <1>;
 641                 #size-cells = <0>;
 642                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 643                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 644                 resets = <&tegra_car 103>;
 645                 reset-names = "i2c";
 646                 clock-names = "div-clk", "fast-clk";
 647                 dmas = <&apbdma 26>, <&apbdma 26>;
 648                 dma-names = "rx", "tx";
 649                 status = "disabled";
 650         };
 651
 652         i2c@7000d000 {
 653                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 654                 reg = <0x7000d000 0x100>;
 655                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 656                 #address-cells = <1>;
 657                 #size-cells = <0>;
 658                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 659                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 660                 clock-names = "div-clk", "fast-clk";
 661                 resets = <&tegra_car 47>;
 662                 reset-names = "i2c";
 663                 dmas = <&apbdma 24>, <&apbdma 24>;
 664                 dma-names = "rx", "tx";
 665                 status = "disabled";
 666         };
 667
 668         spi@7000d400 {
 669                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 670                 reg = <0x7000d400 0x200>;
 671                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 672                 #address-cells = <1>;
 673                 #size-cells = <0>;
 674                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 675                 resets = <&tegra_car 41>;
 676                 reset-names = "spi";
 677                 dmas = <&apbdma 15>, <&apbdma 15>;
 678                 dma-names = "rx", "tx";
 679                 status = "disabled";
 680         };
 681
 682         spi@7000d600 {
 683                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 684                 reg = <0x7000d600 0x200>;
 685                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 689                 resets = <&tegra_car 44>;
 690                 reset-names = "spi";
 691                 dmas = <&apbdma 16>, <&apbdma 16>;
 692                 dma-names = "rx", "tx";
 693                 status = "disabled";
 694         };
 695
 696         spi@7000d800 {
 697                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 698                 reg = <0x7000d800 0x200>;
 699                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 700                 #address-cells = <1>;
 701                 #size-cells = <0>;
 702                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 703                 resets = <&tegra_car 46>;
 704                 reset-names = "spi";
 705                 dmas = <&apbdma 17>, <&apbdma 17>;
 706                 dma-names = "rx", "tx";
 707                 status = "disabled";
 708         };
 709
 710         spi@7000da00 {
 711                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 712                 reg = <0x7000da00 0x200>;
 713                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 714                 #address-cells = <1>;
 715                 #size-cells = <0>;
 716                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 717                 resets = <&tegra_car 68>;
 718                 reset-names = "spi";
 719                 dmas = <&apbdma 18>, <&apbdma 18>;
 720                 dma-names = "rx", "tx";
 721                 status = "disabled";
 722         };
 723
 724         spi@7000dc00 {
 725                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 726                 reg = <0x7000dc00 0x200>;
 727                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 728                 #address-cells = <1>;
 729                 #size-cells = <0>;
 730                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 731                 resets = <&tegra_car 104>;
 732                 reset-names = "spi";
 733                 dmas = <&apbdma 27>, <&apbdma 27>;
 734                 dma-names = "rx", "tx";
 735                 status = "disabled";
 736         };
 737
 738         spi@7000de00 {
 739                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 740                 reg = <0x7000de00 0x200>;
 741                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 742                 #address-cells = <1>;
 743                 #size-cells = <0>;
 744                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 745                 resets = <&tegra_car 106>;
 746                 reset-names = "spi";
 747                 dmas = <&apbdma 28>, <&apbdma 28>;
 748                 dma-names = "rx", "tx";
 749                 status = "disabled";
 750         };
 751
 752         kbc@7000e200 {
 753                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 754                 reg = <0x7000e200 0x100>;
 755                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 756                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 757                 resets = <&tegra_car 36>;
 758                 reset-names = "kbc";
 759                 status = "disabled";
 760         };
 761
 762         tegra_pmc: pmc@7000e400 {
 763                 compatible = "nvidia,tegra30-pmc";
 764                 reg = <0x7000e400 0x400>;
 765                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 766                 clock-names = "pclk", "clk32k_in";
 767                 #clock-cells = <1>;
 768         };
 769
 770         mc: memory-controller@7000f000 {
 771                 compatible = "nvidia,tegra30-mc";
 772                 reg = <0x7000f000 0x400>;
 773                 clocks = <&tegra_car TEGRA30_CLK_MC>;
 774                 clock-names = "mc";
 775
 776                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 777
 778                 #iommu-cells = <1>;
 779                 #reset-cells = <1>;
 780                 #interconnect-cells = <1>;
 781         };
 782
 783         emc: memory-controller@7000f400 {
 784                 compatible = "nvidia,tegra30-emc";
 785                 reg = <0x7000f400 0x400>;
 786                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 787                 clocks = <&tegra_car TEGRA30_CLK_EMC>;
 788
 789                 nvidia,memory-controller = <&mc>;
 790                 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
 791
 792                 #interconnect-cells = <0>;
 793         };
 794
 795         fuse@7000f800 {
 796                 compatible = "nvidia,tegra30-efuse";
 797                 reg = <0x7000f800 0x400>;
 798                 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
 799                 clock-names = "fuse";
 800                 resets = <&tegra_car 39>;
 801                 reset-names = "fuse";
 802         };
 803
 804         tsensor: tsensor@70014000 {
 805                 compatible = "nvidia,tegra30-tsensor";
 806                 reg = <0x70014000 0x500>;
 807                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 808                 clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
 809                 resets = <&tegra_car TEGRA30_CLK_TSENSOR>;
 810
 811                 assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
 812                 assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
 813                 assigned-clock-rates = <500000>;
 814
 815                 #thermal-sensor-cells = <1>;
 816         };
 817
 818         hda@70030000 {
 819                 compatible = "nvidia,tegra30-hda";
 820                 reg = <0x70030000 0x10000>;
 821                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 822                 clocks = <&tegra_car TEGRA30_CLK_HDA>,
 823                          <&tegra_car TEGRA30_CLK_HDA2HDMI>,
 824                          <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
 825                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 826                 resets = <&tegra_car 125>, /* hda */
 827                          <&tegra_car 128>, /* hda2hdmi */
 828                          <&tegra_car 111>; /* hda2codec_2x */
 829                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 830                 status = "disabled";
 831         };
 832
 833         ahub@70080000 {
 834                 compatible = "nvidia,tegra30-ahub";
 835                 reg = <0x70080000 0x200>,
 836                       <0x70080200 0x100>;
 837                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 838                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 839                          <&tegra_car TEGRA30_CLK_APBIF>;
 840                 clock-names = "d_audio", "apbif";
 841                 resets = <&tegra_car 106>, /* d_audio */
 842                          <&tegra_car 107>, /* apbif */
 843                          <&tegra_car 30>,  /* i2s0 */
 844                          <&tegra_car 11>,  /* i2s1 */
 845                          <&tegra_car 18>,  /* i2s2 */
 846                          <&tegra_car 101>, /* i2s3 */
 847                          <&tegra_car 102>, /* i2s4 */
 848                          <&tegra_car 108>, /* dam0 */
 849                          <&tegra_car 109>, /* dam1 */
 850                          <&tegra_car 110>, /* dam2 */
 851                          <&tegra_car 10>;  /* spdif */
 852                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 853                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 854                               "spdif";
 855                 dmas = <&apbdma 1>, <&apbdma 1>,
 856                        <&apbdma 2>, <&apbdma 2>,
 857                        <&apbdma 3>, <&apbdma 3>,
 858                        <&apbdma 4>, <&apbdma 4>;
 859                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 860                             "rx3", "tx3";
 861                 ranges;
 862                 #address-cells = <1>;
 863                 #size-cells = <1>;
 864
 865                 tegra_i2s0: i2s@70080300 {
 866                         compatible = "nvidia,tegra30-i2s";
 867                         reg = <0x70080300 0x100>;
 868                         nvidia,ahub-cif-ids = <4 4>;
 869                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 870                         resets = <&tegra_car 30>;
 871                         reset-names = "i2s";
 872                         status = "disabled";
 873                 };
 874
 875                 tegra_i2s1: i2s@70080400 {
 876                         compatible = "nvidia,tegra30-i2s";
 877                         reg = <0x70080400 0x100>;
 878                         nvidia,ahub-cif-ids = <5 5>;
 879                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 880                         resets = <&tegra_car 11>;
 881                         reset-names = "i2s";
 882                         status = "disabled";
 883                 };
 884
 885                 tegra_i2s2: i2s@70080500 {
 886                         compatible = "nvidia,tegra30-i2s";
 887                         reg = <0x70080500 0x100>;
 888                         nvidia,ahub-cif-ids = <6 6>;
 889                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 890                         resets = <&tegra_car 18>;
 891                         reset-names = "i2s";
 892                         status = "disabled";
 893                 };
 894
 895                 tegra_i2s3: i2s@70080600 {
 896                         compatible = "nvidia,tegra30-i2s";
 897                         reg = <0x70080600 0x100>;
 898                         nvidia,ahub-cif-ids = <7 7>;
 899                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 900                         resets = <&tegra_car 101>;
 901                         reset-names = "i2s";
 902                         status = "disabled";
 903                 };
 904
 905                 tegra_i2s4: i2s@70080700 {
 906                         compatible = "nvidia,tegra30-i2s";
 907                         reg = <0x70080700 0x100>;
 908                         nvidia,ahub-cif-ids = <8 8>;
 909                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 910                         resets = <&tegra_car 102>;
 911                         reset-names = "i2s";
 912                         status = "disabled";
 913                 };
 914         };
 915
 916         mmc@78000000 {
 917                 compatible = "nvidia,tegra30-sdhci";
 918                 reg = <0x78000000 0x200>;
 919                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 920                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 921                 clock-names = "sdhci";
 922                 resets = <&tegra_car 14>;
 923                 reset-names = "sdhci";
 924                 status = "disabled";
 925         };
 926
 927         mmc@78000200 {
 928                 compatible = "nvidia,tegra30-sdhci";
 929                 reg = <0x78000200 0x200>;
 930                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 931                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 932                 clock-names = "sdhci";
 933                 resets = <&tegra_car 9>;
 934                 reset-names = "sdhci";
 935                 status = "disabled";
 936         };
 937
 938         mmc@78000400 {
 939                 compatible = "nvidia,tegra30-sdhci";
 940                 reg = <0x78000400 0x200>;
 941                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 942                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 943                 clock-names = "sdhci";
 944                 resets = <&tegra_car 69>;
 945                 reset-names = "sdhci";
 946                 status = "disabled";
 947         };
 948
 949         mmc@78000600 {
 950                 compatible = "nvidia,tegra30-sdhci";
 951                 reg = <0x78000600 0x200>;
 952                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 953                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 954                 clock-names = "sdhci";
 955                 resets = <&tegra_car 15>;
 956                 reset-names = "sdhci";
 957                 status = "disabled";
 958         };
 959
 960         usb@7d000000 {
 961                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 962                 reg = <0x7d000000 0x4000>;
 963                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 964                 phy_type = "utmi";
 965                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 966                 resets = <&tegra_car 22>;
 967                 reset-names = "usb";
 968                 nvidia,needs-double-reset;
 969                 nvidia,phy = <&phy1>;
 970                 status = "disabled";
 971         };
 972
 973         phy1: usb-phy@7d000000 {
 974                 compatible = "nvidia,tegra30-usb-phy";
 975                 reg = <0x7d000000 0x4000>,
 976                       <0x7d000000 0x4000>;
 977                 phy_type = "utmi";
 978                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 979                          <&tegra_car TEGRA30_CLK_PLL_U>,
 980                          <&tegra_car TEGRA30_CLK_USBD>;
 981                 clock-names = "reg", "pll_u", "utmi-pads";
 982                 resets = <&tegra_car 22>, <&tegra_car 22>;
 983                 reset-names = "usb", "utmi-pads";
 984                 #phy-cells = <0>;
 985                 nvidia,hssync-start-delay = <9>;
 986                 nvidia,idle-wait-delay = <17>;
 987                 nvidia,elastic-limit = <16>;
 988                 nvidia,term-range-adj = <6>;
 989                 nvidia,xcvr-setup = <51>;
 990                 nvidia,xcvr-setup-use-fuses;
 991                 nvidia,xcvr-lsfslew = <1>;
 992                 nvidia,xcvr-lsrslew = <1>;
 993                 nvidia,xcvr-hsslew = <32>;
 994                 nvidia,hssquelch-level = <2>;
 995                 nvidia,hsdiscon-level = <5>;
 996                 nvidia,has-utmi-pad-registers;
 997                 status = "disabled";
 998         };
 999
1000         usb@7d004000 {
1001                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
1002                 reg = <0x7d004000 0x4000>;
1003                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1004                 phy_type = "utmi";
1005                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
1006                 resets = <&tegra_car 58>;
1007                 reset-names = "usb";
1008                 nvidia,phy = <&phy2>;
1009                 status = "disabled";
1010         };
1011
1012         phy2: usb-phy@7d004000 {
1013                 compatible = "nvidia,tegra30-usb-phy";
1014                 reg = <0x7d004000 0x4000>,
1015                       <0x7d000000 0x4000>;
1016                 phy_type = "utmi";
1017                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
1018                          <&tegra_car TEGRA30_CLK_PLL_U>,
1019                          <&tegra_car TEGRA30_CLK_USBD>;
1020                 clock-names = "reg", "pll_u", "utmi-pads";
1021                 resets = <&tegra_car 58>, <&tegra_car 22>;
1022                 reset-names = "usb", "utmi-pads";
1023                 #phy-cells = <0>;
1024                 nvidia,hssync-start-delay = <9>;
1025                 nvidia,idle-wait-delay = <17>;
1026                 nvidia,elastic-limit = <16>;
1027                 nvidia,term-range-adj = <6>;
1028                 nvidia,xcvr-setup = <51>;
1029                 nvidia,xcvr-setup-use-fuses;
1030                 nvidia,xcvr-lsfslew = <2>;
1031                 nvidia,xcvr-lsrslew = <2>;
1032                 nvidia,xcvr-hsslew = <32>;
1033                 nvidia,hssquelch-level = <2>;
1034                 nvidia,hsdiscon-level = <5>;
1035                 status = "disabled";
1036         };
1037
1038         usb@7d008000 {
1039                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
1040                 reg = <0x7d008000 0x4000>;
1041                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1042                 phy_type = "utmi";
1043                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
1044                 resets = <&tegra_car 59>;
1045                 reset-names = "usb";
1046                 nvidia,phy = <&phy3>;
1047                 status = "disabled";
1048         };
1049
1050         phy3: usb-phy@7d008000 {
1051                 compatible = "nvidia,tegra30-usb-phy";
1052                 reg = <0x7d008000 0x4000>,
1053                       <0x7d000000 0x4000>;
1054                 phy_type = "utmi";
1055                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
1056                          <&tegra_car TEGRA30_CLK_PLL_U>,
1057                          <&tegra_car TEGRA30_CLK_USBD>;
1058                 clock-names = "reg", "pll_u", "utmi-pads";
1059                 resets = <&tegra_car 59>, <&tegra_car 22>;
1060                 reset-names = "usb", "utmi-pads";
1061                 #phy-cells = <0>;
1062                 nvidia,hssync-start-delay = <0>;
1063                 nvidia,idle-wait-delay = <17>;
1064                 nvidia,elastic-limit = <16>;
1065                 nvidia,term-range-adj = <6>;
1066                 nvidia,xcvr-setup = <51>;
1067                 nvidia,xcvr-setup-use-fuses;
1068                 nvidia,xcvr-lsfslew = <2>;
1069                 nvidia,xcvr-lsrslew = <2>;
1070                 nvidia,xcvr-hsslew = <32>;
1071                 nvidia,hssquelch-level = <2>;
1072                 nvidia,hsdiscon-level = <5>;
1073                 status = "disabled";
1074         };
1075
1076         cpus {
1077                 #address-cells = <1>;
1078                 #size-cells = <0>;
1079
1080                 cpu0: cpu@0 {
1081                         device_type = "cpu";
1082                         compatible = "arm,cortex-a9";
1083                         reg = <0>;
1084                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1085                         #cooling-cells = <2>;
1086                 };
1087
1088                 cpu1: cpu@1 {
1089                         device_type = "cpu";
1090                         compatible = "arm,cortex-a9";
1091                         reg = <1>;
1092                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1093                         #cooling-cells = <2>;
1094                 };
1095
1096                 cpu2: cpu@2 {
1097                         device_type = "cpu";
1098                         compatible = "arm,cortex-a9";
1099                         reg = <2>;
1100                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1101                         #cooling-cells = <2>;
1102                 };
1103
1104                 cpu3: cpu@3 {
1105                         device_type = "cpu";
1106                         compatible = "arm,cortex-a9";
1107                         reg = <3>;
1108                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1109                         #cooling-cells = <2>;
1110                 };
1111         };
1112
1113         pmu {
1114                 compatible = "arm,cortex-a9-pmu";
1115                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1116                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1117                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1118                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1119                 interrupt-affinity = <&{/cpus/cpu@0}>,
1120                                      <&{/cpus/cpu@1}>,
1121                                      <&{/cpus/cpu@2}>,
1122                                      <&{/cpus/cpu@3}>;
1123         };
1124
1125         thermal-zones {
1126                 tsensor0-thermal {
1127                         polling-delay-passive = <1000>; /* milliseconds */
1128                         polling-delay = <5000>; /* milliseconds */
1129
1130                         thermal-sensors = <&tsensor 0>;
1131
1132                         trips {
1133                                 level1_trip: dvfs-alert {
1134                                         /* throttle at 80C until temperature drops to 79.8C */
1135                                         temperature = <80000>;
1136                                         hysteresis = <200>;
1137                                         type = "passive";
1138                                 };
1139
1140                                 level2_trip: cpu-div2-throttle {
1141                                         /* hardware CPU x2 freq throttle at 85C */
1142                                         temperature = <85000>;
1143                                         hysteresis = <200>;
1144                                         type = "hot";
1145                                 };
1146
1147                                 level3_trip: soc-critical {
1148                                         /* hardware shut down at 90C */
1149                                         temperature = <90000>;
1150                                         hysteresis = <2000>;
1151                                         type = "critical";
1152                                 };
1153                         };
1154
1155                         cooling-maps {
1156                                 map0 {
1157                                         trip = <&level1_trip>;
1158                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1159                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1160                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1161                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1162                                                          <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1163                                 };
1164                         };
1165                 };
1166
1167                 tsensor1-thermal {
1168                         status = "disabled";
1169
1170                         polling-delay-passive = <1000>; /* milliseconds */
1171                         polling-delay = <0>; /* milliseconds */
1172
1173                         thermal-sensors = <&tsensor 1>;
1174
1175                         trips {
1176                                 dvfs-alert {
1177                                         temperature = <80000>;
1178                                         hysteresis = <200>;
1179                                         type = "passive";
1180                                 };
1181                         };
1182                 };
1183         };
1184 };