arch/arm/boot/dts/tegra30-ouya.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/input/gpio-keys.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/thermal/thermal.h>
   7
   8 #include "tegra30.dtsi"
   9 #include "tegra30-cpu-opp.dtsi"
  10 #include "tegra30-cpu-opp-microvolt.dtsi"
  11
  12 / {
  13         model = "Ouya Game Console";
  14         compatible = "ouya,ouya", "nvidia,tegra30";
  15
  16         aliases {
  17                 mmc0 = &sdmmc4; /* eMMC */
  18                 mmc1 = &sdmmc3; /* WiFi */
  19                 rtc0 = &pmic;
  20                 rtc1 = "/rtc@7000e000";
  21                 serial0 = &uartd; /* Debug Port */
  22                 serial1 = &uartc; /* Bluetooth */
  23         };
  24
  25         chosen {
  26                 stdout-path = "serial0:115200n8";
  27         };
  28
  29         memory@80000000 {
  30                 reg = <0x80000000 0x40000000>;
  31         };
  32
  33         reserved-memory {
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 ranges;
  37
  38                 linux,cma@80000000 {
  39                         compatible = "shared-dma-pool";
  40                         alloc-ranges = <0x80000000 0x30000000>;
  41                         size = <0x10000000>; /* 256MiB */
  42                         linux,cma-default;
  43                         reusable;
  44                 };
  45
  46                 ramoops@bfdf0000 {
  47                         compatible = "ramoops";
  48                         reg = <0xbfdf0000 0x10000>;     /* 64kB */
  49                         console-size = <0x8000>;        /* 32kB */
  50                         record-size = <0x400>;          /*  1kB */
  51                         ecc-size = <16>;
  52                 };
  53
  54                 trustzone@bfe00000 {
  55                         reg = <0xbfe00000 0x200000>;
  56                         no-map;
  57                 };
  58         };
  59
  60         host1x@50000000 {
  61                 hdmi@54280000 {
  62                         status = "okay";
  63                         vdd-supply = <&vdd_vid_reg>;
  64                         pll-supply = <&ldo7_reg>;
  65                         hdmi-supply = <&sys_3v3_reg>;
  66                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  67                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  68                 };
  69         };
  70
  71         gpio: gpio@6000d000 {
  72                 gpio-ranges = <&pinmux 0 0 248>;
  73                 #reset-cells = <1>;
  74         };
  75
  76         pinmux@70000868 {
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&state_default>;
  79                 state_default: pinmux {
  80                         /* located at $state_default below */
  81                 };
  82         };
  83
  84         uartc: serial@70006200 {
  85                 status = "okay";
  86                 compatible = "nvidia,tegra30-hsuart";
  87
  88                 nvidia,adjust-baud-rates = <0 9600 100>,
  89                                            <9600 115200 200>,
  90                                            <1000000 4000000 136>;
  91
  92                 /* Azurewave AW-NH660 BCM4330B1 */
  93                 bluetooth {
  94                         compatible = "brcm,bcm4330-bt";
  95
  96                         max-speed = <4000000>;
  97
  98                         clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  99                         clock-names = "txco";
 100
 101                         vbat-supply  = <&sys_3v3_reg>;
 102                         vddio-supply = <&vdd_1v8>;
 103
 104                         shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
 105                         device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
 106                         host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
 107                 };
 108         };
 109
 110         uartd: serial@70006300 {
 111                 status = "okay";
 112         };
 113
 114         hdmi_ddc: i2c@7000c700 {
 115                 status = "okay";
 116                 clock-frequency = <100000>;
 117         };
 118
 119         i2c@7000d000 {
 120                 status = "okay";
 121                 clock-frequency = <400000>;
 122
 123                 cpu_temp: nct1008@4c {
 124                         compatible = "onnn,nct1008";
 125                         reg = <0x4c>;
 126                         vcc-supply = <&sys_3v3_reg>;
 127
 128                         interrupt-parent = <&gpio>;
 129                         interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
 130
 131                         #thermal-sensor-cells = <1>;
 132                 };
 133
 134                 pmic: pmic@2d {
 135                         compatible = "ti,tps65911";
 136                         reg = <0x2d>;
 137
 138                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 139                         #interrupt-cells = <2>;
 140                         interrupt-controller;
 141                         wakeup-source;
 142
 143                         ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>;
 144                         ti,system-power-controller;
 145                         ti,sleep-keep-ck32k;
 146                         ti,sleep-enable;
 147
 148                         #gpio-cells = <2>;
 149                         gpio-controller;
 150
 151                         vcc1-supply = <&vdd_5v0_reg>;
 152                         vcc2-supply = <&vdd_5v0_reg>;
 153                         vcc3-supply = <&vdd_1v8>;
 154                         vcc4-supply = <&vdd_5v0_reg>;
 155                         vcc5-supply = <&vdd_5v0_reg>;
 156                         vcc6-supply = <&vdd2_reg>;
 157                         vcc7-supply = <&vdd_5v0_reg>;
 158                         vccio-supply = <&vdd_5v0_reg>;
 159
 160                         regulators {
 161                                 vdd1_reg: vdd1 {
 162                                         regulator-name = "vddio_ddr_1v2";
 163                                         regulator-min-microvolt = <1200000>;
 164                                         regulator-max-microvolt = <1200000>;
 165                                         regulator-always-on;
 166                                 };
 167
 168                                 vdd2_reg: vdd2 {
 169                                         regulator-name = "vdd_1v5_gen";
 170                                         regulator-min-microvolt = <1500000>;
 171                                         regulator-max-microvolt = <1500000>;
 172                                         regulator-always-on;
 173                                 };
 174
 175                                 vdd_cpu: vddctrl {
 176                                         regulator-name = "vdd_cpu,vdd_sys";
 177                                         regulator-min-microvolt = <800000>;
 178                                         regulator-max-microvolt = <1270000>;
 179                                         regulator-coupled-with = <&vdd_core>;
 180                                         regulator-coupled-max-spread = <300000>;
 181                                         regulator-max-step-microvolt = <100000>;
 182                                         regulator-always-on;
 183
 184                                         nvidia,tegra-cpu-regulator;
 185                                 };
 186
 187                                 vdd_1v8: vio {
 188                                         regulator-name = "vdd_1v8_gen";
 189                                         regulator-min-microvolt = <1800000>;
 190                                         regulator-max-microvolt = <1800000>;
 191                                         regulator-always-on;
 192                                 };
 193
 194                                 ldo1_reg: ldo1 {
 195                                         regulator-name = "vdd_pexa,vdd_pexb";
 196                                         regulator-min-microvolt = <1050000>;
 197                                         regulator-max-microvolt = <1050000>;
 198                                         regulator-always-on;
 199                                 };
 200
 201                                 ldo2_reg: ldo2 {
 202                                         regulator-name = "vdd_sata,avdd_plle";
 203                                         regulator-min-microvolt = <1050000>;
 204                                         regulator-max-microvolt = <1050000>;
 205                                         regulator-always-on;
 206                                 };
 207
 208                                 /* LDO3 is not connected to anything */
 209
 210                                 ldo4_reg: ldo4 {
 211                                         regulator-name = "vdd_rtc";
 212                                         regulator-min-microvolt = <1200000>;
 213                                         regulator-max-microvolt = <1200000>;
 214                                         regulator-always-on;
 215                                 };
 216
 217                                 ldo5_reg: ldo5 {
 218                                         regulator-name = "vddio_sdmmc,avdd_vdac";
 219                                         regulator-min-microvolt = <1800000>;
 220                                         regulator-max-microvolt = <3300000>;
 221                                         regulator-always-on;
 222                                 };
 223
 224                                 ldo6_reg: ldo6 {
 225                                         regulator-name = "avdd_dsi_csi,pwrdet_mipi";
 226                                         regulator-min-microvolt = <1200000>;
 227                                         regulator-max-microvolt = <1200000>;
 228                                         regulator-always-on;
 229                                 };
 230
 231                                 ldo7_reg: ldo7 {
 232                                         regulator-name = "vdd_pllm,x,u,a_p_c_s";
 233                                         regulator-min-microvolt = <1200000>;
 234                                         regulator-max-microvolt = <1200000>;
 235                                         regulator-always-on;
 236                                 };
 237
 238                                 ldo8_reg: ldo8 {
 239                                         regulator-name = "vdd_ddr_hs";
 240                                         regulator-min-microvolt = <1000000>;
 241                                         regulator-max-microvolt = <1000000>;
 242                                         regulator-always-on;
 243                                 };
 244                         };
 245                 };
 246
 247                 vdd_core: tps62361@60 {
 248                         compatible = "ti,tps62361";
 249                         reg = <0x60>;
 250
 251                         regulator-name = "vdd_core";
 252                         regulator-min-microvolt = <950000>;
 253                         regulator-max-microvolt = <1350000>;
 254                         regulator-coupled-with = <&vdd_cpu>;
 255                         regulator-coupled-max-spread = <300000>;
 256                         regulator-max-step-microvolt = <100000>;
 257                         regulator-boot-on;
 258                         regulator-always-on;
 259                         ti,vsel0-state-high;
 260                         ti,vsel1-state-high;
 261                         ti,enable-vout-discharge;
 262
 263                         nvidia,tegra-core-regulator;
 264                 };
 265         };
 266
 267         pmc@7000e400 {
 268                 status = "okay";
 269                 nvidia,invert-interrupt;
 270                 nvidia,suspend-mode = <1>;
 271                 nvidia,cpu-pwr-good-time = <2000>;
 272                 nvidia,cpu-pwr-off-time = <200>;
 273                 nvidia,core-pwr-good-time = <3845 3845>;
 274                 nvidia,core-pwr-off-time = <458>;
 275                 nvidia,core-power-req-active-high;
 276                 nvidia,sys-clock-req-active-high;
 277         };
 278
 279         mc_timings: memory-controller@7000f000 {
 280                 /* timings located at &mc_timings below */
 281         };
 282
 283         emc_timings: memory-controller@7000f400 {
 284                 /* timings located at &emc_timings below */
 285         };
 286
 287         hda@70030000 {
 288                 status = "okay";
 289         };
 290
 291         wifi_pwrseq: wifi_pwrseq {
 292                 compatible = "mmc-pwrseq-simple";
 293
 294                 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
 295                 clock-names = "ext_clock";
 296
 297                 reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
 298                 post-power-on-delay-ms = <300>;
 299                 power-off-delay-us = <300>;
 300         };
 301
 302         sdmmc3: mmc@78000400 {
 303                 status = "okay";
 304
 305                 #address-cells = <1>;
 306                 #size-cells = <0>;
 307
 308                 assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 309                 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
 310                 assigned-clock-rates = <50000000>;
 311
 312                 max-frequency = <50000000>;
 313                 keep-power-in-suspend;
 314
 315                 bus-width = <4>;
 316                 non-removable;
 317
 318                 mmc-pwrseq = <&wifi_pwrseq>;
 319                 vmmc-supply = <&sdmmc_3v3_reg>;
 320                 vqmmc-supply = <&vdd_1v8>;
 321
 322                 /* Azurewave AW-NH660 BCM4330 */
 323                 brcmf: wifi@1 {
 324                         reg = <1>;
 325                         compatible = "brcm,bcm4329-fmac";
 326                         interrupt-parent = <&gpio>;
 327                         interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
 328                         interrupt-names = "host-wake";
 329                 };
 330         };
 331
 332         sdmmc4: mmc@78000600 {
 333                 status = "okay";
 334
 335                 keep-power-in-suspend;
 336                 bus-width = <8>;
 337                 non-removable;
 338                 vmmc-supply = <&sys_3v3_reg>;
 339                 vqmmc-supply = <&vdd_1v8>;
 340                 nvidia,default-tap = <0x0F>;
 341                 max-frequency = <25500000>;
 342         };
 343
 344         usb@7d000000 {
 345                 compatible = "nvidia,tegra30-udc";
 346                 status = "okay";
 347         };
 348
 349         usb-phy@7d000000 {
 350                 status = "okay";
 351                 dr_mode = "peripheral";
 352         };
 353
 354         usb@7d004000 {
 355                 status = "okay";
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358
 359                 smsc@2 { /* SMSC 10/100T Ethernet Controller */
 360                         compatible = "usb424,9e00";
 361                         reg = <2>;
 362                         local-mac-address = [00 11 22 33 44 55];
 363                 };
 364         };
 365
 366         usb-phy@7d004000 {
 367                 vbus-supply = <&vdd_smsc>;
 368                 status = "okay";
 369         };
 370
 371         usb@7d008000 {
 372                 status = "okay";
 373         };
 374
 375         usb-phy@7d008000 {
 376                 vbus-supply = <&usb3_vbus_reg>;
 377                 status = "okay";
 378         };
 379
 380         /* PMIC has a built-in 32KHz oscillator which is used by PMC */
 381         clk32k_in: clock {
 382                 compatible = "fixed-clock";
 383                 #clock-cells = <0>;
 384                 clock-frequency = <32768>;
 385                 clock-output-names = "pmic-oscillator";
 386         };
 387
 388         cpus {
 389                 cpu0: cpu@0 {
 390                         operating-points-v2 = <&cpu0_opp_table>;
 391                         cpu-supply = <&vdd_cpu>;
 392                         #cooling-cells = <2>;
 393                 };
 394
 395                 cpu1: cpu@1 {
 396                         operating-points-v2 = <&cpu0_opp_table>;
 397                         cpu-supply = <&vdd_cpu>;
 398                         #cooling-cells = <2>;
 399                 };
 400
 401                 cpu2: cpu@2 {
 402                         operating-points-v2 = <&cpu0_opp_table>;
 403                         cpu-supply = <&vdd_cpu>;
 404                         #cooling-cells = <2>;
 405                 };
 406
 407                 cpu3: cpu@3 {
 408                         operating-points-v2 = <&cpu0_opp_table>;
 409                         cpu-supply = <&vdd_cpu>;
 410                         #cooling-cells = <2>;
 411                 };
 412         };
 413
 414         firmware {
 415                 trusted-foundations {
 416                         compatible = "tlm,trusted-foundations";
 417                         tlm,version-major = <0x0>;
 418                         tlm,version-minor = <0x0>;
 419                 };
 420         };
 421
 422         fan: gpio_fan {
 423                 compatible = "gpio-fan";
 424                 gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
 425                 gpio-fan,speed-map = <0    0
 426                                       4500 1>;
 427                 #cooling-cells = <2>;
 428         };
 429
 430         thermal-zones {
 431                 cpu_thermal: cpu-thermal {
 432                         polling-delay = <5000>;
 433                         polling-delay-passive = <5000>;
 434
 435                         thermal-sensors = <&cpu_temp 1>;
 436
 437                         trips {
 438                                 cpu_alert0: cpu-alert0 {
 439                                         temperature = <50000>;
 440                                         hysteresis = <10000>;
 441                                         type = "active";
 442                                 };
 443                                 cpu_alert1: cpu-alert1 {
 444                                         temperature = <70000>;
 445                                         hysteresis = <5000>;
 446                                         type = "passive";
 447                                 };
 448                                 cpu_crit: cpu-crit {
 449                                         temperature = <90000>;
 450                                         hysteresis = <2000>;
 451                                         type = "critical";
 452                                 };
 453                         };
 454
 455                         cooling-maps {
 456                                 map0 {
 457                                         trip = <&cpu_alert0>;
 458                                         cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 459                                 };
 460                                 map1 {
 461                                         trip = <&cpu_alert1>;
 462                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 463                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 464                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 465                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 466                                                          <&actmon THERMAL_NO_LIMIT
 467                                                                   THERMAL_NO_LIMIT>;
 468                                 };
 469                         };
 470                 };
 471         };
 472
 473         vdd_12v_in: vdd_12v_in {
 474                 compatible = "regulator-fixed";
 475                 regulator-name = "vdd_12v_in";
 476                 regulator-min-microvolt = <12000000>;
 477                 regulator-max-microvolt = <12000000>;
 478                 regulator-always-on;
 479         };
 480
 481         sdmmc_3v3_reg: sdmmc_3v3_reg {
 482                 compatible = "regulator-fixed";
 483                 regulator-name = "sdmmc_3v3";
 484                 regulator-min-microvolt = <3300000>;
 485                 regulator-max-microvolt = <3300000>;
 486                 enable-active-high;
 487                 regulator-always-on;
 488                 gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
 489                 vin-supply = <&sys_3v3_reg>;
 490         };
 491
 492         vdd_fuse_3v3_reg: vdd_fuse_3v3_reg {
 493                 compatible = "regulator-fixed";
 494                 regulator-name = "vdd_fuse_3v3";
 495                 regulator-min-microvolt = <3300000>;
 496                 regulator-max-microvolt = <3300000>;
 497                 enable-active-high;
 498                 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
 499                 vin-supply = <&sys_3v3_reg>;
 500                 regulator-always-on;
 501         };
 502
 503         vdd_vid_reg: vdd_vid_reg {
 504                 compatible = "regulator-fixed";
 505                 regulator-name = "vddio_vid";
 506                 regulator-min-microvolt = <5000000>;
 507                 regulator-max-microvolt = <5000000>;
 508                 enable-active-high;
 509                 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
 510                 vin-supply = <&vdd_5v0_reg>;
 511                 regulator-boot-on;
 512         };
 513
 514         ddr_reg: ddr_reg {
 515                 compatible = "regulator-fixed";
 516                 regulator-name = "vdd_ddr";
 517                 regulator-min-microvolt = <1500000>;
 518                 regulator-max-microvolt = <1500000>;
 519                 regulator-always-on;
 520                 enable-active-high;
 521                 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 522                 regulator-boot-on;
 523                 vin-supply = <&vdd_12v_in>;
 524         };
 525
 526         sys_3v3_reg: sys_3v3_reg {
 527                 compatible = "regulator-fixed";
 528                 regulator-name = "sys_3v3";
 529                 regulator-min-microvolt = <3300000>;
 530                 regulator-max-microvolt = <3300000>;
 531                 enable-active-high;
 532                 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 533                 regulator-always-on;
 534                 regulator-boot-on;
 535                 vin-supply = <&vdd_12v_in>;
 536         };
 537
 538         vdd_5v0_reg: vdd_5v0_reg {
 539                 compatible = "regulator-fixed";
 540                 regulator-name = "vdd_5v0";
 541                 regulator-min-microvolt = <5000000>;
 542                 regulator-max-microvolt = <5000000>;
 543                 enable-active-high;
 544                 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 545                 regulator-always-on;
 546                 regulator-boot-on;
 547                 vin-supply = <&vdd_12v_in>;
 548         };
 549
 550         vdd_smsc: vdd_smsc {
 551                 compatible = "regulator-fixed";
 552                 regulator-name = "vdd_smsc";
 553                 enable-active-high;
 554                 gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>;
 555         };
 556
 557         usb3_vbus_reg: usb3_vbus_reg {
 558                 compatible = "regulator-fixed";
 559                 regulator-name = "usb3_vbus";
 560                 regulator-min-microvolt = <5000000>;
 561                 regulator-max-microvolt = <5000000>;
 562                 enable-active-high;
 563                 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
 564                 vin-supply = <&vdd_5v0_reg>;
 565         };
 566
 567         gpio-keys {
 568                 compatible = "gpio-keys";
 569
 570                 power {
 571                         gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
 572                         debounce-interval = <10>;
 573                         linux,code = <KEY_POWER>;
 574                         wakeup-event-action = <EV_ACT_ASSERTED>;
 575                         wakeup-source;
 576                 };
 577         };
 578
 579
 580         leds {
 581                 compatible = "gpio-leds";
 582
 583                 led-power {
 584                         label = "power-led";
 585                         gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
 586                         default-state = "on";
 587                         linux,default-trigger = "heartbeat";
 588                         retain-state-suspended;
 589                 };
 590         };
 591 };
 592 &mc_timings {
 593         emc-timings-0 {
 594                 nvidia,ram-code = <0>; /* Samsung RAM */
 595                 timing-25500000 {
 596                         clock-frequency = <25500000>;
 597                         nvidia,emem-configuration = <
 598                                 0x00030003 /* MC_EMEM_ARB_CFG */
 599                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 600                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 601                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 602                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 603                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 604                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 605                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 606                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 607                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 608                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 609                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 610                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 611                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 612                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 613                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 614                                 0x75830303 /* MC_EMEM_ARB_MISC0 */
 615                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 616                         >;
 617                 };
 618                 timing-51000000 {
 619                         clock-frequency = <51000000>;
 620                         nvidia,emem-configuration = <
 621                                 0x00010003 /* MC_EMEM_ARB_CFG */
 622                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 623                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 624                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 625                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 626                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 627                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 628                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 629                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 630                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 631                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 632                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 633                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 634                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 635                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 636                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 637                                 0x74630303 /* MC_EMEM_ARB_MISC0 */
 638                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 639                         >;
 640                 };
 641                 timing-102000000 {
 642                         clock-frequency = <102000000>;
 643                         nvidia,emem-configuration = <
 644                                 0x00000003 /* MC_EMEM_ARB_CFG */
 645                                 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 646                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 647                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 648                                 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 649                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 650                                 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 651                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 652                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 653                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 654                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 655                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 656                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 657                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 658                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 659                                 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 660                                 0x73c30504 /* MC_EMEM_ARB_MISC0 */
 661                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 662                         >;
 663                 };
 664                 timing-204000000 {
 665                         clock-frequency = <204000000>;
 666                         nvidia,emem-configuration = <
 667                                 0x00000006 /* MC_EMEM_ARB_CFG */
 668                                 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 669                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 670                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 671                                 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 672                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 673                                 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 674                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 675                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 676                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 677                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 678                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 679                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 680                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 681                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 682                                 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 683                                 0x73840a06 /* MC_EMEM_ARB_MISC0 */
 684                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 685                         >;
 686                 };
 687                 timing-400000000 {
 688                         clock-frequency = <400000000>;
 689                         nvidia,emem-configuration = <
 690                                 0x0000000c /* MC_EMEM_ARB_CFG */
 691                                 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 692                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 693                                 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 694                                 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 695                                 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 696                                 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 697                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 698                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 699                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 700                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 701                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 702                                 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 703                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 704                                 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 705                                 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 706                                 0x7086120a /* MC_EMEM_ARB_MISC0 */
 707                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 708                         >;
 709                 };
 710                 timing-800000000 {
 711                         clock-frequency = <800000000>;
 712                         nvidia,emem-configuration = <
 713                                 0x00000018 /* MC_EMEM_ARB_CFG */
 714                                 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 715                                 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 716                                 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
 717                                 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
 718                                 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
 719                                 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
 720                                 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
 721                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 722                                 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
 723                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 724                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 725                                 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
 726                                 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
 727                                 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
 728                                 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
 729                                 0x712c2414 /* MC_EMEM_ARB_MISC0 */
 730                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 731                         >;
 732                 };
 733         };
 734         emc-timings-1 {
 735                 nvidia,ram-code = <1>; /* Hynix M RAM */
 736                 timing-25500000 {
 737                         clock-frequency = <25500000>;
 738                         nvidia,emem-configuration = <
 739                                 0x00030003 /* MC_EMEM_ARB_CFG */
 740                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 741                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 742                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 743                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 744                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 745                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 746                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 747                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 748                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 749                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 750                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 751                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 752                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 753                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 754                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 755                                 0x75830303 /* MC_EMEM_ARB_MISC0 */
 756                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 757                         >;
 758                 };
 759                 timing-51000000 {
 760                         clock-frequency = <51000000>;
 761                         nvidia,emem-configuration = <
 762                                 0x00010003 /* MC_EMEM_ARB_CFG */
 763                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 764                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 765                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 766                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 767                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 768                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 769                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 770                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 771                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 772                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 773                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 774                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 775                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 776                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 777                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 778                                 0x74630303 /* MC_EMEM_ARB_MISC0 */
 779                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 780                         >;
 781                 };
 782                 timing-102000000 {
 783                         clock-frequency = <102000000>;
 784                         nvidia,emem-configuration = <
 785                                 0x00000003 /* MC_EMEM_ARB_CFG */
 786                                 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 787                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 788                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 789                                 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 790                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 791                                 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 792                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 793                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 794                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 795                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 796                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 797                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 798                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 799                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 800                                 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 801                                 0x73c30504 /* MC_EMEM_ARB_MISC0 */
 802                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 803                         >;
 804                 };
 805                 timing-204000000 {
 806                         clock-frequency = <204000000>;
 807                         nvidia,emem-configuration = <
 808                                 0x00000006 /* MC_EMEM_ARB_CFG */
 809                                 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 810                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 811                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 812                                 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 813                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 814                                 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 815                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 816                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 817                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 818                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 819                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 820                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 821                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 822                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 823                                 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 824                                 0x73840a06 /* MC_EMEM_ARB_MISC0 */
 825                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 826                         >;
 827                 };
 828                 timing-400000000 {
 829                         clock-frequency = <400000000>;
 830                         nvidia,emem-configuration = <
 831                                 0x0000000c /* MC_EMEM_ARB_CFG */
 832                                 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 833                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 834                                 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 835                                 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 836                                 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 837                                 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 838                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 839                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 840                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 841                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 842                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 843                                 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 844                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 845                                 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 846                                 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 847                                 0x7086120a /* MC_EMEM_ARB_MISC0 */
 848                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 849                         >;
 850                 };
 851                 timing-800000000 {
 852                         clock-frequency = <800000000>;
 853                         nvidia,emem-configuration = <
 854                                 0x00000018 /* MC_EMEM_ARB_CFG */
 855                                 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 856                                 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 857                                 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
 858                                 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
 859                                 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
 860                                 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
 861                                 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
 862                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 863                                 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
 864                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 865                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 866                                 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
 867                                 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
 868                                 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
 869                                 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
 870                                 0x712c2414 /* MC_EMEM_ARB_MISC0 */
 871                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 872                         >;
 873                 };
 874         };
 875         emc-timings-2 {
 876                 nvidia,ram-code = <2>; /* Hynix A RAM */
 877                 timing-25500000 {
 878                         clock-frequency = <25500000>;
 879                         nvidia,emem-configuration = <
 880                                 0x00030003 /* MC_EMEM_ARB_CFG */
 881                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 882                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 883                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 884                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 885                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 886                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 887                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 888                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 889                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 890                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 891                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 892                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 893                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 894                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 895                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 896                                 0x75e30303 /* MC_EMEM_ARB_MISC0 */
 897                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 898                         >;
 899                 };
 900                 timing-51000000 {
 901                         clock-frequency = <51000000>;
 902                         nvidia,emem-configuration = <
 903                                 0x00010003 /* MC_EMEM_ARB_CFG */
 904                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 905                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 906                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 907                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 908                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 909                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 910                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 911                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 912                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 913                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 914                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 915                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 916                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 917                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 918                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 919                                 0x74e30303 /* MC_EMEM_ARB_MISC0 */
 920                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 921                         >;
 922                 };
 923                 timing-102000000 {
 924                         clock-frequency = <102000000>;
 925                         nvidia,emem-configuration = <
 926                                 0x00000003 /* MC_EMEM_ARB_CFG */
 927                                 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 928                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 929                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 930                                 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 931                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 932                                 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 933                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 934                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 935                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 936                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 937                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 938                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 939                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 940                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 941                                 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 942                                 0x74430504 /* MC_EMEM_ARB_MISC0 */
 943                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 944                         >;
 945                 };
 946                 timing-204000000 {
 947                         clock-frequency = <204000000>;
 948                         nvidia,emem-configuration = <
 949                                 0x00000006 /* MC_EMEM_ARB_CFG */
 950                                 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 951                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 952                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 953                                 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 954                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 955                                 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 956                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 957                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 958                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 959                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 960                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 961                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 962                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 963                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 964                                 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 965                                 0x74040a06 /* MC_EMEM_ARB_MISC0 */
 966                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 967                         >;
 968                 };
 969                 timing-400000000 {
 970                         clock-frequency = <400000000>;
 971                         nvidia,emem-configuration = <
 972                                 0x0000000c /* MC_EMEM_ARB_CFG */
 973                                 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 974                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 975                                 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 976                                 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 977                                 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 978                                 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 979                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 980                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 981                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 982                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 983                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 984                                 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 985                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 986                                 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 987                                 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 988                                 0x7086120a /* MC_EMEM_ARB_MISC0 */
 989                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 990                         >;
 991                 };
 992                 timing-800000000 {
 993                         clock-frequency = <800000000>;
 994                         nvidia,emem-configuration = <
 995                                 0x00000018 /* MC_EMEM_ARB_CFG */
 996                                 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 997                                 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 998                                 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
 999                                 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
1000                                 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
1001                                 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
1002                                 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
1003                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
1004                                 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
1005                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
1006                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
1007                                 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
1008                                 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
1009                                 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
1010                                 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
1011                                 0x712c2414 /* MC_EMEM_ARB_MISC0 */
1012                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
1013                         >;
1014                 };
1015         };
1016 };
1017 &emc_timings {
1018         emc-timings-0 {
1019                 nvidia,ram-code = <0>;  /* Samsung RAM */
1020                 timing-25500000 {
1021                         clock-frequency = <25500000>;
1022                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1023                         nvidia,emc-mode-1 = <0x80100003>;
1024                         nvidia,emc-mode-2 = <0x80200008>;
1025                         nvidia,emc-mode-reset = <0x80001221>;
1026                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1027                         nvidia,emc-cfg-periodic-qrst;
1028                         nvidia,emc-cfg-dyn-self-ref;
1029                         nvidia,emc-configuration = <
1030                                 0x00000001 /* EMC_RC */
1031                                 0x00000006 /* EMC_RFC */
1032                                 0x00000000 /* EMC_RAS */
1033                                 0x00000000 /* EMC_RP */
1034                                 0x00000002 /* EMC_R2W */
1035                                 0x0000000a /* EMC_W2R */
1036                                 0x00000005 /* EMC_R2P */
1037                                 0x0000000b /* EMC_W2P */
1038                                 0x00000000 /* EMC_RD_RCD */
1039                                 0x00000000 /* EMC_WR_RCD */
1040                                 0x00000003 /* EMC_RRD */
1041                                 0x00000001 /* EMC_REXT */
1042                                 0x00000000 /* EMC_WEXT */
1043                                 0x00000005 /* EMC_WDV */
1044                                 0x00000005 /* EMC_QUSE */
1045                                 0x00000004 /* EMC_QRST */
1046                                 0x0000000a /* EMC_QSAFE */
1047                                 0x0000000b /* EMC_RDV */
1048                                 0x000000c0 /* EMC_REFRESH */
1049                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1050                                 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
1051                                 0x00000002 /* EMC_PDEX2WR */
1052                                 0x00000002 /* EMC_PDEX2RD */
1053                                 0x00000001 /* EMC_PCHG2PDEN */
1054                                 0x00000000 /* EMC_ACT2PDEN */
1055                                 0x00000007 /* EMC_AR2PDEN */
1056                                 0x0000000f /* EMC_RW2PDEN */
1057                                 0x00000007 /* EMC_TXSR */
1058                                 0x00000007 /* EMC_TXSRDLL */
1059                                 0x00000004 /* EMC_TCKE */
1060                                 0x00000002 /* EMC_TFAW */
1061                                 0x00000000 /* EMC_TRPAB */
1062                                 0x00000004 /* EMC_TCLKSTABLE */
1063                                 0x00000005 /* EMC_TCLKSTOP */
1064                                 0x000000c7 /* EMC_TREFBW */
1065                                 0x00000006 /* EMC_QUSE_EXTRA */
1066                                 0x00000004 /* EMC_FBIO_CFG6 */
1067                                 0x00000000 /* EMC_ODT_WRITE */
1068                                 0x00000000 /* EMC_ODT_READ */
1069                                 0x00004288 /* EMC_FBIO_CFG5 */
1070                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1071                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1072                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1073                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1074                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1075                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1076                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1077                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1078                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1079                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1080                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1081                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1082                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1083                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1084                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1085                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1086                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1087                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1088                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1089                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1090                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1091                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1092                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1093                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1094                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1095                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1096                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1097                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1098                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1099                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1100                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1101                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1102                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1103                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1104                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1105                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1106                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1107                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1108                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1109                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1110                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1111                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1112                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1113                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1114                                 0x00000000 /* EMC_CTT */
1115                                 0x00000000 /* EMC_CTT_DURATION */
1116                                 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
1117                                 0xe8000000 /* EMC_FBIO_SPARE */
1118                                 0xff00ff00 /* EMC_CFG_RSV */
1119                         >;
1120                 };
1121                 timing-51000000 {
1122                         clock-frequency = <51000000>;
1123                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1124                         nvidia,emc-mode-1 = <0x80100003>;
1125                         nvidia,emc-mode-2 = <0x80200008>;
1126                         nvidia,emc-mode-reset = <0x80001221>;
1127                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1128                         nvidia,emc-cfg-periodic-qrst;
1129                         nvidia,emc-cfg-dyn-self-ref;
1130                         nvidia,emc-configuration = <
1131                                 0x00000002 /* EMC_RC */
1132                                 0x0000000d /* EMC_RFC */
1133                                 0x00000001 /* EMC_RAS */
1134                                 0x00000000 /* EMC_RP */
1135                                 0x00000002 /* EMC_R2W */
1136                                 0x0000000a /* EMC_W2R */
1137                                 0x00000005 /* EMC_R2P */
1138                                 0x0000000b /* EMC_W2P */
1139                                 0x00000000 /* EMC_RD_RCD */
1140                                 0x00000000 /* EMC_WR_RCD */
1141                                 0x00000003 /* EMC_RRD */
1142                                 0x00000001 /* EMC_REXT */
1143                                 0x00000000 /* EMC_WEXT */
1144                                 0x00000005 /* EMC_WDV */
1145                                 0x00000005 /* EMC_QUSE */
1146                                 0x00000004 /* EMC_QRST */
1147                                 0x0000000a /* EMC_QSAFE */
1148                                 0x0000000b /* EMC_RDV */
1149                                 0x00000181 /* EMC_REFRESH */
1150                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1151                                 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
1152                                 0x00000002 /* EMC_PDEX2WR */
1153                                 0x00000002 /* EMC_PDEX2RD */
1154                                 0x00000001 /* EMC_PCHG2PDEN */
1155                                 0x00000000 /* EMC_ACT2PDEN */
1156                                 0x00000007 /* EMC_AR2PDEN */
1157                                 0x0000000f /* EMC_RW2PDEN */
1158                                 0x0000000e /* EMC_TXSR */
1159                                 0x0000000e /* EMC_TXSRDLL */
1160                                 0x00000004 /* EMC_TCKE */
1161                                 0x00000003 /* EMC_TFAW */
1162                                 0x00000000 /* EMC_TRPAB */
1163                                 0x00000004 /* EMC_TCLKSTABLE */
1164                                 0x00000005 /* EMC_TCLKSTOP */
1165                                 0x0000018e /* EMC_TREFBW */
1166                                 0x00000006 /* EMC_QUSE_EXTRA */
1167                                 0x00000004 /* EMC_FBIO_CFG6 */
1168                                 0x00000000 /* EMC_ODT_WRITE */
1169                                 0x00000000 /* EMC_ODT_READ */
1170                                 0x00004288 /* EMC_FBIO_CFG5 */
1171                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1172                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1173                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1174                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1175                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1176                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1177                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1178                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1179                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1180                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1181                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1182                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1183                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1184                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1185                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1186                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1187                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1188                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1189                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1190                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1191                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1192                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1193                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1194                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1195                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1196                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1197                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1198                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1199                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1200                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1201                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1202                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1203                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1204                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1205                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1206                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1207                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1208                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1209                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1210                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1211                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1212                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1213                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1214                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1215                                 0x00000000 /* EMC_CTT */
1216                                 0x00000000 /* EMC_CTT_DURATION */
1217                                 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
1218                                 0xe8000000 /* EMC_FBIO_SPARE */
1219                                 0xff00ff00 /* EMC_CFG_RSV */
1220                         >;
1221                 };
1222                 timing-102000000 {
1223                         clock-frequency = <102000000>;
1224                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1225                         nvidia,emc-mode-1 = <0x80100003>;
1226                         nvidia,emc-mode-2 = <0x80200008>;
1227                         nvidia,emc-mode-reset = <0x80001221>;
1228                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1229                         nvidia,emc-cfg-periodic-qrst;
1230                         nvidia,emc-cfg-dyn-self-ref;
1231                         nvidia,emc-configuration = <
1232                                 0x00000004 /* EMC_RC */
1233                                 0x0000001a /* EMC_RFC */
1234                                 0x00000003 /* EMC_RAS */
1235                                 0x00000001 /* EMC_RP */
1236                                 0x00000002 /* EMC_R2W */
1237                                 0x0000000a /* EMC_W2R */
1238                                 0x00000005 /* EMC_R2P */
1239                                 0x0000000b /* EMC_W2P */
1240                                 0x00000001 /* EMC_RD_RCD */
1241                                 0x00000001 /* EMC_WR_RCD */
1242                                 0x00000003 /* EMC_RRD */
1243                                 0x00000001 /* EMC_REXT */
1244                                 0x00000000 /* EMC_WEXT */
1245                                 0x00000005 /* EMC_WDV */
1246                                 0x00000005 /* EMC_QUSE */
1247                                 0x00000004 /* EMC_QRST */
1248                                 0x0000000a /* EMC_QSAFE */
1249                                 0x0000000b /* EMC_RDV */
1250                                 0x00000303 /* EMC_REFRESH */
1251                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1252                                 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
1253                                 0x00000002 /* EMC_PDEX2WR */
1254                                 0x00000002 /* EMC_PDEX2RD */
1255                                 0x00000001 /* EMC_PCHG2PDEN */
1256                                 0x00000000 /* EMC_ACT2PDEN */
1257                                 0x00000007 /* EMC_AR2PDEN */
1258                                 0x0000000f /* EMC_RW2PDEN */
1259                                 0x0000001c /* EMC_TXSR */
1260                                 0x0000001c /* EMC_TXSRDLL */
1261                                 0x00000004 /* EMC_TCKE */
1262                                 0x00000005 /* EMC_TFAW */
1263                                 0x00000000 /* EMC_TRPAB */
1264                                 0x00000004 /* EMC_TCLKSTABLE */
1265                                 0x00000005 /* EMC_TCLKSTOP */
1266                                 0x0000031c /* EMC_TREFBW */
1267                                 0x00000006 /* EMC_QUSE_EXTRA */
1268                                 0x00000004 /* EMC_FBIO_CFG6 */
1269                                 0x00000000 /* EMC_ODT_WRITE */
1270                                 0x00000000 /* EMC_ODT_READ */
1271                                 0x00004288 /* EMC_FBIO_CFG5 */
1272                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1273                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1274                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1275                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1276                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1277                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1278                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1279                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1280                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1281                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1282                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1283                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1284                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1285                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1286                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1287                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1288                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1289                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1290                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1291                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1292                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1293                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1294                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1295                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1296                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1297                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1298                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1299                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1300                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1301                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1302                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1303                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1304                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1305                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1306                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1307                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1308                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1309                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1310                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1311                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1312                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1313                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1314                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1315                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1316                                 0x00000000 /* EMC_CTT */
1317                                 0x00000000 /* EMC_CTT_DURATION */
1318                                 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
1319                                 0xe8000000 /* EMC_FBIO_SPARE */
1320                                 0xff00ff00 /* EMC_CFG_RSV */
1321                         >;
1322                 };
1323                 timing-204000000 {
1324                         clock-frequency = <204000000>;
1325                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1326                         nvidia,emc-mode-1 = <0x80100003>;
1327                         nvidia,emc-mode-2 = <0x80200008>;
1328                         nvidia,emc-mode-reset = <0x80001221>;
1329                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1330                         nvidia,emc-cfg-periodic-qrst;
1331                         nvidia,emc-cfg-dyn-self-ref;
1332                         nvidia,emc-configuration = <
1333                                 0x00000009 /* EMC_RC */
1334                                 0x00000035 /* EMC_RFC */
1335                                 0x00000007 /* EMC_RAS */
1336                                 0x00000002 /* EMC_RP */
1337                                 0x00000002 /* EMC_R2W */
1338                                 0x0000000a /* EMC_W2R */
1339                                 0x00000005 /* EMC_R2P */
1340                                 0x0000000b /* EMC_W2P */
1341                                 0x00000002 /* EMC_RD_RCD */
1342                                 0x00000002 /* EMC_WR_RCD */
1343                                 0x00000003 /* EMC_RRD */
1344                                 0x00000001 /* EMC_REXT */
1345                                 0x00000000 /* EMC_WEXT */
1346                                 0x00000005 /* EMC_WDV */
1347                                 0x00000005 /* EMC_QUSE */
1348                                 0x00000004 /* EMC_QRST */
1349                                 0x0000000a /* EMC_QSAFE */
1350                                 0x0000000b /* EMC_RDV */
1351                                 0x00000607 /* EMC_REFRESH */
1352                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1353                                 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
1354                                 0x00000002 /* EMC_PDEX2WR */
1355                                 0x00000002 /* EMC_PDEX2RD */
1356                                 0x00000001 /* EMC_PCHG2PDEN */
1357                                 0x00000000 /* EMC_ACT2PDEN */
1358                                 0x00000007 /* EMC_AR2PDEN */
1359                                 0x0000000f /* EMC_RW2PDEN */
1360                                 0x00000038 /* EMC_TXSR */
1361                                 0x00000038 /* EMC_TXSRDLL */
1362                                 0x00000004 /* EMC_TCKE */
1363                                 0x00000009 /* EMC_TFAW */
1364                                 0x00000000 /* EMC_TRPAB */
1365                                 0x00000004 /* EMC_TCLKSTABLE */
1366                                 0x00000005 /* EMC_TCLKSTOP */
1367                                 0x00000638 /* EMC_TREFBW */
1368                                 0x00000006 /* EMC_QUSE_EXTRA */
1369                                 0x00000006 /* EMC_FBIO_CFG6 */
1370                                 0x00000000 /* EMC_ODT_WRITE */
1371                                 0x00000000 /* EMC_ODT_READ */
1372                                 0x00004288 /* EMC_FBIO_CFG5 */
1373                                 0x004400a4 /* EMC_CFG_DIG_DLL */
1374                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1375                                 0x00080000 /* EMC_DLL_XFORM_DQS0 */
1376                                 0x00080000 /* EMC_DLL_XFORM_DQS1 */
1377                                 0x00080000 /* EMC_DLL_XFORM_DQS2 */
1378                                 0x00080000 /* EMC_DLL_XFORM_DQS3 */
1379                                 0x00080000 /* EMC_DLL_XFORM_DQS4 */
1380                                 0x00080000 /* EMC_DLL_XFORM_DQS5 */
1381                                 0x00080000 /* EMC_DLL_XFORM_DQS6 */
1382                                 0x00080000 /* EMC_DLL_XFORM_DQS7 */
1383                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1384                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1385                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1386                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1387                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1388                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1389                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1390                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1391                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1392                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1393                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1394                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1395                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1396                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1397                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1398                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1399                                 0x00080000 /* EMC_DLL_XFORM_DQ0 */
1400                                 0x00080000 /* EMC_DLL_XFORM_DQ1 */
1401                                 0x00080000 /* EMC_DLL_XFORM_DQ2 */
1402                                 0x00080000 /* EMC_DLL_XFORM_DQ3 */
1403                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1404                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1405                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1406                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1407                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1408                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1409                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1410                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1411                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1412                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1413                                 0x00020000 /* EMC_ZCAL_INTERVAL */
1414                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
1415                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1416                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1417                                 0x00000000 /* EMC_CTT */
1418                                 0x00000000 /* EMC_CTT_DURATION */
1419                                 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
1420                                 0xe8000000 /* EMC_FBIO_SPARE */
1421                                 0xff00ff00 /* EMC_CFG_RSV */
1422                         >;
1423                 };
1424                 timing-400000000 {
1425                         clock-frequency = <400000000>;
1426                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1427                         nvidia,emc-mode-1 = <0x80100002>;
1428                         nvidia,emc-mode-2 = <0x80200000>;
1429                         nvidia,emc-mode-reset = <0x80000521>;
1430                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1431                         nvidia,emc-configuration = <
1432                                 0x00000012 /* EMC_RC */
1433                                 0x00000066 /* EMC_RFC */
1434                                 0x0000000c /* EMC_RAS */
1435                                 0x00000004 /* EMC_RP */
1436                                 0x00000003 /* EMC_R2W */
1437                                 0x00000008 /* EMC_W2R */
1438                                 0x00000002 /* EMC_R2P */
1439                                 0x0000000a /* EMC_W2P */
1440                                 0x00000004 /* EMC_RD_RCD */
1441                                 0x00000004 /* EMC_WR_RCD */
1442                                 0x00000002 /* EMC_RRD */
1443                                 0x00000001 /* EMC_REXT */
1444                                 0x00000000 /* EMC_WEXT */
1445                                 0x00000004 /* EMC_WDV */
1446                                 0x00000006 /* EMC_QUSE */
1447                                 0x00000004 /* EMC_QRST */
1448                                 0x0000000a /* EMC_QSAFE */
1449                                 0x0000000c /* EMC_RDV */
1450                                 0x00000bf0 /* EMC_REFRESH */
1451                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1452                                 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
1453                                 0x00000001 /* EMC_PDEX2WR */
1454                                 0x00000008 /* EMC_PDEX2RD */
1455                                 0x00000001 /* EMC_PCHG2PDEN */
1456                                 0x00000000 /* EMC_ACT2PDEN */
1457                                 0x00000008 /* EMC_AR2PDEN */
1458                                 0x0000000f /* EMC_RW2PDEN */
1459                                 0x0000006c /* EMC_TXSR */
1460                                 0x00000200 /* EMC_TXSRDLL */
1461                                 0x00000004 /* EMC_TCKE */
1462                                 0x00000010 /* EMC_TFAW */
1463                                 0x00000000 /* EMC_TRPAB */
1464                                 0x00000004 /* EMC_TCLKSTABLE */
1465                                 0x00000005 /* EMC_TCLKSTOP */
1466                                 0x00000c30 /* EMC_TREFBW */
1467                                 0x00000000 /* EMC_QUSE_EXTRA */
1468                                 0x00000004 /* EMC_FBIO_CFG6 */
1469                                 0x00000000 /* EMC_ODT_WRITE */
1470                                 0x00000000 /* EMC_ODT_READ */
1471                                 0x00007088 /* EMC_FBIO_CFG5 */
1472                                 0x001d0084 /* EMC_CFG_DIG_DLL */
1473                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1474                                 0x0003c000 /* EMC_DLL_XFORM_DQS0 */
1475                                 0x0003c000 /* EMC_DLL_XFORM_DQS1 */
1476                                 0x0003c000 /* EMC_DLL_XFORM_DQS2 */
1477                                 0x0003c000 /* EMC_DLL_XFORM_DQS3 */
1478                                 0x0003c000 /* EMC_DLL_XFORM_DQS4 */
1479                                 0x0003c000 /* EMC_DLL_XFORM_DQS5 */
1480                                 0x0003c000 /* EMC_DLL_XFORM_DQS6 */
1481                                 0x0003c000 /* EMC_DLL_XFORM_DQS7 */
1482                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1483                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1484                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1485                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1486                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1487                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1488                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1489                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1490                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1491                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1492                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1493                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1494                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1495                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1496                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1497                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1498                                 0x00048000 /* EMC_DLL_XFORM_DQ0 */
1499                                 0x00048000 /* EMC_DLL_XFORM_DQ1 */
1500                                 0x00048000 /* EMC_DLL_XFORM_DQ2 */
1501                                 0x00048000 /* EMC_DLL_XFORM_DQ3 */
1502                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1503                                 0x0800013d /* EMC_XM2DQSPADCTRL2 */
1504                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1505                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1506                                 0x01f1f508 /* EMC_XM2COMPPADCTRL */
1507                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1508                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1509                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
1510                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
1511                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1512                                 0x00020000 /* EMC_ZCAL_INTERVAL */
1513                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
1514                                 0x0158000c /* EMC_MRS_WAIT_CNT */
1515                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1516                                 0x00000000 /* EMC_CTT */
1517                                 0x00000000 /* EMC_CTT_DURATION */
1518                                 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
1519                                 0xe8000000 /* EMC_FBIO_SPARE */
1520                                 0xff00ff89 /* EMC_CFG_RSV */
1521                         >;
1522                 };
1523                 timing-800000000 {
1524                         clock-frequency = <800000000>;
1525                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1526                         nvidia,emc-mode-1 = <0x80100002>;
1527                         nvidia,emc-mode-2 = <0x80200018>;
1528                         nvidia,emc-mode-reset = <0x80000d71>;
1529                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1530                         nvidia,emc-cfg-periodic-qrst;
1531                         nvidia,emc-configuration = <
1532                                 0x00000025 /* EMC_RC */
1533                                 0x000000ce /* EMC_RFC */
1534                                 0x0000001a /* EMC_RAS */
1535                                 0x00000009 /* EMC_RP */
1536                                 0x00000005 /* EMC_R2W */
1537                                 0x0000000d /* EMC_W2R */
1538                                 0x00000004 /* EMC_R2P */
1539                                 0x00000013 /* EMC_W2P */
1540                                 0x00000009 /* EMC_RD_RCD */
1541                                 0x00000009 /* EMC_WR_RCD */
1542                                 0x00000004 /* EMC_RRD */
1543                                 0x00000001 /* EMC_REXT */
1544                                 0x00000000 /* EMC_WEXT */
1545                                 0x00000007 /* EMC_WDV */
1546                                 0x0000000a /* EMC_QUSE */
1547                                 0x00000009 /* EMC_QRST */
1548                                 0x0000000b /* EMC_QSAFE */
1549                                 0x00000011 /* EMC_RDV */
1550                                 0x00001820 /* EMC_REFRESH */
1551                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1552                                 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
1553                                 0x00000003 /* EMC_PDEX2WR */
1554                                 0x00000012 /* EMC_PDEX2RD */
1555                                 0x00000001 /* EMC_PCHG2PDEN */
1556                                 0x00000000 /* EMC_ACT2PDEN */
1557                                 0x0000000f /* EMC_AR2PDEN */
1558                                 0x00000018 /* EMC_RW2PDEN */
1559                                 0x000000d8 /* EMC_TXSR */
1560                                 0x00000200 /* EMC_TXSRDLL */
1561                                 0x00000005 /* EMC_TCKE */
1562                                 0x00000020 /* EMC_TFAW */
1563                                 0x00000000 /* EMC_TRPAB */
1564                                 0x00000007 /* EMC_TCLKSTABLE */
1565                                 0x00000008 /* EMC_TCLKSTOP */
1566                                 0x00001860 /* EMC_TREFBW */
1567                                 0x0000000b /* EMC_QUSE_EXTRA */
1568                                 0x00000006 /* EMC_FBIO_CFG6 */
1569                                 0x00000000 /* EMC_ODT_WRITE */
1570                                 0x00000000 /* EMC_ODT_READ */
1571                                 0x00005088 /* EMC_FBIO_CFG5 */
1572                                 0xf0070191 /* EMC_CFG_DIG_DLL */
1573                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1574                                 0x0000800a /* EMC_DLL_XFORM_DQS0 */
1575                                 0x0000000a /* EMC_DLL_XFORM_DQS1 */
1576                                 0x0000000a /* EMC_DLL_XFORM_DQS2 */
1577                                 0x0000000a /* EMC_DLL_XFORM_DQS3 */
1578                                 0x0000000a /* EMC_DLL_XFORM_DQS4 */
1579                                 0x0000000a /* EMC_DLL_XFORM_DQS5 */
1580                                 0x0000000a /* EMC_DLL_XFORM_DQS6 */
1581                                 0x0000000a /* EMC_DLL_XFORM_DQS7 */
1582                                 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
1583                                 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
1584                                 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
1585                                 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
1586                                 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
1587                                 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
1588                                 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
1589                                 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
1590                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1591                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1592                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1593                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1594                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1595                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1596                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1597                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1598                                 0x0000000a /* EMC_DLL_XFORM_DQ0 */
1599                                 0x0000000a /* EMC_DLL_XFORM_DQ1 */
1600                                 0x0000000a /* EMC_DLL_XFORM_DQ2 */
1601                                 0x0000000a /* EMC_DLL_XFORM_DQ3 */
1602                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1603                                 0x0600013d /* EMC_XM2DQSPADCTRL2 */
1604                                 0x22220000 /* EMC_XM2DQPADCTRL2 */
1605                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1606                                 0x01f1f501 /* EMC_XM2COMPPADCTRL */
1607                                 0x07077404 /* EMC_XM2VTTGENPADCTRL */
1608                                 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
1609                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
1610                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
1611                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1612                                 0x00020000 /* EMC_ZCAL_INTERVAL */
1613                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
1614                                 0x00f0000c /* EMC_MRS_WAIT_CNT */
1615                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1616                                 0x00000000 /* EMC_CTT */
1617                                 0x00000000 /* EMC_CTT_DURATION */
1618                                 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
1619                                 0xe8000000 /* EMC_FBIO_SPARE */
1620                                 0xff00ff49 /* EMC_CFG_RSV */
1621                         >;
1622                 };
1623         };
1624         emc-timings-1 {
1625                 nvidia,ram-code = <1>;  /* Hynix M RAM */
1626                 timing-25500000 {
1627                         clock-frequency = <25500000>;
1628                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1629                         nvidia,emc-mode-1 = <0x80100003>;
1630                         nvidia,emc-mode-2 = <0x80200008>;
1631                         nvidia,emc-mode-reset = <0x80001221>;
1632                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1633                         nvidia,emc-cfg-periodic-qrst;
1634                         nvidia,emc-cfg-dyn-self-ref;
1635                         nvidia,emc-configuration = <
1636                                 0x00000001 /* EMC_RC */
1637                                 0x00000006 /* EMC_RFC */
1638                                 0x00000000 /* EMC_RAS */
1639                                 0x00000000 /* EMC_RP */
1640                                 0x00000002 /* EMC_R2W */
1641                                 0x0000000a /* EMC_W2R */
1642                                 0x00000005 /* EMC_R2P */
1643                                 0x0000000b /* EMC_W2P */
1644                                 0x00000000 /* EMC_RD_RCD */
1645                                 0x00000000 /* EMC_WR_RCD */
1646                                 0x00000003 /* EMC_RRD */
1647                                 0x00000001 /* EMC_REXT */
1648                                 0x00000000 /* EMC_WEXT */
1649                                 0x00000005 /* EMC_WDV */
1650                                 0x00000005 /* EMC_QUSE */
1651                                 0x00000004 /* EMC_QRST */
1652                                 0x0000000a /* EMC_QSAFE */
1653                                 0x0000000b /* EMC_RDV */
1654                                 0x000000c0 /* EMC_REFRESH */
1655                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1656                                 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
1657                                 0x00000002 /* EMC_PDEX2WR */
1658                                 0x00000002 /* EMC_PDEX2RD */
1659                                 0x00000001 /* EMC_PCHG2PDEN */
1660                                 0x00000000 /* EMC_ACT2PDEN */
1661                                 0x00000007 /* EMC_AR2PDEN */
1662                                 0x0000000f /* EMC_RW2PDEN */
1663                                 0x00000007 /* EMC_TXSR */
1664                                 0x00000007 /* EMC_TXSRDLL */
1665                                 0x00000004 /* EMC_TCKE */
1666                                 0x00000002 /* EMC_TFAW */
1667                                 0x00000000 /* EMC_TRPAB */
1668                                 0x00000004 /* EMC_TCLKSTABLE */
1669                                 0x00000005 /* EMC_TCLKSTOP */
1670                                 0x000000c7 /* EMC_TREFBW */
1671                                 0x00000006 /* EMC_QUSE_EXTRA */
1672                                 0x00000004 /* EMC_FBIO_CFG6 */
1673                                 0x00000000 /* EMC_ODT_WRITE */
1674                                 0x00000000 /* EMC_ODT_READ */
1675                                 0x00004288 /* EMC_FBIO_CFG5 */
1676                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1677                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1678                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1679                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1680                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1681                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1682                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1683                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1684                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1685                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1686                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1687                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1688                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1689                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1690                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1691                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1692                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1693                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1694                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1695                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1696                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1697                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1698                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1699                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1700                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1701                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1702                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1703                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1704                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1705                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1706                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1707                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1708                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1709                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1710                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1711                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1712                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1713                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1714                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1715                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1716                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1717                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1718                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1719                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1720                                 0x00000000 /* EMC_CTT */
1721                                 0x00000000 /* EMC_CTT_DURATION */
1722                                 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
1723                                 0xe8000000 /* EMC_FBIO_SPARE */
1724                                 0xff00ff00 /* EMC_CFG_RSV */
1725                         >;
1726                 };
1727                 timing-51000000 {
1728                         clock-frequency = <51000000>;
1729                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1730                         nvidia,emc-mode-1 = <0x80100003>;
1731                         nvidia,emc-mode-2 = <0x80200008>;
1732                         nvidia,emc-mode-reset = <0x80001221>;
1733                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1734                         nvidia,emc-cfg-periodic-qrst;
1735                         nvidia,emc-cfg-dyn-self-ref;
1736                         nvidia,emc-configuration = <
1737                                 0x00000002 /* EMC_RC */
1738                                 0x0000000d /* EMC_RFC */
1739                                 0x00000001 /* EMC_RAS */
1740                                 0x00000000 /* EMC_RP */
1741                                 0x00000002 /* EMC_R2W */
1742                                 0x0000000a /* EMC_W2R */
1743                                 0x00000005 /* EMC_R2P */
1744                                 0x0000000b /* EMC_W2P */
1745                                 0x00000000 /* EMC_RD_RCD */
1746                                 0x00000000 /* EMC_WR_RCD */
1747                                 0x00000003 /* EMC_RRD */
1748                                 0x00000001 /* EMC_REXT */
1749                                 0x00000000 /* EMC_WEXT */
1750                                 0x00000005 /* EMC_WDV */
1751                                 0x00000005 /* EMC_QUSE */
1752                                 0x00000004 /* EMC_QRST */
1753                                 0x0000000a /* EMC_QSAFE */
1754                                 0x0000000b /* EMC_RDV */
1755                                 0x00000181 /* EMC_REFRESH */
1756                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1757                                 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
1758                                 0x00000002 /* EMC_PDEX2WR */
1759                                 0x00000002 /* EMC_PDEX2RD */
1760                                 0x00000001 /* EMC_PCHG2PDEN */
1761                                 0x00000000 /* EMC_ACT2PDEN */
1762                                 0x00000007 /* EMC_AR2PDEN */
1763                                 0x0000000f /* EMC_RW2PDEN */
1764                                 0x0000000e /* EMC_TXSR */
1765                                 0x0000000e /* EMC_TXSRDLL */
1766                                 0x00000004 /* EMC_TCKE */
1767                                 0x00000003 /* EMC_TFAW */
1768                                 0x00000000 /* EMC_TRPAB */
1769                                 0x00000004 /* EMC_TCLKSTABLE */
1770                                 0x00000005 /* EMC_TCLKSTOP */
1771                                 0x0000018e /* EMC_TREFBW */
1772                                 0x00000006 /* EMC_QUSE_EXTRA */
1773                                 0x00000004 /* EMC_FBIO_CFG6 */
1774                                 0x00000000 /* EMC_ODT_WRITE */
1775                                 0x00000000 /* EMC_ODT_READ */
1776                                 0x00004288 /* EMC_FBIO_CFG5 */
1777                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1778                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1779                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1780                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1781                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1782                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1783                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1784                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1785                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1786                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1787                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1788                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1789                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1790                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1791                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1792                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1793                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1794                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1795                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1796                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1797                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1798                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1799                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1800                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1801                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1802                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1803                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1804                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1805                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1806                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1807                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1808                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1809                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1810                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1811                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1812                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1813                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1814                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1815                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1816                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1817                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1818                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1819                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1820                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1821                                 0x00000000 /* EMC_CTT */
1822                                 0x00000000 /* EMC_CTT_DURATION */
1823                                 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
1824                                 0xe8000000 /* EMC_FBIO_SPARE */
1825                                 0xff00ff00 /* EMC_CFG_RSV */
1826                         >;
1827                 };
1828                 timing-102000000 {
1829                         clock-frequency = <102000000>;
1830                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1831                         nvidia,emc-mode-1 = <0x80100003>;
1832                         nvidia,emc-mode-2 = <0x80200008>;
1833                         nvidia,emc-mode-reset = <0x80001221>;
1834                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1835                         nvidia,emc-cfg-periodic-qrst;
1836                         nvidia,emc-cfg-dyn-self-ref;
1837                         nvidia,emc-configuration = <
1838                                 0x00000004 /* EMC_RC */
1839                                 0x0000001a /* EMC_RFC */
1840                                 0x00000003 /* EMC_RAS */
1841                                 0x00000001 /* EMC_RP */
1842                                 0x00000002 /* EMC_R2W */
1843                                 0x0000000a /* EMC_W2R */
1844                                 0x00000005 /* EMC_R2P */
1845                                 0x0000000b /* EMC_W2P */
1846                                 0x00000001 /* EMC_RD_RCD */
1847                                 0x00000001 /* EMC_WR_RCD */
1848                                 0x00000003 /* EMC_RRD */
1849                                 0x00000001 /* EMC_REXT */
1850                                 0x00000000 /* EMC_WEXT */
1851                                 0x00000005 /* EMC_WDV */
1852                                 0x00000005 /* EMC_QUSE */
1853                                 0x00000004 /* EMC_QRST */
1854                                 0x0000000a /* EMC_QSAFE */
1855                                 0x0000000b /* EMC_RDV */
1856                                 0x00000303 /* EMC_REFRESH */
1857                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1858                                 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
1859                                 0x00000002 /* EMC_PDEX2WR */
1860                                 0x00000002 /* EMC_PDEX2RD */
1861                                 0x00000001 /* EMC_PCHG2PDEN */
1862                                 0x00000000 /* EMC_ACT2PDEN */
1863                                 0x00000007 /* EMC_AR2PDEN */
1864                                 0x0000000f /* EMC_RW2PDEN */
1865                                 0x0000001c /* EMC_TXSR */
1866                                 0x0000001c /* EMC_TXSRDLL */
1867                                 0x00000004 /* EMC_TCKE */
1868                                 0x00000005 /* EMC_TFAW */
1869                                 0x00000000 /* EMC_TRPAB */
1870                                 0x00000004 /* EMC_TCLKSTABLE */
1871                                 0x00000005 /* EMC_TCLKSTOP */
1872                                 0x0000031c /* EMC_TREFBW */
1873                                 0x00000006 /* EMC_QUSE_EXTRA */
1874                                 0x00000004 /* EMC_FBIO_CFG6 */
1875                                 0x00000000 /* EMC_ODT_WRITE */
1876                                 0x00000000 /* EMC_ODT_READ */
1877                                 0x00004288 /* EMC_FBIO_CFG5 */
1878                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1879                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1880                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1881                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1882                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1883                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1884                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1885                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1886                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1887                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1888                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1889                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1890                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1891                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1892                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1893                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1894                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1895                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1896                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1897                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1898                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1899                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1900                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1901                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1902                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1903                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1904                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1905                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1906                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1907                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1908                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1909                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1910                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1911                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1912                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1913                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1914                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1915                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1916                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1917                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1918                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1919                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1920                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1921                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1922                                 0x00000000 /* EMC_CTT */
1923                                 0x00000000 /* EMC_CTT_DURATION */
1924                                 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
1925                                 0xe8000000 /* EMC_FBIO_SPARE */
1926                                 0xff00ff00 /* EMC_CFG_RSV */
1927                         >;
1928                 };
1929                 timing-204000000 {
1930                         clock-frequency = <204000000>;
1931                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1932                         nvidia,emc-mode-1 = <0x80100003>;
1933                         nvidia,emc-mode-2 = <0x80200008>;
1934                         nvidia,emc-mode-reset = <0x80001221>;
1935                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1936                         nvidia,emc-cfg-periodic-qrst;
1937                         nvidia,emc-cfg-dyn-self-ref;
1938                         nvidia,emc-configuration = <
1939                                 0x00000009 /* EMC_RC */
1940                                 0x00000035 /* EMC_RFC */
1941                                 0x00000007 /* EMC_RAS */
1942                                 0x00000002 /* EMC_RP */
1943                                 0x00000002 /* EMC_R2W */
1944                                 0x0000000a /* EMC_W2R */
1945                                 0x00000005 /* EMC_R2P */
1946                                 0x0000000b /* EMC_W2P */
1947                                 0x00000002 /* EMC_RD_RCD */
1948                                 0x00000002 /* EMC_WR_RCD */
1949                                 0x00000003 /* EMC_RRD */
1950                                 0x00000001 /* EMC_REXT */
1951                                 0x00000000 /* EMC_WEXT */
1952                                 0x00000005 /* EMC_WDV */
1953                                 0x00000005 /* EMC_QUSE */
1954                                 0x00000004 /* EMC_QRST */
1955                                 0x0000000a /* EMC_QSAFE */
1956                                 0x0000000b /* EMC_RDV */
1957                                 0x00000607 /* EMC_REFRESH */
1958                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1959                                 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
1960                                 0x00000002 /* EMC_PDEX2WR */
1961                                 0x00000002 /* EMC_PDEX2RD */
1962                                 0x00000001 /* EMC_PCHG2PDEN */
1963                                 0x00000000 /* EMC_ACT2PDEN */
1964                                 0x00000007 /* EMC_AR2PDEN */
1965                                 0x0000000f /* EMC_RW2PDEN */
1966                                 0x00000038 /* EMC_TXSR */
1967                                 0x00000038 /* EMC_TXSRDLL */
1968                                 0x00000004 /* EMC_TCKE */
1969                                 0x00000009 /* EMC_TFAW */
1970                                 0x00000000 /* EMC_TRPAB */
1971                                 0x00000004 /* EMC_TCLKSTABLE */
1972                                 0x00000005 /* EMC_TCLKSTOP */
1973                                 0x00000638 /* EMC_TREFBW */
1974                                 0x00000006 /* EMC_QUSE_EXTRA */
1975                                 0x00000006 /* EMC_FBIO_CFG6 */
1976                                 0x00000000 /* EMC_ODT_WRITE */
1977                                 0x00000000 /* EMC_ODT_READ */
1978                                 0x00004288 /* EMC_FBIO_CFG5 */
1979                                 0x004400a4 /* EMC_CFG_DIG_DLL */
1980                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1981                                 0x00080000 /* EMC_DLL_XFORM_DQS0 */
1982                                 0x00080000 /* EMC_DLL_XFORM_DQS1 */
1983                                 0x00080000 /* EMC_DLL_XFORM_DQS2 */
1984                                 0x00080000 /* EMC_DLL_XFORM_DQS3 */
1985                                 0x00080000 /* EMC_DLL_XFORM_DQS4 */
1986                                 0x00080000 /* EMC_DLL_XFORM_DQS5 */
1987                                 0x00080000 /* EMC_DLL_XFORM_DQS6 */
1988                                 0x00080000 /* EMC_DLL_XFORM_DQS7 */
1989                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1990                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1991                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1992                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1993                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1994                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1995                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1996                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1997                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1998                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1999                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2000                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2001                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2002                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2003                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2004                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2005                                 0x00080000 /* EMC_DLL_XFORM_DQ0 */
2006                                 0x00080000 /* EMC_DLL_XFORM_DQ1 */
2007                                 0x00080000 /* EMC_DLL_XFORM_DQ2 */
2008                                 0x00080000 /* EMC_DLL_XFORM_DQ3 */
2009                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2010                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2011                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2012                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2013                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2014                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2015                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2016                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2017                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2018                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2019                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2020                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2021                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2022                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2023                                 0x00000000 /* EMC_CTT */
2024                                 0x00000000 /* EMC_CTT_DURATION */
2025                                 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
2026                                 0xe8000000 /* EMC_FBIO_SPARE */
2027                                 0xff00ff00 /* EMC_CFG_RSV */
2028                         >;
2029                 };
2030                 timing-400000000 {
2031                         clock-frequency = <400000000>;
2032                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2033                         nvidia,emc-mode-1 = <0x80100002>;
2034                         nvidia,emc-mode-2 = <0x80200000>;
2035                         nvidia,emc-mode-reset = <0x80000521>;
2036                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2037                         nvidia,emc-configuration = <
2038                                 0x00000012 /* EMC_RC */
2039                                 0x00000066 /* EMC_RFC */
2040                                 0x0000000c /* EMC_RAS */
2041                                 0x00000004 /* EMC_RP */
2042                                 0x00000003 /* EMC_R2W */
2043                                 0x00000008 /* EMC_W2R */
2044                                 0x00000002 /* EMC_R2P */
2045                                 0x0000000a /* EMC_W2P */
2046                                 0x00000004 /* EMC_RD_RCD */
2047                                 0x00000004 /* EMC_WR_RCD */
2048                                 0x00000002 /* EMC_RRD */
2049                                 0x00000001 /* EMC_REXT */
2050                                 0x00000000 /* EMC_WEXT */
2051                                 0x00000004 /* EMC_WDV */
2052                                 0x00000006 /* EMC_QUSE */
2053                                 0x00000004 /* EMC_QRST */
2054                                 0x0000000a /* EMC_QSAFE */
2055                                 0x0000000c /* EMC_RDV */
2056                                 0x00000bf0 /* EMC_REFRESH */
2057                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2058                                 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
2059                                 0x00000001 /* EMC_PDEX2WR */
2060                                 0x00000008 /* EMC_PDEX2RD */
2061                                 0x00000001 /* EMC_PCHG2PDEN */
2062                                 0x00000000 /* EMC_ACT2PDEN */
2063                                 0x00000008 /* EMC_AR2PDEN */
2064                                 0x0000000f /* EMC_RW2PDEN */
2065                                 0x0000006c /* EMC_TXSR */
2066                                 0x00000200 /* EMC_TXSRDLL */
2067                                 0x00000004 /* EMC_TCKE */
2068                                 0x00000010 /* EMC_TFAW */
2069                                 0x00000000 /* EMC_TRPAB */
2070                                 0x00000004 /* EMC_TCLKSTABLE */
2071                                 0x00000005 /* EMC_TCLKSTOP */
2072                                 0x00000c30 /* EMC_TREFBW */
2073                                 0x00000000 /* EMC_QUSE_EXTRA */
2074                                 0x00000004 /* EMC_FBIO_CFG6 */
2075                                 0x00000000 /* EMC_ODT_WRITE */
2076                                 0x00000000 /* EMC_ODT_READ */
2077                                 0x00007088 /* EMC_FBIO_CFG5 */
2078                                 0x001d0084 /* EMC_CFG_DIG_DLL */
2079                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2080                                 0x0003c000 /* EMC_DLL_XFORM_DQS0 */
2081                                 0x0003c000 /* EMC_DLL_XFORM_DQS1 */
2082                                 0x0003c000 /* EMC_DLL_XFORM_DQS2 */
2083                                 0x0003c000 /* EMC_DLL_XFORM_DQS3 */
2084                                 0x0003c000 /* EMC_DLL_XFORM_DQS4 */
2085                                 0x0003c000 /* EMC_DLL_XFORM_DQS5 */
2086                                 0x0003c000 /* EMC_DLL_XFORM_DQS6 */
2087                                 0x0003c000 /* EMC_DLL_XFORM_DQS7 */
2088                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2089                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2090                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2091                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2092                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2093                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2094                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2095                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2096                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2097                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2098                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2099                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2100                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2101                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2102                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2103                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2104                                 0x00048000 /* EMC_DLL_XFORM_DQ0 */
2105                                 0x00048000 /* EMC_DLL_XFORM_DQ1 */
2106                                 0x00048000 /* EMC_DLL_XFORM_DQ2 */
2107                                 0x00048000 /* EMC_DLL_XFORM_DQ3 */
2108                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2109                                 0x0800013d /* EMC_XM2DQSPADCTRL2 */
2110                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2111                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2112                                 0x01f1f508 /* EMC_XM2COMPPADCTRL */
2113                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2114                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2115                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2116                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
2117                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2118                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2119                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2120                                 0x0158000c /* EMC_MRS_WAIT_CNT */
2121                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2122                                 0x00000000 /* EMC_CTT */
2123                                 0x00000000 /* EMC_CTT_DURATION */
2124                                 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
2125                                 0xe8000000 /* EMC_FBIO_SPARE */
2126                                 0xff00ff89 /* EMC_CFG_RSV */
2127                         >;
2128                 };
2129                 timing-800000000 {
2130                         clock-frequency = <800000000>;
2131                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2132                         nvidia,emc-mode-1 = <0x80100002>;
2133                         nvidia,emc-mode-2 = <0x80200018>;
2134                         nvidia,emc-mode-reset = <0x80000d71>;
2135                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2136                         nvidia,emc-cfg-periodic-qrst;
2137                         nvidia,emc-configuration = <
2138                                 0x00000025 /* EMC_RC */
2139                                 0x000000ce /* EMC_RFC */
2140                                 0x0000001a /* EMC_RAS */
2141                                 0x00000009 /* EMC_RP */
2142                                 0x00000005 /* EMC_R2W */
2143                                 0x0000000d /* EMC_W2R */
2144                                 0x00000004 /* EMC_R2P */
2145                                 0x00000013 /* EMC_W2P */
2146                                 0x00000009 /* EMC_RD_RCD */
2147                                 0x00000009 /* EMC_WR_RCD */
2148                                 0x00000004 /* EMC_RRD */
2149                                 0x00000001 /* EMC_REXT */
2150                                 0x00000000 /* EMC_WEXT */
2151                                 0x00000007 /* EMC_WDV */
2152                                 0x0000000a /* EMC_QUSE */
2153                                 0x00000009 /* EMC_QRST */
2154                                 0x0000000b /* EMC_QSAFE */
2155                                 0x00000011 /* EMC_RDV */
2156                                 0x00001820 /* EMC_REFRESH */
2157                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2158                                 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
2159                                 0x00000003 /* EMC_PDEX2WR */
2160                                 0x00000012 /* EMC_PDEX2RD */
2161                                 0x00000001 /* EMC_PCHG2PDEN */
2162                                 0x00000000 /* EMC_ACT2PDEN */
2163                                 0x0000000f /* EMC_AR2PDEN */
2164                                 0x00000018 /* EMC_RW2PDEN */
2165                                 0x000000d8 /* EMC_TXSR */
2166                                 0x00000200 /* EMC_TXSRDLL */
2167                                 0x00000005 /* EMC_TCKE */
2168                                 0x00000020 /* EMC_TFAW */
2169                                 0x00000000 /* EMC_TRPAB */
2170                                 0x00000007 /* EMC_TCLKSTABLE */
2171                                 0x00000008 /* EMC_TCLKSTOP */
2172                                 0x00001860 /* EMC_TREFBW */
2173                                 0x0000000b /* EMC_QUSE_EXTRA */
2174                                 0x00000006 /* EMC_FBIO_CFG6 */
2175                                 0x00000000 /* EMC_ODT_WRITE */
2176                                 0x00000000 /* EMC_ODT_READ */
2177                                 0x00005088 /* EMC_FBIO_CFG5 */
2178                                 0xf0070191 /* EMC_CFG_DIG_DLL */
2179                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2180                                 0x0000800a /* EMC_DLL_XFORM_DQS0 */
2181                                 0x0000000a /* EMC_DLL_XFORM_DQS1 */
2182                                 0x0000000a /* EMC_DLL_XFORM_DQS2 */
2183                                 0x0000000a /* EMC_DLL_XFORM_DQS3 */
2184                                 0x0000000a /* EMC_DLL_XFORM_DQS4 */
2185                                 0x0000000a /* EMC_DLL_XFORM_DQS5 */
2186                                 0x0000000a /* EMC_DLL_XFORM_DQS6 */
2187                                 0x0000000a /* EMC_DLL_XFORM_DQS7 */
2188                                 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
2189                                 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
2190                                 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
2191                                 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
2192                                 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
2193                                 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
2194                                 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
2195                                 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
2196                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2197                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2198                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2199                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2200                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2201                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2202                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2203                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2204                                 0x0000000a /* EMC_DLL_XFORM_DQ0 */
2205                                 0x0000000a /* EMC_DLL_XFORM_DQ1 */
2206                                 0x0000000a /* EMC_DLL_XFORM_DQ2 */
2207                                 0x0000000a /* EMC_DLL_XFORM_DQ3 */
2208                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2209                                 0x0600013d /* EMC_XM2DQSPADCTRL2 */
2210                                 0x22220000 /* EMC_XM2DQPADCTRL2 */
2211                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2212                                 0x01f1f501 /* EMC_XM2COMPPADCTRL */
2213                                 0x07077404 /* EMC_XM2VTTGENPADCTRL */
2214                                 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
2215                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2216                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
2217                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2218                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2219                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2220                                 0x00f0000c /* EMC_MRS_WAIT_CNT */
2221                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2222                                 0x00000000 /* EMC_CTT */
2223                                 0x00000000 /* EMC_CTT_DURATION */
2224                                 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
2225                                 0xe8000000 /* EMC_FBIO_SPARE */
2226                                 0xff00ff49 /* EMC_CFG_RSV */
2227                         >;
2228                 };
2229         };
2230         emc-timings-2 {
2231                 nvidia,ram-code = <2>;  /* Hynix A RAM */
2232                 timing-25500000 {
2233                         clock-frequency = <25500000>;
2234                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2235                         nvidia,emc-mode-1 = <0x80100003>;
2236                         nvidia,emc-mode-2 = <0x80200008>;
2237                         nvidia,emc-mode-reset = <0x80001221>;
2238                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2239                         nvidia,emc-cfg-periodic-qrst;
2240                         nvidia,emc-cfg-dyn-self-ref;
2241                         nvidia,emc-configuration = <
2242                                 0x00000001 /* EMC_RC */
2243                                 0x00000007 /* EMC_RFC */
2244                                 0x00000000 /* EMC_RAS */
2245                                 0x00000000 /* EMC_RP */
2246                                 0x00000002 /* EMC_R2W */
2247                                 0x0000000a /* EMC_W2R */
2248                                 0x00000005 /* EMC_R2P */
2249                                 0x0000000b /* EMC_W2P */
2250                                 0x00000000 /* EMC_RD_RCD */
2251                                 0x00000000 /* EMC_WR_RCD */
2252                                 0x00000003 /* EMC_RRD */
2253                                 0x00000001 /* EMC_REXT */
2254                                 0x00000000 /* EMC_WEXT */
2255                                 0x00000005 /* EMC_WDV */
2256                                 0x00000005 /* EMC_QUSE */
2257                                 0x00000004 /* EMC_QRST */
2258                                 0x0000000a /* EMC_QSAFE */
2259                                 0x0000000b /* EMC_RDV */
2260                                 0x000000c0 /* EMC_REFRESH */
2261                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2262                                 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
2263                                 0x00000002 /* EMC_PDEX2WR */
2264                                 0x00000002 /* EMC_PDEX2RD */
2265                                 0x00000001 /* EMC_PCHG2PDEN */
2266                                 0x00000000 /* EMC_ACT2PDEN */
2267                                 0x00000007 /* EMC_AR2PDEN */
2268                                 0x0000000f /* EMC_RW2PDEN */
2269                                 0x00000008 /* EMC_TXSR */
2270                                 0x00000008 /* EMC_TXSRDLL */
2271                                 0x00000004 /* EMC_TCKE */
2272                                 0x00000002 /* EMC_TFAW */
2273                                 0x00000000 /* EMC_TRPAB */
2274                                 0x00000004 /* EMC_TCLKSTABLE */
2275                                 0x00000005 /* EMC_TCLKSTOP */
2276                                 0x000000c7 /* EMC_TREFBW */
2277                                 0x00000006 /* EMC_QUSE_EXTRA */
2278                                 0x00000004 /* EMC_FBIO_CFG6 */
2279                                 0x00000000 /* EMC_ODT_WRITE */
2280                                 0x00000000 /* EMC_ODT_READ */
2281                                 0x00004288 /* EMC_FBIO_CFG5 */
2282                                 0x007800a4 /* EMC_CFG_DIG_DLL */
2283                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2284                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2285                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2286                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2287                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2288                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2289                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2290                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2291                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2292                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2293                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2294                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2295                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2296                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2297                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2298                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2299                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2300                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2301                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2302                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2303                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2304                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2305                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2306                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2307                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2308                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2309                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2310                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2311                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2312                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2313                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2314                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2315                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2316                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2317                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2318                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2319                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2320                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2321                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2322                                 0x00000000 /* EMC_ZCAL_INTERVAL */
2323                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
2324                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2325                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2326                                 0x00000000 /* EMC_CTT */
2327                                 0x00000000 /* EMC_CTT_DURATION */
2328                                 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
2329                                 0xe8000000 /* EMC_FBIO_SPARE */
2330                                 0xff00ff00 /* EMC_CFG_RSV */
2331                         >;
2332                 };
2333                 timing-51000000 {
2334                         clock-frequency = <51000000>;
2335                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2336                         nvidia,emc-mode-1 = <0x80100003>;
2337                         nvidia,emc-mode-2 = <0x80200008>;
2338                         nvidia,emc-mode-reset = <0x80001221>;
2339                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2340                         nvidia,emc-cfg-periodic-qrst;
2341                         nvidia,emc-cfg-dyn-self-ref;
2342                         nvidia,emc-configuration = <
2343                                 0x00000002 /* EMC_RC */
2344                                 0x0000000f /* EMC_RFC */
2345                                 0x00000001 /* EMC_RAS */
2346                                 0x00000000 /* EMC_RP */
2347                                 0x00000002 /* EMC_R2W */
2348                                 0x0000000a /* EMC_W2R */
2349                                 0x00000005 /* EMC_R2P */
2350                                 0x0000000b /* EMC_W2P */
2351                                 0x00000000 /* EMC_RD_RCD */
2352                                 0x00000000 /* EMC_WR_RCD */
2353                                 0x00000003 /* EMC_RRD */
2354                                 0x00000001 /* EMC_REXT */
2355                                 0x00000000 /* EMC_WEXT */
2356                                 0x00000005 /* EMC_WDV */
2357                                 0x00000005 /* EMC_QUSE */
2358                                 0x00000004 /* EMC_QRST */
2359                                 0x0000000a /* EMC_QSAFE */
2360                                 0x0000000b /* EMC_RDV */
2361                                 0x00000181 /* EMC_REFRESH */
2362                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2363                                 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
2364                                 0x00000002 /* EMC_PDEX2WR */
2365                                 0x00000002 /* EMC_PDEX2RD */
2366                                 0x00000001 /* EMC_PCHG2PDEN */
2367                                 0x00000000 /* EMC_ACT2PDEN */
2368                                 0x00000007 /* EMC_AR2PDEN */
2369                                 0x0000000f /* EMC_RW2PDEN */
2370                                 0x00000010 /* EMC_TXSR */
2371                                 0x00000010 /* EMC_TXSRDLL */
2372                                 0x00000004 /* EMC_TCKE */
2373                                 0x00000003 /* EMC_TFAW */
2374                                 0x00000000 /* EMC_TRPAB */
2375                                 0x00000004 /* EMC_TCLKSTABLE */
2376                                 0x00000005 /* EMC_TCLKSTOP */
2377                                 0x0000018e /* EMC_TREFBW */
2378                                 0x00000006 /* EMC_QUSE_EXTRA */
2379                                 0x00000004 /* EMC_FBIO_CFG6 */
2380                                 0x00000000 /* EMC_ODT_WRITE */
2381                                 0x00000000 /* EMC_ODT_READ */
2382                                 0x00004288 /* EMC_FBIO_CFG5 */
2383                                 0x007800a4 /* EMC_CFG_DIG_DLL */
2384                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2385                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2386                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2387                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2388                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2389                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2390                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2391                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2392                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2393                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2394                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2395                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2396                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2397                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2398                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2399                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2400                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2401                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2402                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2403                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2404                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2405                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2406                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2407                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2408                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2409                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2410                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2411                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2412                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2413                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2414                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2415                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2416                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2417                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2418                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2419                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2420                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2421                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2422                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2423                                 0x00000000 /* EMC_ZCAL_INTERVAL */
2424                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
2425                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2426                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2427                                 0x00000000 /* EMC_CTT */
2428                                 0x00000000 /* EMC_CTT_DURATION */
2429                                 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
2430                                 0xe8000000 /* EMC_FBIO_SPARE */
2431                                 0xff00ff00 /* EMC_CFG_RSV */
2432                         >;
2433                 };
2434                 timing-102000000 {
2435                         clock-frequency = <102000000>;
2436                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2437                         nvidia,emc-mode-1 = <0x80100003>;
2438                         nvidia,emc-mode-2 = <0x80200008>;
2439                         nvidia,emc-mode-reset = <0x80001221>;
2440                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2441                         nvidia,emc-cfg-periodic-qrst;
2442                         nvidia,emc-cfg-dyn-self-ref;
2443                         nvidia,emc-configuration = <
2444                                 0x00000004 /* EMC_RC */
2445                                 0x0000001e /* EMC_RFC */
2446                                 0x00000003 /* EMC_RAS */
2447                                 0x00000001 /* EMC_RP */
2448                                 0x00000002 /* EMC_R2W */
2449                                 0x0000000a /* EMC_W2R */
2450                                 0x00000005 /* EMC_R2P */
2451                                 0x0000000b /* EMC_W2P */
2452                                 0x00000001 /* EMC_RD_RCD */
2453                                 0x00000001 /* EMC_WR_RCD */
2454                                 0x00000003 /* EMC_RRD */
2455                                 0x00000001 /* EMC_REXT */
2456                                 0x00000000 /* EMC_WEXT */
2457                                 0x00000005 /* EMC_WDV */
2458                                 0x00000005 /* EMC_QUSE */
2459                                 0x00000004 /* EMC_QRST */
2460                                 0x0000000a /* EMC_QSAFE */
2461                                 0x0000000b /* EMC_RDV */
2462                                 0x00000303 /* EMC_REFRESH */
2463                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2464                                 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
2465                                 0x00000002 /* EMC_PDEX2WR */
2466                                 0x00000002 /* EMC_PDEX2RD */
2467                                 0x00000001 /* EMC_PCHG2PDEN */
2468                                 0x00000000 /* EMC_ACT2PDEN */
2469                                 0x00000007 /* EMC_AR2PDEN */
2470                                 0x0000000f /* EMC_RW2PDEN */
2471                                 0x00000020 /* EMC_TXSR */
2472                                 0x00000020 /* EMC_TXSRDLL */
2473                                 0x00000004 /* EMC_TCKE */
2474                                 0x00000005 /* EMC_TFAW */
2475                                 0x00000000 /* EMC_TRPAB */
2476                                 0x00000004 /* EMC_TCLKSTABLE */
2477                                 0x00000005 /* EMC_TCLKSTOP */
2478                                 0x0000031c /* EMC_TREFBW */
2479                                 0x00000006 /* EMC_QUSE_EXTRA */
2480                                 0x00000004 /* EMC_FBIO_CFG6 */
2481                                 0x00000000 /* EMC_ODT_WRITE */
2482                                 0x00000000 /* EMC_ODT_READ */
2483                                 0x00004288 /* EMC_FBIO_CFG5 */
2484                                 0x007800a4 /* EMC_CFG_DIG_DLL */
2485                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2486                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2487                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2488                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2489                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2490                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2491                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2492                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2493                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2494                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2495                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2496                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2497                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2498                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2499                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2500                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2501                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2502                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2503                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2504                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2505                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2506                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2507                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2508                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2509                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2510                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2511                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2512                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2513                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2514                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2515                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2516                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2517                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2518                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2519                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2520                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2521                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2522                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2523                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2524                                 0x00000000 /* EMC_ZCAL_INTERVAL */
2525                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
2526                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2527                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2528                                 0x00000000 /* EMC_CTT */
2529                                 0x00000000 /* EMC_CTT_DURATION */
2530                                 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
2531                                 0xe8000000 /* EMC_FBIO_SPARE */
2532                                 0xff00ff00 /* EMC_CFG_RSV */
2533                         >;
2534                 };
2535                 timing-204000000 {
2536                         clock-frequency = <204000000>;
2537                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2538                         nvidia,emc-mode-1 = <0x80100003>;
2539                         nvidia,emc-mode-2 = <0x80200008>;
2540                         nvidia,emc-mode-reset = <0x80001221>;
2541                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2542                         nvidia,emc-cfg-periodic-qrst;
2543                         nvidia,emc-cfg-dyn-self-ref;
2544                         nvidia,emc-configuration = <
2545                                 0x00000009 /* EMC_RC */
2546                                 0x0000003d /* EMC_RFC */
2547                                 0x00000007 /* EMC_RAS */
2548                                 0x00000002 /* EMC_RP */
2549                                 0x00000002 /* EMC_R2W */
2550                                 0x0000000a /* EMC_W2R */
2551                                 0x00000005 /* EMC_R2P */
2552                                 0x0000000b /* EMC_W2P */
2553                                 0x00000002 /* EMC_RD_RCD */
2554                                 0x00000002 /* EMC_WR_RCD */
2555                                 0x00000003 /* EMC_RRD */
2556                                 0x00000001 /* EMC_REXT */
2557                                 0x00000000 /* EMC_WEXT */
2558                                 0x00000005 /* EMC_WDV */
2559                                 0x00000005 /* EMC_QUSE */
2560                                 0x00000004 /* EMC_QRST */
2561                                 0x0000000a /* EMC_QSAFE */
2562                                 0x0000000b /* EMC_RDV */
2563                                 0x00000607 /* EMC_REFRESH */
2564                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2565                                 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
2566                                 0x00000002 /* EMC_PDEX2WR */
2567                                 0x00000002 /* EMC_PDEX2RD */
2568                                 0x00000001 /* EMC_PCHG2PDEN */
2569                                 0x00000000 /* EMC_ACT2PDEN */
2570                                 0x00000007 /* EMC_AR2PDEN */
2571                                 0x0000000f /* EMC_RW2PDEN */
2572                                 0x00000040 /* EMC_TXSR */
2573                                 0x00000040 /* EMC_TXSRDLL */
2574                                 0x00000004 /* EMC_TCKE */
2575                                 0x00000009 /* EMC_TFAW */
2576                                 0x00000000 /* EMC_TRPAB */
2577                                 0x00000004 /* EMC_TCLKSTABLE */
2578                                 0x00000005 /* EMC_TCLKSTOP */
2579                                 0x00000638 /* EMC_TREFBW */
2580                                 0x00000006 /* EMC_QUSE_EXTRA */
2581                                 0x00000006 /* EMC_FBIO_CFG6 */
2582                                 0x00000000 /* EMC_ODT_WRITE */
2583                                 0x00000000 /* EMC_ODT_READ */
2584                                 0x00004288 /* EMC_FBIO_CFG5 */
2585                                 0x004400a4 /* EMC_CFG_DIG_DLL */
2586                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2587                                 0x00080000 /* EMC_DLL_XFORM_DQS0 */
2588                                 0x00080000 /* EMC_DLL_XFORM_DQS1 */
2589                                 0x00080000 /* EMC_DLL_XFORM_DQS2 */
2590                                 0x00080000 /* EMC_DLL_XFORM_DQS3 */
2591                                 0x00080000 /* EMC_DLL_XFORM_DQS4 */
2592                                 0x00080000 /* EMC_DLL_XFORM_DQS5 */
2593                                 0x00080000 /* EMC_DLL_XFORM_DQS6 */
2594                                 0x00080000 /* EMC_DLL_XFORM_DQS7 */
2595                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2596                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2597                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2598                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2599                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2600                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2601                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2602                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2603                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2604                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2605                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2606                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2607                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2608                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2609                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2610                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2611                                 0x00080000 /* EMC_DLL_XFORM_DQ0 */
2612                                 0x00080000 /* EMC_DLL_XFORM_DQ1 */
2613                                 0x00080000 /* EMC_DLL_XFORM_DQ2 */
2614                                 0x00080000 /* EMC_DLL_XFORM_DQ3 */
2615                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2616                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2617                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2618                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2619                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2620                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2621                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2622                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2623                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2624                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2625                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2626                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2627                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2628                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2629                                 0x00000000 /* EMC_CTT */
2630                                 0x00000000 /* EMC_CTT_DURATION */
2631                                 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
2632                                 0xe8000000 /* EMC_FBIO_SPARE */
2633                                 0xff00ff00 /* EMC_CFG_RSV */
2634                         >;
2635                 };
2636                 timing-400000000 {
2637                         clock-frequency = <400000000>;
2638                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2639                         nvidia,emc-mode-1 = <0x80100002>;
2640                         nvidia,emc-mode-2 = <0x80200000>;
2641                         nvidia,emc-mode-reset = <0x80000521>;
2642                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2643                         nvidia,emc-configuration = <
2644                                 0x00000012 /* EMC_RC */
2645                                 0x00000076 /* EMC_RFC */
2646                                 0x0000000c /* EMC_RAS */
2647                                 0x00000004 /* EMC_RP */
2648                                 0x00000003 /* EMC_R2W */
2649                                 0x00000008 /* EMC_W2R */
2650                                 0x00000002 /* EMC_R2P */
2651                                 0x0000000a /* EMC_W2P */
2652                                 0x00000004 /* EMC_RD_RCD */
2653                                 0x00000004 /* EMC_WR_RCD */
2654                                 0x00000002 /* EMC_RRD */
2655                                 0x00000001 /* EMC_REXT */
2656                                 0x00000000 /* EMC_WEXT */
2657                                 0x00000004 /* EMC_WDV */
2658                                 0x00000006 /* EMC_QUSE */
2659                                 0x00000004 /* EMC_QRST */
2660                                 0x0000000a /* EMC_QSAFE */
2661                                 0x0000000c /* EMC_RDV */
2662                                 0x00000bf0 /* EMC_REFRESH */
2663                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2664                                 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
2665                                 0x00000001 /* EMC_PDEX2WR */
2666                                 0x00000008 /* EMC_PDEX2RD */
2667                                 0x00000001 /* EMC_PCHG2PDEN */
2668                                 0x00000000 /* EMC_ACT2PDEN */
2669                                 0x00000008 /* EMC_AR2PDEN */
2670                                 0x0000000f /* EMC_RW2PDEN */
2671                                 0x0000007c /* EMC_TXSR */
2672                                 0x00000200 /* EMC_TXSRDLL */
2673                                 0x00000004 /* EMC_TCKE */
2674                                 0x00000010 /* EMC_TFAW */
2675                                 0x00000000 /* EMC_TRPAB */
2676                                 0x00000004 /* EMC_TCLKSTABLE */
2677                                 0x00000005 /* EMC_TCLKSTOP */
2678                                 0x00000c30 /* EMC_TREFBW */
2679                                 0x00000000 /* EMC_QUSE_EXTRA */
2680                                 0x00000004 /* EMC_FBIO_CFG6 */
2681                                 0x00000000 /* EMC_ODT_WRITE */
2682                                 0x00000000 /* EMC_ODT_READ */
2683                                 0x00007088 /* EMC_FBIO_CFG5 */
2684                                 0x001d0084 /* EMC_CFG_DIG_DLL */
2685                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2686                                 0x00044000 /* EMC_DLL_XFORM_DQS0 */
2687                                 0x00044000 /* EMC_DLL_XFORM_DQS1 */
2688                                 0x00044000 /* EMC_DLL_XFORM_DQS2 */
2689                                 0x00044000 /* EMC_DLL_XFORM_DQS3 */
2690                                 0x00044000 /* EMC_DLL_XFORM_DQS4 */
2691                                 0x00044000 /* EMC_DLL_XFORM_DQS5 */
2692                                 0x00044000 /* EMC_DLL_XFORM_DQS6 */
2693                                 0x00044000 /* EMC_DLL_XFORM_DQS7 */
2694                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2695                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2696                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2697                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2698                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2699                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2700                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2701                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2702                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2703                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2704                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2705                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2706                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2707                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2708                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2709                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2710                                 0x00058000 /* EMC_DLL_XFORM_DQ0 */
2711                                 0x00058000 /* EMC_DLL_XFORM_DQ1 */
2712                                 0x00058000 /* EMC_DLL_XFORM_DQ2 */
2713                                 0x00058000 /* EMC_DLL_XFORM_DQ3 */
2714                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2715                                 0x0800013d /* EMC_XM2DQSPADCTRL2 */
2716                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2717                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2718                                 0x01f1f508 /* EMC_XM2COMPPADCTRL */
2719                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2720                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2721                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2722                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
2723                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2724                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2725                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2726                                 0x0148000c /* EMC_MRS_WAIT_CNT */
2727                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2728                                 0x00000000 /* EMC_CTT */
2729                                 0x00000000 /* EMC_CTT_DURATION */
2730                                 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
2731                                 0xe8000000 /* EMC_FBIO_SPARE */
2732                                 0xff00ff89 /* EMC_CFG_RSV */
2733                         >;
2734                 };
2735                 timing-800000000 {
2736                         clock-frequency = <800000000>;
2737                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2738                         nvidia,emc-mode-1 = <0x80100002>;
2739                         nvidia,emc-mode-2 = <0x80200018>;
2740                         nvidia,emc-mode-reset = <0x80000d71>;
2741                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2742                         nvidia,emc-cfg-periodic-qrst;
2743                         nvidia,emc-configuration = <
2744                                 0x00000025 /* EMC_RC */
2745                                 0x000000ee /* EMC_RFC */
2746                                 0x0000001a /* EMC_RAS */
2747                                 0x00000009 /* EMC_RP */
2748                                 0x00000005 /* EMC_R2W */
2749                                 0x0000000d /* EMC_W2R */
2750                                 0x00000004 /* EMC_R2P */
2751                                 0x00000013 /* EMC_W2P */
2752                                 0x00000009 /* EMC_RD_RCD */
2753                                 0x00000009 /* EMC_WR_RCD */
2754                                 0x00000003 /* EMC_RRD */
2755                                 0x00000001 /* EMC_REXT */
2756                                 0x00000000 /* EMC_WEXT */
2757                                 0x00000007 /* EMC_WDV */
2758                                 0x0000000a /* EMC_QUSE */
2759                                 0x00000009 /* EMC_QRST */
2760                                 0x0000000b /* EMC_QSAFE */
2761                                 0x00000011 /* EMC_RDV */
2762                                 0x00001820 /* EMC_REFRESH */
2763                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2764                                 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
2765                                 0x00000003 /* EMC_PDEX2WR */
2766                                 0x00000012 /* EMC_PDEX2RD */
2767                                 0x00000001 /* EMC_PCHG2PDEN */
2768                                 0x00000000 /* EMC_ACT2PDEN */
2769                                 0x0000000f /* EMC_AR2PDEN */
2770                                 0x00000018 /* EMC_RW2PDEN */
2771                                 0x000000f8 /* EMC_TXSR */
2772                                 0x00000200 /* EMC_TXSRDLL */
2773                                 0x00000005 /* EMC_TCKE */
2774                                 0x00000020 /* EMC_TFAW */
2775                                 0x00000000 /* EMC_TRPAB */
2776                                 0x00000007 /* EMC_TCLKSTABLE */
2777                                 0x00000008 /* EMC_TCLKSTOP */
2778                                 0x00001860 /* EMC_TREFBW */
2779                                 0x0000000b /* EMC_QUSE_EXTRA */
2780                                 0x00000006 /* EMC_FBIO_CFG6 */
2781                                 0x00000000 /* EMC_ODT_WRITE */
2782                                 0x00000000 /* EMC_ODT_READ */
2783                                 0x00005088 /* EMC_FBIO_CFG5 */
2784                                 0xf0070191 /* EMC_CFG_DIG_DLL */
2785                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2786                                 0x0000000c /* EMC_DLL_XFORM_DQS0 */
2787                                 0x007fc00a /* EMC_DLL_XFORM_DQS1 */
2788                                 0x00000008 /* EMC_DLL_XFORM_DQS2 */
2789                                 0x0000000a /* EMC_DLL_XFORM_DQS3 */
2790                                 0x0000000a /* EMC_DLL_XFORM_DQS4 */
2791                                 0x0000000a /* EMC_DLL_XFORM_DQS5 */
2792                                 0x0000000a /* EMC_DLL_XFORM_DQS6 */
2793                                 0x0000000a /* EMC_DLL_XFORM_DQS7 */
2794                                 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
2795                                 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
2796                                 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
2797                                 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
2798                                 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
2799                                 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
2800                                 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
2801                                 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
2802                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2803                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2804                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2805                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2806                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2807                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2808                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2809                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2810                                 0x0000000a /* EMC_DLL_XFORM_DQ0 */
2811                                 0x0000000c /* EMC_DLL_XFORM_DQ1 */
2812                                 0x0000000a /* EMC_DLL_XFORM_DQ2 */
2813                                 0x0000000a /* EMC_DLL_XFORM_DQ3 */
2814                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2815                                 0x0600013d /* EMC_XM2DQSPADCTRL2 */
2816                                 0x22220000 /* EMC_XM2DQPADCTRL2 */
2817                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2818                                 0x01f1f501 /* EMC_XM2COMPPADCTRL */
2819                                 0x07077404 /* EMC_XM2VTTGENPADCTRL */
2820                                 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
2821                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2822                                 0x0a000021 /* EMC_XM2DQSPADCTRL3 */
2823                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2824                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2825                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2826                                 0x00d0000c /* EMC_MRS_WAIT_CNT */
2827                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2828                                 0x00000000 /* EMC_CTT */
2829                                 0x00000000 /* EMC_CTT_DURATION */
2830                                 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
2831                                 0xe8000000 /* EMC_FBIO_SPARE */
2832                                 0xff00ff49 /* EMC_CFG_RSV */
2833                         >;
2834                 };
2835         };
2836 };
2837 &state_default {
2838         clk_32k_out_pa0 {
2839                 nvidia,pins = "clk_32k_out_pa0";
2840                 nvidia,function = "blink";
2841                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2842                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2843                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2844         };
2845         uart3_cts_n_pa1 {
2846                 nvidia,pins = "uart3_cts_n_pa1";
2847                 nvidia,function = "uartc";
2848                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2849                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2850                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2851         };
2852         dap2_fs_pa2 {
2853                 nvidia,pins = "dap2_fs_pa2";
2854                 nvidia,function = "i2s1";
2855                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2856                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2857                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2858         };
2859         dap2_sclk_pa3 {
2860                 nvidia,pins = "dap2_sclk_pa3";
2861                 nvidia,function = "i2s1";
2862                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2863                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2864                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2865         };
2866         dap2_din_pa4 {
2867                 nvidia,pins = "dap2_din_pa4";
2868                 nvidia,function = "i2s1";
2869                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2870                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2871                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2872         };
2873         dap2_dout_pa5 {
2874                 nvidia,pins = "dap2_dout_pa5";
2875                 nvidia,function = "i2s1";
2876                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2877                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2878                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2879         };
2880         sdmmc3_clk_pa6 {
2881                 nvidia,pins = "sdmmc3_clk_pa6";
2882                 nvidia,function = "sdmmc3";
2883                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2884                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2885                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2886         };
2887         sdmmc3_cmd_pa7 {
2888                 nvidia,pins = "sdmmc3_cmd_pa7";
2889                 nvidia,function = "sdmmc3";
2890                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2891                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2892                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2893         };
2894         gmi_a17_pb0 {
2895                 nvidia,pins = "gmi_a17_pb0";
2896                 nvidia,function = "spi4";
2897                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2898                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2899                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2900         };
2901         gmi_a18_pb1 {
2902                 nvidia,pins = "gmi_a18_pb1";
2903                 nvidia,function = "spi4";
2904                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2905                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2906                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2907         };
2908         lcd_pwr0_pb2 {
2909                 nvidia,pins = "lcd_pwr0_pb2";
2910                 nvidia,function = "displaya";
2911                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2912                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2913                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2914         };
2915         lcd_pclk_pb3 {
2916                 nvidia,pins = "lcd_pclk_pb3";
2917                 nvidia,function = "displaya";
2918                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2919                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2920                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2921         };
2922         sdmmc3_dat3_pb4 {
2923                 nvidia,pins = "sdmmc3_dat3_pb4";
2924                 nvidia,function = "sdmmc3";
2925                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2926                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2927                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2928         };
2929         sdmmc3_dat2_pb5 {
2930                 nvidia,pins = "sdmmc3_dat2_pb5";
2931                 nvidia,function = "sdmmc3";
2932                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2933                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2934                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2935         };
2936         sdmmc3_dat1_pb6 {
2937                 nvidia,pins = "sdmmc3_dat1_pb6";
2938                 nvidia,function = "sdmmc3";
2939                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2940                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2941                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2942         };
2943         sdmmc3_dat0_pb7 {
2944                 nvidia,pins = "sdmmc3_dat0_pb7";
2945                 nvidia,function = "sdmmc3";
2946                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2947                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2948                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2949         };
2950         uart3_rts_n_pc0 {
2951                 nvidia,pins = "uart3_rts_n_pc0";
2952                 nvidia,function = "uartc";
2953                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2954                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2955                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2956         };
2957         lcd_pwr1_pc1 {
2958                 nvidia,pins = "lcd_pwr1_pc1";
2959                 nvidia,function = "displaya";
2960                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2961                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2962                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2963         };
2964         uart2_txd_pc2 {
2965                 nvidia,pins = "uart2_txd_pc2";
2966                 nvidia,function = "uartb";
2967                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2968                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2969                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2970         };
2971         uart2_rxd_pc3 {
2972                 nvidia,pins = "uart2_rxd_pc3";
2973                 nvidia,function = "uartb";
2974                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2975                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2976                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2977         };
2978         gen1_i2c_scl_pc4 {
2979                 nvidia,pins = "gen1_i2c_scl_pc4";
2980                 nvidia,function = "i2c1";
2981                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2982                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2983                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2984                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2985         };
2986         gen1_i2c_sda_pc5 {
2987                 nvidia,pins = "gen1_i2c_sda_pc5";
2988                 nvidia,function = "i2c1";
2989                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2990                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2991                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2992                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2993         };
2994         lcd_pwr2_pc6 {
2995                 nvidia,pins = "lcd_pwr2_pc6";
2996                 nvidia,function = "displaya";
2997                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2998                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2999                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3000         };
3001         gmi_wp_n_pc7 {
3002                 nvidia,pins = "gmi_wp_n_pc7";
3003                 nvidia,function = "gmi";
3004                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3005                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3006                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3007         };
3008         sdmmc3_dat5_pd0 {
3009                 nvidia,pins = "sdmmc3_dat5_pd0";
3010                 nvidia,function = "sdmmc3";
3011                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3012                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3013                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3014         };
3015         sdmmc3_dat4_pd1 {
3016                 nvidia,pins = "sdmmc3_dat4_pd1";
3017                 nvidia,function = "sdmmc3";
3018                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3019                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3020                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3021         };
3022         lcd_dc1_pd2 {
3023                 nvidia,pins = "lcd_dc1_pd2";
3024                 nvidia,function = "displaya";
3025                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3026                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3027                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3028         };
3029         sdmmc3_dat6_pd3 {
3030                 nvidia,pins = "sdmmc3_dat6_pd3";
3031                 nvidia,function = "spi4";
3032                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3033                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3034                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3035         };
3036         sdmmc3_dat7_pd4 {
3037                 nvidia,pins = "sdmmc3_dat7_pd4";
3038                 nvidia,function = "spi4";
3039                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3040                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3041                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3042         };
3043         vi_d1_pd5 {
3044                 nvidia,pins = "vi_d1_pd5";
3045                 nvidia,function = "sdmmc2";
3046                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3047                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3048                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3049         };
3050         vi_vsync_pd6 {
3051                 nvidia,pins = "vi_vsync_pd6";
3052                 nvidia,function = "ddr";
3053                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3054                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3055                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3056         };
3057         vi_hsync_pd7 {
3058                 nvidia,pins = "vi_hsync_pd7";
3059                 nvidia,function = "ddr";
3060                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3061                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3062                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3063         };
3064         lcd_d0_pe0 {
3065                 nvidia,pins = "lcd_d0_pe0";
3066                 nvidia,function = "displaya";
3067                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3068                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3069                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3070         };
3071         lcd_d1_pe1 {
3072                 nvidia,pins = "lcd_d1_pe1";
3073                 nvidia,function = "displaya";
3074                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3075                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3076                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3077         };
3078         lcd_d2_pe2 {
3079                 nvidia,pins = "lcd_d2_pe2";
3080                 nvidia,function = "displaya";
3081                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3082                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3083                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3084         };
3085         lcd_d3_pe3 {
3086                 nvidia,pins = "lcd_d3_pe3";
3087                 nvidia,function = "displaya";
3088                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3089                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3090                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3091         };
3092         lcd_d4_pe4 {
3093                 nvidia,pins = "lcd_d4_pe4";
3094                 nvidia,function = "displaya";
3095                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3096                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3097                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3098         };
3099         lcd_d5_pe5 {
3100                 nvidia,pins = "lcd_d5_pe5";
3101                 nvidia,function = "displaya";
3102                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3103                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3104                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3105         };
3106         lcd_d6_pe6 {
3107                 nvidia,pins = "lcd_d6_pe6";
3108                 nvidia,function = "displaya";
3109                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3110                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3111                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3112         };
3113         lcd_d7_pe7 {
3114                 nvidia,pins = "lcd_d7_pe7";
3115                 nvidia,function = "displaya";
3116                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3117                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3118                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3119         };
3120         lcd_d8_pf0 {
3121                 nvidia,pins = "lcd_d8_pf0";
3122                 nvidia,function = "displaya";
3123                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3124                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3125                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3126         };
3127         lcd_d9_pf1 {
3128                 nvidia,pins = "lcd_d9_pf1";
3129                 nvidia,function = "displaya";
3130                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3131                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3132                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3133         };
3134         lcd_d10_pf2 {
3135                 nvidia,pins = "lcd_d10_pf2";
3136                 nvidia,function = "displaya";
3137                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3138                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3139                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3140         };
3141         lcd_d11_pf3 {
3142                 nvidia,pins = "lcd_d11_pf3";
3143                 nvidia,function = "displaya";
3144                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3145                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3146                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3147         };
3148         lcd_d12_pf4 {
3149                 nvidia,pins = "lcd_d12_pf4";
3150                 nvidia,function = "displaya";
3151                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3152                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3153                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3154         };
3155         lcd_d13_pf5 {
3156                 nvidia,pins = "lcd_d13_pf5";
3157                 nvidia,function = "displaya";
3158                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3159                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3160                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3161         };
3162         lcd_d14_pf6 {
3163                 nvidia,pins = "lcd_d14_pf6";
3164                 nvidia,function = "displaya";
3165                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3166                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3167                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3168         };
3169         lcd_d15_pf7 {
3170                 nvidia,pins = "lcd_d15_pf7";
3171                 nvidia,function = "displaya";
3172                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3173                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3174                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3175         };
3176         gmi_ad0_pg0 {
3177                 nvidia,pins = "gmi_ad0_pg0";
3178                 nvidia,function = "nand";
3179                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3180                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3181                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3182         };
3183         gmi_ad1_pg1 {
3184                 nvidia,pins = "gmi_ad1_pg1";
3185                 nvidia,function = "nand";
3186                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3187                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3188                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3189         };
3190         gmi_ad2_pg2 {
3191                 nvidia,pins = "gmi_ad2_pg2";
3192                 nvidia,function = "nand";
3193                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3194                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3195                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3196         };
3197         gmi_ad3_pg3 {
3198                 nvidia,pins = "gmi_ad3_pg3";
3199                 nvidia,function = "nand";
3200                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3201                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3202                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3203         };
3204         gmi_ad4_pg4 {
3205                 nvidia,pins = "gmi_ad4_pg4";
3206                 nvidia,function = "nand";
3207                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3208                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3209                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3210         };
3211         gmi_ad5_pg5 {
3212                 nvidia,pins = "gmi_ad5_pg5";
3213                 nvidia,function = "nand";
3214                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3215                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3216                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3217         };
3218         gmi_ad6_pg6 {
3219                 nvidia,pins = "gmi_ad6_pg6";
3220                 nvidia,function = "nand";
3221                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3222                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3223                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3224         };
3225         gmi_ad7_pg7 {
3226                 nvidia,pins = "gmi_ad7_pg7";
3227                 nvidia,function = "nand";
3228                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3229                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3230                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3231         };
3232         gmi_ad8_ph0 {
3233                 nvidia,pins = "gmi_ad8_ph0";
3234                 nvidia,function = "pwm0";
3235                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3236                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3237                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3238         };
3239         gmi_ad9_ph1 {
3240                 nvidia,pins = "gmi_ad9_ph1";
3241                 nvidia,function = "pwm1";
3242                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3243                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3244                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3245         };
3246         gmi_ad10_ph2 {
3247                 nvidia,pins = "gmi_ad10_ph2";
3248                 nvidia,function = "pwm2";
3249                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3250                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3251                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3252         };
3253         gmi_ad11_ph3 {
3254                 nvidia,pins = "gmi_ad11_ph3";
3255                 nvidia,function = "nand";
3256                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3257                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3258                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3259         };
3260         gmi_ad12_ph4 {
3261                 nvidia,pins = "gmi_ad12_ph4";
3262                 nvidia,function = "nand";
3263                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3264                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3265                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3266         };
3267         gmi_ad13_ph5 {
3268                 nvidia,pins = "gmi_ad13_ph5";
3269                 nvidia,function = "nand";
3270                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3271                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3272                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3273         };
3274         gmi_ad14_ph6 {
3275                 nvidia,pins = "gmi_ad14_ph6";
3276                 nvidia,function = "nand";
3277                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3278                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3279                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3280         };
3281         gmi_wr_n_pi0 {
3282                 nvidia,pins = "gmi_wr_n_pi0";
3283                 nvidia,function = "nand";
3284                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3285                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3286                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3287         };
3288         gmi_oe_n_pi1 {
3289                 nvidia,pins = "gmi_oe_n_pi1";
3290                 nvidia,function = "nand";
3291                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3292                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3293                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3294         };
3295         gmi_dqs_pi2 {
3296                 nvidia,pins = "gmi_dqs_pi2";
3297                 nvidia,function = "nand";
3298                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3299                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3300                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3301         };
3302         gmi_iordy_pi5 {
3303                 nvidia,pins = "gmi_iordy_pi5";
3304                 nvidia,function = "rsvd1";
3305                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3306                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3307                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3308         };
3309         gmi_cs7_n_pi6 {
3310                 nvidia,pins = "gmi_cs7_n_pi6";
3311                 nvidia,function = "nand";
3312                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3313                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3314                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3315         };
3316         gmi_wait_pi7 {
3317                 nvidia,pins = "gmi_wait_pi7";
3318                 nvidia,function = "nand";
3319                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3320                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3321                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3322         };
3323         lcd_de_pj1 {
3324                 nvidia,pins = "lcd_de_pj1";
3325                 nvidia,function = "displaya";
3326                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3327                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3328                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3329         };
3330         gmi_cs1_n_pj2 {
3331                 nvidia,pins = "gmi_cs1_n_pj2";
3332                 nvidia,function = "rsvd1";
3333                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3334                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3335                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3336         };
3337         lcd_hsync_pj3 {
3338                 nvidia,pins = "lcd_hsync_pj3";
3339                 nvidia,function = "displaya";
3340                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3341                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3342                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3343         };
3344         lcd_vsync_pj4 {
3345                 nvidia,pins = "lcd_vsync_pj4";
3346                 nvidia,function = "displaya";
3347                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3348                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3349                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3350         };
3351         uart2_cts_n_pj5 {
3352                 nvidia,pins = "uart2_cts_n_pj5";
3353                 nvidia,function = "uartb";
3354                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
3355                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3356                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3357         };
3358         uart2_rts_n_pj6 {
3359                 nvidia,pins = "uart2_rts_n_pj6";
3360                 nvidia,function = "uartb";
3361                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3362                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3363                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3364         };
3365         gmi_a16_pj7 {
3366                 nvidia,pins = "gmi_a16_pj7";
3367                 nvidia,function = "spi4";
3368                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3369                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3370                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3371         };
3372         gmi_adv_n_pk0 {
3373                 nvidia,pins = "gmi_adv_n_pk0";
3374                 nvidia,function = "nand";
3375                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3376                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3377                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3378         };
3379         gmi_clk_pk1 {
3380                 nvidia,pins = "gmi_clk_pk1";
3381                 nvidia,function = "nand";
3382                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3383                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3384                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3385         };
3386         gmi_cs2_n_pk3 {
3387                 nvidia,pins = "gmi_cs2_n_pk3";
3388                 nvidia,function = "rsvd1";
3389                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3390                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3391                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3392         };
3393         gmi_cs3_n_pk4 {
3394                 nvidia,pins = "gmi_cs3_n_pk4";
3395                 nvidia,function = "nand";
3396                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3397                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3398                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3399         };
3400         spdif_out_pk5 {
3401                 nvidia,pins = "spdif_out_pk5";
3402                 nvidia,function = "spdif";
3403                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3404                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3405                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3406         };
3407         spdif_in_pk6 {
3408                 nvidia,pins = "spdif_in_pk6";
3409                 nvidia,function = "spdif";
3410                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3411                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3412                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3413         };
3414         gmi_a19_pk7 {
3415                 nvidia,pins = "gmi_a19_pk7";
3416                 nvidia,function = "spi4";
3417                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3418                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3419                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3420         };
3421         vi_d2_pl0 {
3422                 nvidia,pins = "vi_d2_pl0";
3423                 nvidia,function = "sdmmc2";
3424                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3425                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3426                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3427         };
3428         vi_d3_pl1 {
3429                 nvidia,pins = "vi_d3_pl1";
3430                 nvidia,function = "sdmmc2";
3431                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3432                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3433                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3434         };
3435         vi_d4_pl2 {
3436                 nvidia,pins = "vi_d4_pl2";
3437                 nvidia,function = "vi";
3438                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3439                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3440                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3441         };
3442         vi_d5_pl3 {
3443                 nvidia,pins = "vi_d5_pl3";
3444                 nvidia,function = "sdmmc2";
3445                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3446                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3447                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3448         };
3449         vi_d6_pl4 {
3450                 nvidia,pins = "vi_d6_pl4";
3451                 nvidia,function = "vi";
3452                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3453                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3454                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3455         };
3456         vi_d7_pl5 {
3457                 nvidia,pins = "vi_d7_pl5";
3458                 nvidia,function = "sdmmc2";
3459                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3460                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3461                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3462         };
3463         vi_d8_pl6 {
3464                 nvidia,pins = "vi_d8_pl6";
3465                 nvidia,function = "sdmmc2";
3466                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3467                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3468                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3469         };
3470         vi_d9_pl7 {
3471                 nvidia,pins = "vi_d9_pl7";
3472                 nvidia,function = "sdmmc2";
3473                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3474                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3475                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3476         };
3477         lcd_d16_pm0 {
3478                 nvidia,pins = "lcd_d16_pm0";
3479                 nvidia,function = "displaya";
3480                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3481                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3482                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3483         };
3484         lcd_d17_pm1 {
3485                 nvidia,pins = "lcd_d17_pm1";
3486                 nvidia,function = "displaya";
3487                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3488                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3489                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3490         };
3491         lcd_d18_pm2 {
3492                 nvidia,pins = "lcd_d18_pm2";
3493                 nvidia,function = "displaya";
3494                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3495                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3496                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3497         };
3498         lcd_d19_pm3 {
3499                 nvidia,pins = "lcd_d19_pm3";
3500                 nvidia,function = "displaya";
3501                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3502                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3503                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3504         };
3505         lcd_d20_pm4 {
3506                 nvidia,pins = "lcd_d20_pm4";
3507                 nvidia,function = "displaya";
3508                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3509                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3510                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3511         };
3512         lcd_d21_pm5 {
3513                 nvidia,pins = "lcd_d21_pm5";
3514                 nvidia,function = "displaya";
3515                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3516                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3517                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3518         };
3519         lcd_d22_pm6 {
3520                 nvidia,pins = "lcd_d22_pm6";
3521                 nvidia,function = "displaya";
3522                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3523                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3524                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3525         };
3526         lcd_d23_pm7 {
3527                 nvidia,pins = "lcd_d23_pm7";
3528                 nvidia,function = "displaya";
3529                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3530                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3531                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3532         };
3533         dap1_fs_pn0 {
3534                 nvidia,pins = "dap1_fs_pn0";
3535                 nvidia,function = "i2s0";
3536                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3537                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3538                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3539         };
3540         dap1_din_pn1 {
3541                 nvidia,pins = "dap1_din_pn1";
3542                 nvidia,function = "i2s0";
3543                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3544                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3545                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3546         };
3547         dap1_dout_pn2 {
3548                 nvidia,pins = "dap1_dout_pn2";
3549                 nvidia,function = "i2s0";
3550                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3551                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3552                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3553         };
3554         dap1_sclk_pn3 {
3555                 nvidia,pins = "dap1_sclk_pn3";
3556                 nvidia,function = "i2s0";
3557                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3558                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3559                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3560         };
3561         lcd_cs0_n_pn4 {
3562                 nvidia,pins = "lcd_cs0_n_pn4";
3563                 nvidia,function = "displaya";
3564                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3565                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3566                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3567         };
3568         lcd_sdout_pn5 {
3569                 nvidia,pins = "lcd_sdout_pn5";
3570                 nvidia,function = "displaya";
3571                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3572                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3573                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3574         };
3575         lcd_dc0_pn6 {
3576                 nvidia,pins = "lcd_dc0_pn6";
3577                 nvidia,function = "displaya";
3578                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3579                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3580                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3581         };
3582         hdmi_int_pn7 {
3583                 nvidia,pins = "hdmi_int_pn7";
3584                 nvidia,function = "hdmi";
3585                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3586                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3587                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3588         };
3589         ulpi_data7_po0 {
3590                 nvidia,pins = "ulpi_data7_po0";
3591                 nvidia,function = "uarta";
3592                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
3593                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3594                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3595         };
3596         ulpi_data0_po1 {
3597                 nvidia,pins = "ulpi_data0_po1";
3598                 nvidia,function = "uarta";
3599                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3600                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3601                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3602         };
3603         ulpi_data1_po2 {
3604                 nvidia,pins = "ulpi_data1_po2";
3605                 nvidia,function = "uarta";
3606                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3607                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3608                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3609         };
3610         ulpi_data2_po3 {
3611                 nvidia,pins = "ulpi_data2_po3";
3612                 nvidia,function = "uarta";
3613                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3614                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3615                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3616         };
3617         ulpi_data3_po4 {
3618                 nvidia,pins = "ulpi_data3_po4";
3619                 nvidia,function = "uarta";
3620                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3621                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3622                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3623         };
3624         ulpi_data4_po5 {
3625                 nvidia,pins = "ulpi_data4_po5";
3626                 nvidia,function = "uarta";
3627                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3628                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3629                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3630         };
3631         ulpi_data5_po6 {
3632                 nvidia,pins = "ulpi_data5_po6";
3633                 nvidia,function = "uarta";
3634                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3635                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3636                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3637         };
3638         ulpi_data6_po7 {
3639                 nvidia,pins = "ulpi_data6_po7";
3640                 nvidia,function = "uarta";
3641                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3642                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3643                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3644         };
3645         dap3_fs_pp0 {
3646                 nvidia,pins = "dap3_fs_pp0";
3647                 nvidia,function = "i2s2";
3648                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3649                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3650                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3651         };
3652         dap3_din_pp1 {
3653                 nvidia,pins = "dap3_din_pp1";
3654                 nvidia,function = "i2s2";
3655                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3656                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3657                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3658         };
3659         dap3_dout_pp2 {
3660                 nvidia,pins = "dap3_dout_pp2";
3661                 nvidia,function = "i2s2";
3662                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3663                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3664                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3665         };
3666         dap3_sclk_pp3 {
3667                 nvidia,pins = "dap3_sclk_pp3";
3668                 nvidia,function = "i2s2";
3669                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3670                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3671                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3672         };
3673         dap4_fs_pp4 {
3674                 nvidia,pins = "dap4_fs_pp4";
3675                 nvidia,function = "i2s3";
3676                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3677                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3678                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3679         };
3680         dap4_din_pp5 {
3681                 nvidia,pins = "dap4_din_pp5";
3682                 nvidia,function = "i2s3";
3683                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3684                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3685                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3686         };
3687         dap4_dout_pp6 {
3688                 nvidia,pins = "dap4_dout_pp6";
3689                 nvidia,function = "i2s3";
3690                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3691                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3692                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3693         };
3694         dap4_sclk_pp7 {
3695                 nvidia,pins = "dap4_sclk_pp7";
3696                 nvidia,function = "i2s3";
3697                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3698                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3699                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3700         };
3701         kb_col0_pq0 {
3702                 nvidia,pins = "kb_col0_pq0";
3703                 nvidia,function = "kbc";
3704                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3705                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3706                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3707         };
3708         kb_col1_pq1 {
3709                 nvidia,pins = "kb_col1_pq1";
3710                 nvidia,function = "kbc";
3711                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3712                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3713                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3714         };
3715         kb_col2_pq2 {
3716                 nvidia,pins = "kb_col2_pq2";
3717                 nvidia,function = "kbc";
3718                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3719                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3720                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3721         };
3722         kb_col3_pq3 {
3723                 nvidia,pins = "kb_col3_pq3";
3724                 nvidia,function = "kbc";
3725                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3726                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3727                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3728         };
3729         kb_col4_pq4 {
3730                 nvidia,pins = "kb_col4_pq4";
3731                 nvidia,function = "kbc";
3732                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3733                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3734                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3735         };
3736         kb_col5_pq5 {
3737                 nvidia,pins = "kb_col5_pq5";
3738                 nvidia,function = "kbc";
3739                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3740                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3741                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3742         };
3743         kb_col6_pq6 {
3744                 nvidia,pins = "kb_col6_pq6";
3745                 nvidia,function = "kbc";
3746                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3747                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3748                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3749         };
3750         kb_col7_pq7 {
3751                 nvidia,pins = "kb_col7_pq7";
3752                 nvidia,function = "kbc";
3753                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3754                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3755                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3756         };
3757         kb_row0_pr0 {
3758                 nvidia,pins = "kb_row0_pr0";
3759                 nvidia,function = "kbc";
3760                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3761                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3762                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3763         };
3764         kb_row1_pr1 {
3765                 nvidia,pins = "kb_row1_pr1";
3766                 nvidia,function = "kbc";
3767                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3768                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3769                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3770         };
3771         kb_row2_pr2 {
3772                 nvidia,pins = "kb_row2_pr2";
3773                 nvidia,function = "kbc";
3774                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3775                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3776                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3777         };
3778         kb_row3_pr3 {
3779                 nvidia,pins = "kb_row3_pr3";
3780                 nvidia,function = "kbc";
3781                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3782                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3783                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3784         };
3785         kb_row4_pr4 {
3786                 nvidia,pins = "kb_row4_pr4";
3787                 nvidia,function = "kbc";
3788                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3789                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3790                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3791         };
3792         kb_row5_pr5 {
3793                 nvidia,pins = "kb_row5_pr5";
3794                 nvidia,function = "kbc";
3795                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3796                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3797                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3798         };
3799         kb_row6_pr6 {
3800                 nvidia,pins = "kb_row6_pr6";
3801                 nvidia,function = "kbc";
3802                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3803                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3804                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3805         };
3806         kb_row7_pr7 {
3807                 nvidia,pins = "kb_row7_pr7";
3808                 nvidia,function = "kbc";
3809                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3810                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3811                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3812         };
3813         kb_row8_ps0 {
3814                 nvidia,pins = "kb_row8_ps0";
3815                 nvidia,function = "kbc";
3816                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3817                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3818                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3819         };
3820         kb_row9_ps1 {
3821                 nvidia,pins = "kb_row9_ps1";
3822                 nvidia,function = "kbc";
3823                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3824                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3825                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3826         };
3827         kb_row10_ps2 {
3828                 nvidia,pins = "kb_row10_ps2";
3829                 nvidia,function = "kbc";
3830                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3831                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3832                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3833         };
3834         kb_row11_ps3 {
3835                 nvidia,pins = "kb_row11_ps3";
3836                 nvidia,function = "kbc";
3837                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3838                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3839                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3840         };
3841         kb_row12_ps4 {
3842                 nvidia,pins = "kb_row12_ps4";
3843                 nvidia,function = "kbc";
3844                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3845                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3846                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3847         };
3848         kb_row13_ps5 {
3849                 nvidia,pins = "kb_row13_ps5";
3850                 nvidia,function = "kbc";
3851                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3852                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3853                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3854         };
3855         kb_row14_ps6 {
3856                 nvidia,pins = "kb_row14_ps6";
3857                 nvidia,function = "kbc";
3858                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3859                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3860                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3861         };
3862         kb_row15_ps7 {
3863                 nvidia,pins = "kb_row15_ps7";
3864                 nvidia,function = "kbc";
3865                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3866                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3867                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3868         };
3869         vi_pclk_pt0 {
3870                 nvidia,pins = "vi_pclk_pt0";
3871                 nvidia,function = "rsvd1";
3872                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3873                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3874                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3875         };
3876         vi_mclk_pt1 {
3877                 nvidia,pins = "vi_mclk_pt1";
3878                 nvidia,function = "vi";
3879                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3880                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3881                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3882         };
3883         vi_d10_pt2 {
3884                 nvidia,pins = "vi_d10_pt2";
3885                 nvidia,function = "ddr";
3886                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3887                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3888                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3889         };
3890         vi_d11_pt3 {
3891                 nvidia,pins = "vi_d11_pt3";
3892                 nvidia,function = "ddr";
3893                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3894                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3895                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3896         };
3897         vi_d0_pt4 {
3898                 nvidia,pins = "vi_d0_pt4";
3899                 nvidia,function = "ddr";
3900                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3901                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3902                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3903         };
3904         gen2_i2c_scl_pt5 {
3905                 nvidia,pins = "gen2_i2c_scl_pt5";
3906                 nvidia,function = "i2c2";
3907                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3908                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3909                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3910                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
3911         };
3912         gen2_i2c_sda_pt6 {
3913                 nvidia,pins = "gen2_i2c_sda_pt6";
3914                 nvidia,function = "i2c2";
3915                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3916                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3917                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3918                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
3919         };
3920         sdmmc4_cmd_pt7 {
3921                 nvidia,pins = "sdmmc4_cmd_pt7";
3922                 nvidia,function = "sdmmc4";
3923                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3924                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3925                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3926                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
3927         };
3928         pu0 {
3929                 nvidia,pins = "pu0";
3930                 nvidia,function = "owr";
3931                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3932                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3933                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3934         };
3935         pu1 {
3936                 nvidia,pins = "pu1";
3937                 nvidia,function = "rsvd1";
3938                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3939                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3940                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3941         };
3942         pu2 {
3943                 nvidia,pins = "pu2";
3944                 nvidia,function = "rsvd1";
3945                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3946                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3947                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3948         };
3949         pu3 {
3950                 nvidia,pins = "pu3";
3951                 nvidia,function = "pwm0";
3952                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3953                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3954                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3955         };
3956         pu4 {
3957                 nvidia,pins = "pu4";
3958                 nvidia,function = "pwm1";
3959                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3960                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3961                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3962         };
3963         pu5 {
3964                 nvidia,pins = "pu5";
3965                 nvidia,function = "rsvd4";
3966                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3967                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3968                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3969         };
3970         pu6 {
3971                 nvidia,pins = "pu6";
3972                 nvidia,function = "pwm3";
3973                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3974                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3975                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3976         };
3977         jtag_rtck_pu7 {
3978                 nvidia,pins = "jtag_rtck_pu7";
3979                 nvidia,function = "rtck";
3980                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3981                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3982                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3983         };
3984         pv0 {
3985                 nvidia,pins = "pv0";
3986                 nvidia,function = "rsvd1";
3987                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3988                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3989                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3990         };
3991         pv1 {
3992                 nvidia,pins = "pv1";
3993                 nvidia,function = "rsvd1";
3994                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3995                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3996                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3997         };
3998         pv2 {
3999                 nvidia,pins = "pv2";
4000                 nvidia,function = "owr";
4001                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4002                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4003                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4004         };
4005         pv3 {
4006                 nvidia,pins = "pv3";
4007                 nvidia,function = "clk_12m_out";
4008                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4009                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4010                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4011         };
4012         ddc_scl_pv4 {
4013                 nvidia,pins = "ddc_scl_pv4";
4014                 nvidia,function = "i2c4";
4015                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4016                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4017                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4018         };
4019         ddc_sda_pv5 {
4020                 nvidia,pins = "ddc_sda_pv5";
4021                 nvidia,function = "i2c4";
4022                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4023                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4024                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4025         };
4026         crt_hsync_pv6 {
4027                 nvidia,pins = "crt_hsync_pv6";
4028                 nvidia,function = "crt";
4029                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4030                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4031                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4032         };
4033         crt_vsync_pv7 {
4034                 nvidia,pins = "crt_vsync_pv7";
4035                 nvidia,function = "crt";
4036                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4037                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4038                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4039         };
4040         lcd_cs1_n_pw0 {
4041                 nvidia,pins = "lcd_cs1_n_pw0";
4042                 nvidia,function = "displaya";
4043                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4044                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4045                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4046         };
4047         lcd_m1_pw1 {
4048                 nvidia,pins = "lcd_m1_pw1";
4049                 nvidia,function = "displaya";
4050                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
4051                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4052                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4053         };
4054         spi2_cs1_n_pw2 {
4055                 nvidia,pins = "spi2_cs1_n_pw2";
4056                 nvidia,function = "spi2";
4057                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4058                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4059                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4060         };
4061         clk1_out_pw4 {
4062                 nvidia,pins = "clk1_out_pw4";
4063                 nvidia,function = "extperiph1";
4064                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4065                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4066                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4067         };
4068         clk2_out_pw5 {
4069                 nvidia,pins = "clk2_out_pw5";
4070                 nvidia,function = "extperiph2";
4071                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4072                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4073                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4074         };
4075         uart3_txd_pw6 {
4076                 nvidia,pins = "uart3_txd_pw6";
4077                 nvidia,function = "uartc";
4078                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4079                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4080                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4081         };
4082         uart3_rxd_pw7 {
4083                 nvidia,pins = "uart3_rxd_pw7";
4084                 nvidia,function = "uartc";
4085                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4086                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4087                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4088         };
4089         spi2_sck_px2 {
4090                 nvidia,pins = "spi2_sck_px2";
4091                 nvidia,function = "gmi";
4092                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4093                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4094                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4095         };
4096         spi1_mosi_px4 {
4097                 nvidia,pins = "spi1_mosi_px4";
4098                 nvidia,function = "spi1";
4099                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4100                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4101                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4102         };
4103         spi1_sck_px5 {
4104                 nvidia,pins = "spi1_sck_px5";
4105                 nvidia,function = "spi1";
4106                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4107                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4108                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4109         };
4110         spi1_cs0_n_px6 {
4111                 nvidia,pins = "spi1_cs0_n_px6";
4112                 nvidia,function = "spi1";
4113                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4114                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4115                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4116         };
4117         spi1_miso_px7 {
4118                 nvidia,pins = "spi1_miso_px7";
4119                 nvidia,function = "spi1";
4120                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4121                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4122                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4123         };
4124         ulpi_clk_py0 {
4125                 nvidia,pins = "ulpi_clk_py0";
4126                 nvidia,function = "uartd";
4127                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4128                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4129                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4130         };
4131         ulpi_dir_py1 {
4132                 nvidia,pins = "ulpi_dir_py1";
4133                 nvidia,function = "uartd";
4134                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4135                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4136                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4137         };
4138         ulpi_nxt_py2 {
4139                 nvidia,pins = "ulpi_nxt_py2";
4140                 nvidia,function = "uartd";
4141                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4142                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4143                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4144         };
4145         ulpi_stp_py3 {
4146                 nvidia,pins = "ulpi_stp_py3";
4147                 nvidia,function = "uartd";
4148                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4149                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4150                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4151         };
4152         sdmmc1_dat3_py4 {
4153                 nvidia,pins = "sdmmc1_dat3_py4";
4154                 nvidia,function = "sdmmc1";
4155                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4156                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4157                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4158         };
4159         sdmmc1_dat2_py5 {
4160                 nvidia,pins = "sdmmc1_dat2_py5";
4161                 nvidia,function = "sdmmc1";
4162                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4163                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4164                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4165         };
4166         sdmmc1_dat1_py6 {
4167                 nvidia,pins = "sdmmc1_dat1_py6";
4168                 nvidia,function = "sdmmc1";
4169                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4170                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4171                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4172         };
4173         sdmmc1_dat0_py7 {
4174                 nvidia,pins = "sdmmc1_dat0_py7";
4175                 nvidia,function = "sdmmc1";
4176                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4177                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4178                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4179         };
4180         sdmmc1_clk_pz0 {
4181                 nvidia,pins = "sdmmc1_clk_pz0";
4182                 nvidia,function = "sdmmc1";
4183                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4184                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4185                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4186         };
4187         sdmmc1_cmd_pz1 {
4188                 nvidia,pins = "sdmmc1_cmd_pz1";
4189                 nvidia,function = "sdmmc1";
4190                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4191                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4192                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4193         };
4194         lcd_sdin_pz2 {
4195                 nvidia,pins = "lcd_sdin_pz2";
4196                 nvidia,function = "displaya";
4197                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4198                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4199                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4200         };
4201         lcd_wr_n_pz3 {
4202                 nvidia,pins = "lcd_wr_n_pz3";
4203                 nvidia,function = "displaya";
4204                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4205                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4206                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4207         };
4208         lcd_sck_pz4 {
4209                 nvidia,pins = "lcd_sck_pz4";
4210                 nvidia,function = "displaya";
4211                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4212                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4213                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4214         };
4215         sys_clk_req_pz5 {
4216                 nvidia,pins = "sys_clk_req_pz5";
4217                 nvidia,function = "sysclk";
4218                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4219                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4220                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4221         };
4222         pwr_i2c_scl_pz6 {
4223                 nvidia,pins = "pwr_i2c_scl_pz6";
4224                 nvidia,function = "i2cpwr";
4225                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4226                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4227                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4228                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4229         };
4230         pwr_i2c_sda_pz7 {
4231                 nvidia,pins = "pwr_i2c_sda_pz7";
4232                 nvidia,function = "i2cpwr";
4233                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4234                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4235                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4236                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4237         };
4238         sdmmc4_dat0_paa0 {
4239                 nvidia,pins = "sdmmc4_dat0_paa0";
4240                 nvidia,function = "sdmmc4";
4241                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4242                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4243                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4244                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4245         };
4246         sdmmc4_dat1_paa1 {
4247                 nvidia,pins = "sdmmc4_dat1_paa1";
4248                 nvidia,function = "sdmmc4";
4249                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4250                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4251                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4252                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4253         };
4254         sdmmc4_dat2_paa2 {
4255                 nvidia,pins = "sdmmc4_dat2_paa2";
4256                 nvidia,function = "sdmmc4";
4257                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4258                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4259                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4260                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4261         };
4262         sdmmc4_dat3_paa3 {
4263                 nvidia,pins = "sdmmc4_dat3_paa3";
4264                 nvidia,function = "sdmmc4";
4265                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4266                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4267                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4268                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4269         };
4270         sdmmc4_dat4_paa4 {
4271                 nvidia,pins = "sdmmc4_dat4_paa4";
4272                 nvidia,function = "sdmmc4";
4273                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4274                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4275                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4276                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4277         };
4278         sdmmc4_dat5_paa5 {
4279                 nvidia,pins = "sdmmc4_dat5_paa5";
4280                 nvidia,function = "sdmmc4";
4281                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4282                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4283                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4284                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4285         };
4286         sdmmc4_dat6_paa6 {
4287                 nvidia,pins = "sdmmc4_dat6_paa6";
4288                 nvidia,function = "sdmmc4";
4289                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4290                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4291                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4292                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4293         };
4294         sdmmc4_dat7_paa7 {
4295                 nvidia,pins = "sdmmc4_dat7_paa7";
4296                 nvidia,function = "sdmmc4";
4297                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4298                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4299                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4300                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4301         };
4302         pbb0 {
4303                 nvidia,pins = "pbb0";
4304                 nvidia,function = "i2s4";
4305                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4306                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4307                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4308         };
4309         cam_i2c_scl_pbb1 {
4310                 nvidia,pins = "cam_i2c_scl_pbb1";
4311                 nvidia,function = "i2c3";
4312                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4313                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4314                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4315                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
4316         };
4317         cam_i2c_sda_pbb2 {
4318                 nvidia,pins = "cam_i2c_sda_pbb2";
4319                 nvidia,function = "i2c3";
4320                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4321                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4322                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4323                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
4324         };
4325         pbb3 {
4326                 nvidia,pins = "pbb3";
4327                 nvidia,function = "vgp3";
4328                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4329                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4330                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4331         };
4332         pbb4 {
4333                 nvidia,pins = "pbb4";
4334                 nvidia,function = "vgp4";
4335                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4336                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4337                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4338         };
4339         pbb5 {
4340                 nvidia,pins = "pbb5";
4341                 nvidia,function = "vgp5";
4342                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4343                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4344                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4345         };
4346         pbb6 {
4347                 nvidia,pins = "pbb6";
4348                 nvidia,function = "vgp6";
4349                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4350                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4351                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4352         };
4353         pbb7 {
4354                 nvidia,pins = "pbb7";
4355                 nvidia,function = "i2s4";
4356                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4357                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4358                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4359         };
4360         cam_mclk_pcc0 {
4361                 nvidia,pins = "cam_mclk_pcc0";
4362                 nvidia,function = "vi_alt3";
4363                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4364                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4365                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4366         };
4367         pcc1 {
4368                 nvidia,pins = "pcc1";
4369                 nvidia,function = "i2s4";
4370                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4371                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4372                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4373         };
4374         pcc2 {
4375                 nvidia,pins = "pcc2";
4376                 nvidia,function = "i2s4";
4377                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4378                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4379                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4380         };
4381         sdmmc4_rst_n_pcc3 {
4382                 nvidia,pins = "sdmmc4_rst_n_pcc3";
4383                 nvidia,function = "sdmmc4";
4384                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
4385                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4386                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4387                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4388         };
4389         sdmmc4_clk_pcc4 {
4390                 nvidia,pins = "sdmmc4_clk_pcc4";
4391                 nvidia,function = "sdmmc4";
4392                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4393                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4394                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4395                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4396         };
4397         clk2_req_pcc5 {
4398                 nvidia,pins = "clk2_req_pcc5";
4399                 nvidia,function = "dap";
4400                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4401                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4402                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4403         };
4404         pex_l2_rst_n_pcc6 {
4405                 nvidia,pins = "pex_l2_rst_n_pcc6";
4406                 nvidia,function = "pcie";
4407                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4408                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4409                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4410         };
4411         pex_l2_clkreq_n_pcc7 {
4412                 nvidia,pins = "pex_l2_clkreq_n_pcc7";
4413                 nvidia,function = "pcie";
4414                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4415                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4416                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4417         };
4418         pex_l0_prsnt_n_pdd0 {
4419                 nvidia,pins = "pex_l0_prsnt_n_pdd0";
4420                 nvidia,function = "pcie";
4421                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4422                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4423                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4424         };
4425         pex_l0_rst_n_pdd1 {
4426                 nvidia,pins = "pex_l0_rst_n_pdd1";
4427                 nvidia,function = "pcie";
4428                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4429                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4430                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4431         };
4432         pex_l0_clkreq_n_pdd2 {
4433                 nvidia,pins = "pex_l0_clkreq_n_pdd2";
4434                 nvidia,function = "pcie";
4435                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4436                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4437                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4438         };
4439         pex_wake_n_pdd3 {
4440                 nvidia,pins = "pex_wake_n_pdd3";
4441                 nvidia,function = "pcie";
4442                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4443                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4444                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4445         };
4446         pex_l1_prsnt_n_pdd4 {
4447                 nvidia,pins = "pex_l1_prsnt_n_pdd4";
4448                 nvidia,function = "pcie";
4449                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4450                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4451                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4452         };
4453         pex_l1_rst_n_pdd5 {
4454                 nvidia,pins = "pex_l1_rst_n_pdd5";
4455                 nvidia,function = "pcie";
4456                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4457                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4458                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4459         };
4460         pex_l1_clkreq_n_pdd6 {
4461                 nvidia,pins = "pex_l1_clkreq_n_pdd6";
4462                 nvidia,function = "pcie";
4463                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4464                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4465                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4466         };
4467         pex_l2_prsnt_n_pdd7 {
4468                 nvidia,pins = "pex_l2_prsnt_n_pdd7";
4469                 nvidia,function = "pcie";
4470                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4471                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4472                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4473         };
4474         clk3_out_pee0 {
4475                 nvidia,pins = "clk3_out_pee0";
4476                 nvidia,function = "extperiph3";
4477                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4478                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4479                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4480         };
4481         clk3_req_pee1 {
4482                 nvidia,pins = "clk3_req_pee1";
4483                 nvidia,function = "dev3";
4484                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4485                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4486                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4487         };
4488         clk1_req_pee2 {
4489                 nvidia,pins = "clk1_req_pee2";
4490                 nvidia,function = "dap";
4491                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4492                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4493                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4494         };
4495         hdmi_cec_pee3 {
4496                 nvidia,pins = "hdmi_cec_pee3";
4497                 nvidia,function = "cec";
4498                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4499                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4500                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4501                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
4502         };
4503         owr {
4504                 nvidia,pins = "owr";
4505                 nvidia,function = "owr";
4506                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4507                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4508                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4509         };
4510         drive_groups {
4511                 nvidia,pins = "drive_gma",
4512                               "drive_gmb",
4513                               "drive_gmc",
4514                               "drive_gmd";
4515                 nvidia,pull-down-strength = <9>;
4516                 nvidia,pull-up-strength = <9>;
4517                 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
4518                 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
4519         };
4520 };
4521
4522 &emc_icc_dvfs_opp_table {
4523         /delete-node/ opp@900000000,1350;
4524 };
4525
4526 &emc_bw_dfs_opp_table {
4527         /delete-node/ opp@900000000;
4528 };