arch/arm/boot/dts/tegra30-ouya.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/input/gpio-keys.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/thermal/thermal.h>
   7
   8 #include "tegra30.dtsi"
   9 #include "tegra30-cpu-opp.dtsi"
  10 #include "tegra30-cpu-opp-microvolt.dtsi"
  11
  12 / {
  13         model = "Ouya Game Console";
  14         compatible = "ouya,ouya", "nvidia,tegra30";
  15
  16         aliases {
  17                 mmc0 = &sdmmc4; /* eMMC */
  18                 mmc1 = &sdmmc3; /* WiFi */
  19                 rtc0 = &pmic;
  20                 rtc1 = "/rtc@7000e000";
  21                 serial0 = &uartd; /* Debug Port */
  22                 serial1 = &uartc; /* Bluetooth */
  23         };
  24
  25         chosen {
  26                 stdout-path = "serial0:115200n8";
  27         };
  28
  29         memory@80000000 {
  30                 reg = <0x80000000 0x40000000>;
  31         };
  32
  33         reserved-memory {
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 ranges;
  37
  38                 linux,cma@80000000 {
  39                         compatible = "shared-dma-pool";
  40                         alloc-ranges = <0x80000000 0x30000000>;
  41                         size = <0x10000000>; /* 256MiB */
  42                         linux,cma-default;
  43                         reusable;
  44                 };
  45
  46                 ramoops@bfdf0000 {
  47                         compatible = "ramoops";
  48                         reg = <0xbfdf0000 0x10000>;     /* 64kB */
  49                         console-size = <0x8000>;        /* 32kB */
  50                         record-size = <0x400>;          /*  1kB */
  51                         ecc-size = <16>;
  52                 };
  53
  54                 trustzone@bfe00000 {
  55                         reg = <0xbfe00000 0x200000>;
  56                         no-map;
  57                 };
  58         };
  59
  60         host1x@50000000 {
  61                 hdmi@54280000 {
  62                         status = "okay";
  63                         vdd-supply = <&vdd_vid_reg>;
  64                         pll-supply = <&ldo7_reg>;
  65                         hdmi-supply = <&sys_3v3_reg>;
  66                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  67                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  68                 };
  69         };
  70
  71         gpio: gpio@6000d000 {
  72                 gpio-ranges = <&pinmux 0 0 248>;
  73                 #reset-cells = <1>;
  74         };
  75
  76         pinmux@70000868 {
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&state_default>;
  79                 state_default: pinmux {
  80                         /* located at $state_default below */
  81                 };
  82         };
  83
  84         uartc: serial@70006200 {
  85                 status = "okay";
  86                 compatible = "nvidia,tegra30-hsuart";
  87
  88                 nvidia,adjust-baud-rates = <0 9600 100>,
  89                                            <9600 115200 200>,
  90                                            <1000000 4000000 136>;
  91
  92                 /* Azurewave AW-NH660 BCM4330B1 */
  93                 bluetooth {
  94                         compatible = "brcm,bcm4330-bt";
  95
  96                         max-speed = <4000000>;
  97
  98                         clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  99                         clock-names = "txco";
 100
 101                         vbat-supply  = <&sys_3v3_reg>;
 102                         vddio-supply = <&vdd_1v8>;
 103
 104                         shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
 105                         device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
 106                         host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
 107                 };
 108         };
 109
 110         uartd: serial@70006300 {
 111                 status = "okay";
 112         };
 113
 114         hdmi_ddc: i2c@7000c700 {
 115                 status = "okay";
 116                 clock-frequency = <100000>;
 117         };
 118
 119         i2c@7000d000 {
 120                 status = "okay";
 121                 clock-frequency = <400000>;
 122
 123                 cpu_temp: nct1008@4c {
 124                         compatible = "onnn,nct1008";
 125                         reg = <0x4c>;
 126                         vcc-supply = <&sys_3v3_reg>;
 127                         #thermal-sensor-cells = <1>;
 128 /*
 129  *                      The interrupt is bugged, once triggered it never clears.
 130  *                      interrupt-parent = <&gpio>;
 131  *                      interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
 132  */
 133                 };
 134
 135                 pmic: pmic@2d {
 136                         compatible = "ti,tps65911";
 137                         reg = <0x2d>;
 138
 139                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 140                         #interrupt-cells = <2>;
 141                         interrupt-controller;
 142
 143                         ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>;
 144                         ti,system-power-controller;
 145                         ti,sleep-keep-ck32k;
 146                         ti,sleep-enable;
 147
 148                         #gpio-cells = <2>;
 149                         gpio-controller;
 150
 151                         vcc1-supply = <&vdd_5v0_reg>;
 152                         vcc2-supply = <&vdd_5v0_reg>;
 153                         vcc3-supply = <&vdd_1v8>;
 154                         vcc4-supply = <&vdd_5v0_reg>;
 155                         vcc5-supply = <&vdd_5v0_reg>;
 156                         vcc6-supply = <&vdd2_reg>;
 157                         vcc7-supply = <&vdd_5v0_reg>;
 158                         vccio-supply = <&vdd_5v0_reg>;
 159
 160                         regulators {
 161                                 vdd1_reg: vdd1 {
 162                                         regulator-name = "vddio_ddr_1v2";
 163                                         regulator-min-microvolt = <1200000>;
 164                                         regulator-max-microvolt = <1200000>;
 165                                         regulator-always-on;
 166                                 };
 167
 168                                 vdd2_reg: vdd2 {
 169                                         regulator-name = "vdd_1v5_gen";
 170                                         regulator-min-microvolt = <1500000>;
 171                                         regulator-max-microvolt = <1500000>;
 172                                         regulator-always-on;
 173                                 };
 174
 175                                 vdd_cpu: vddctrl {
 176                                         regulator-name = "vdd_cpu,vdd_sys";
 177                                         regulator-min-microvolt = <800000>;
 178                                         regulator-max-microvolt = <1270000>;
 179                                         regulator-coupled-with = <&vdd_core>;
 180                                         regulator-coupled-max-spread = <300000>;
 181                                         regulator-max-step-microvolt = <100000>;
 182                                         regulator-always-on;
 183
 184                                         nvidia,tegra-cpu-regulator;
 185                                 };
 186
 187                                 vdd_1v8: vio {
 188                                         regulator-name = "vdd_1v8_gen";
 189                                         regulator-min-microvolt = <1800000>;
 190                                         regulator-max-microvolt = <1800000>;
 191                                         regulator-always-on;
 192                                 };
 193
 194                                 ldo1_reg: ldo1 {
 195                                         regulator-name = "vdd_pexa,vdd_pexb";
 196                                         regulator-min-microvolt = <1050000>;
 197                                         regulator-max-microvolt = <1050000>;
 198                                         regulator-always-on;
 199                                 };
 200
 201                                 ldo2_reg: ldo2 {
 202                                         regulator-name = "vdd_sata,avdd_plle";
 203                                         regulator-min-microvolt = <1050000>;
 204                                         regulator-max-microvolt = <1050000>;
 205                                         regulator-always-on;
 206                                 };
 207
 208                                 /* LDO3 is not connected to anything */
 209
 210                                 ldo4_reg: ldo4 {
 211                                         regulator-name = "vdd_rtc";
 212                                         regulator-min-microvolt = <1200000>;
 213                                         regulator-max-microvolt = <1200000>;
 214                                         regulator-always-on;
 215                                 };
 216
 217                                 ldo5_reg: ldo5 {
 218                                         regulator-name = "vddio_sdmmc,avdd_vdac";
 219                                         regulator-min-microvolt = <1800000>;
 220                                         regulator-max-microvolt = <3300000>;
 221                                         regulator-always-on;
 222                                 };
 223
 224                                 ldo6_reg: ldo6 {
 225                                         regulator-name = "avdd_dsi_csi,pwrdet_mipi";
 226                                         regulator-min-microvolt = <1200000>;
 227                                         regulator-max-microvolt = <1200000>;
 228                                         regulator-always-on;
 229                                 };
 230
 231                                 ldo7_reg: ldo7 {
 232                                         regulator-name = "vdd_pllm,x,u,a_p_c_s";
 233                                         regulator-min-microvolt = <1200000>;
 234                                         regulator-max-microvolt = <1200000>;
 235                                         regulator-always-on;
 236                                 };
 237
 238                                 ldo8_reg: ldo8 {
 239                                         regulator-name = "vdd_ddr_hs";
 240                                         regulator-min-microvolt = <1000000>;
 241                                         regulator-max-microvolt = <1000000>;
 242                                         regulator-always-on;
 243                                 };
 244                         };
 245                 };
 246
 247                 vdd_core: tps62361@60 {
 248                         compatible = "ti,tps62361";
 249                         reg = <0x60>;
 250
 251                         regulator-name = "vdd_core";
 252                         regulator-min-microvolt = <950000>;
 253                         regulator-max-microvolt = <1350000>;
 254                         regulator-coupled-with = <&vdd_cpu>;
 255                         regulator-coupled-max-spread = <300000>;
 256                         regulator-max-step-microvolt = <100000>;
 257                         regulator-boot-on;
 258                         regulator-always-on;
 259                         ti,vsel0-state-high;
 260                         ti,vsel1-state-high;
 261                         ti,enable-vout-discharge;
 262
 263                         nvidia,tegra-core-regulator;
 264                 };
 265         };
 266
 267         pmc@7000e400 {
 268                 status = "okay";
 269                 nvidia,invert-interrupt;
 270                 nvidia,suspend-mode = <1>;
 271                 nvidia,cpu-pwr-good-time = <2000>;
 272                 nvidia,cpu-pwr-off-time = <200>;
 273                 nvidia,core-pwr-good-time = <3845 3845>;
 274                 nvidia,core-pwr-off-time = <458>;
 275                 nvidia,core-power-req-active-high;
 276                 nvidia,sys-clock-req-active-high;
 277         };
 278
 279         mc_timings: memory-controller@7000f000 {
 280                 /* timings located at &mc_timings below */
 281         };
 282
 283         emc_timings: memory-controller@7000f400 {
 284                 /* timings located at &emc_timings below */
 285         };
 286
 287         hda@70030000 {
 288                 status = "okay";
 289         };
 290
 291         wifi_pwrseq: wifi_pwrseq {
 292                 compatible = "mmc-pwrseq-simple";
 293
 294                 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
 295                 clock-names = "ext_clock";
 296
 297                 reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
 298                 post-power-on-delay-ms = <300>;
 299                 power-off-delay-us = <300>;
 300         };
 301
 302         sdmmc3: mmc@78000400 {
 303                 status = "okay";
 304
 305                 #address-cells = <1>;
 306                 #size-cells = <0>;
 307
 308                 assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 309                 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
 310                 assigned-clock-rates = <50000000>;
 311
 312                 max-frequency = <50000000>;
 313                 keep-power-in-suspend;
 314
 315                 bus-width = <4>;
 316                 non-removable;
 317
 318                 mmc-pwrseq = <&wifi_pwrseq>;
 319                 vmmc-supply = <&sdmmc_3v3_reg>;
 320                 vqmmc-supply = <&vdd_1v8>;
 321
 322                 /* Azurewave AW-NH660 BCM4330 */
 323                 brcmf: wifi@1 {
 324                         reg = <1>;
 325                         compatible = "brcm,bcm4329-fmac";
 326                         interrupt-parent = <&gpio>;
 327                         interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
 328                         interrupt-names = "host-wake";
 329                 };
 330         };
 331
 332         sdmmc4: mmc@78000600 {
 333                 status = "okay";
 334
 335                 keep-power-in-suspend;
 336                 bus-width = <8>;
 337                 non-removable;
 338                 vmmc-supply = <&sys_3v3_reg>;
 339                 vqmmc-supply = <&vdd_1v8>;
 340                 nvidia,default-tap = <0x0F>;
 341                 max-frequency = <25500000>;
 342         };
 343
 344         usb@7d000000 {
 345                 compatible = "nvidia,tegra30-udc";
 346                 status = "okay";
 347         };
 348
 349         usb-phy@7d000000 {
 350                 status = "okay";
 351                 dr_mode = "peripheral";
 352         };
 353
 354         usb@7d004000 {
 355                 status = "okay";
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358
 359                 smsc@2 { /* SMSC 10/100T Ethernet Controller */
 360                         compatible = "usb424,9e00";
 361                         reg = <2>;
 362                         local-mac-address = [00 11 22 33 44 55];
 363                 };
 364         };
 365
 366         usb-phy@7d004000 {
 367                 vbus-supply = <&vdd_smsc>;
 368                 status = "okay";
 369         };
 370
 371         usb@7d008000 {
 372                 status = "okay";
 373         };
 374
 375         usb-phy@7d008000 {
 376                 vbus-supply = <&usb3_vbus_reg>;
 377                 status = "okay";
 378         };
 379
 380         /* PMIC has a built-in 32KHz oscillator which is used by PMC */
 381         clk32k_in: clock {
 382                 compatible = "fixed-clock";
 383                 #clock-cells = <0>;
 384                 clock-frequency = <32768>;
 385                 clock-output-names = "pmic-oscillator";
 386         };
 387
 388         cpus {
 389                 cpu0: cpu@0 {
 390                         operating-points-v2 = <&cpu0_opp_table>;
 391                         cpu-supply = <&vdd_cpu>;
 392                         #cooling-cells = <2>;
 393                 };
 394                 cpu@1 {
 395                         operating-points-v2 = <&cpu0_opp_table>;
 396                         cpu-supply = <&vdd_cpu>;
 397                 };
 398
 399                 cpu@2 {
 400                         operating-points-v2 = <&cpu0_opp_table>;
 401                         cpu-supply = <&vdd_cpu>;
 402                 };
 403
 404                 cpu@3 {
 405                         operating-points-v2 = <&cpu0_opp_table>;
 406                         cpu-supply = <&vdd_cpu>;
 407                 };
 408         };
 409
 410         firmware {
 411                 trusted-foundations {
 412                         compatible = "tlm,trusted-foundations";
 413                         tlm,version-major = <0x0>;
 414                         tlm,version-minor = <0x0>;
 415                 };
 416         };
 417
 418         fan: gpio_fan {
 419                 compatible = "gpio-fan";
 420                 gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
 421                 gpio-fan,speed-map = <0    0
 422                                       4500 1>;
 423                 #cooling-cells = <2>;
 424         };
 425
 426         thermal-zones {
 427                 cpu_thermal: cpu-thermal {
 428                         polling-delay = <5000>;
 429                         polling-delay-passive = <5000>;
 430
 431                         thermal-sensors = <&cpu_temp 1>;
 432
 433                         trips {
 434                                 cpu_alert0: cpu-alert0 {
 435                                         temperature = <50000>;
 436                                         hysteresis = <10000>;
 437                                         type = "active";
 438                                 };
 439                                 cpu_alert1: cpu-alert1 {
 440                                         temperature = <70000>;
 441                                         hysteresis = <5000>;
 442                                         type = "passive";
 443                                 };
 444                                 cpu_crit: cpu-crit {
 445                                         temperature = <90000>;
 446                                         hysteresis = <2000>;
 447                                         type = "critical";
 448                                 };
 449                         };
 450
 451                         cooling-maps {
 452                                 map0 {
 453                                         trip = <&cpu_alert0>;
 454                                         cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 455                                 };
 456                                 map1 {
 457                                         trip = <&cpu_alert1>;
 458                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 459                                 };
 460                         };
 461                 };
 462         };
 463
 464         vdd_12v_in: vdd_12v_in {
 465                 compatible = "regulator-fixed";
 466                 regulator-name = "vdd_12v_in";
 467                 regulator-min-microvolt = <12000000>;
 468                 regulator-max-microvolt = <12000000>;
 469                 regulator-always-on;
 470         };
 471
 472         sdmmc_3v3_reg: sdmmc_3v3_reg {
 473                 compatible = "regulator-fixed";
 474                 regulator-name = "sdmmc_3v3";
 475                 regulator-min-microvolt = <3300000>;
 476                 regulator-max-microvolt = <3300000>;
 477                 enable-active-high;
 478                 regulator-always-on;
 479                 gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
 480                 vin-supply = <&sys_3v3_reg>;
 481         };
 482
 483         vdd_fuse_3v3_reg: vdd_fuse_3v3_reg {
 484                 compatible = "regulator-fixed";
 485                 regulator-name = "vdd_fuse_3v3";
 486                 regulator-min-microvolt = <3300000>;
 487                 regulator-max-microvolt = <3300000>;
 488                 enable-active-high;
 489                 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
 490                 vin-supply = <&sys_3v3_reg>;
 491                 regulator-always-on;
 492         };
 493
 494         vdd_vid_reg: vdd_vid_reg {
 495                 compatible = "regulator-fixed";
 496                 regulator-name = "vddio_vid";
 497                 regulator-min-microvolt = <5000000>;
 498                 regulator-max-microvolt = <5000000>;
 499                 enable-active-high;
 500                 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
 501                 vin-supply = <&vdd_5v0_reg>;
 502                 regulator-boot-on;
 503         };
 504
 505         ddr_reg: ddr_reg {
 506                 compatible = "regulator-fixed";
 507                 regulator-name = "vdd_ddr";
 508                 regulator-min-microvolt = <1500000>;
 509                 regulator-max-microvolt = <1500000>;
 510                 regulator-always-on;
 511                 enable-active-high;
 512                 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 513                 regulator-boot-on;
 514                 vin-supply = <&vdd_12v_in>;
 515         };
 516
 517         sys_3v3_reg: sys_3v3_reg {
 518                 compatible = "regulator-fixed";
 519                 regulator-name = "sys_3v3";
 520                 regulator-min-microvolt = <3300000>;
 521                 regulator-max-microvolt = <3300000>;
 522                 enable-active-high;
 523                 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 524                 regulator-always-on;
 525                 regulator-boot-on;
 526                 vin-supply = <&vdd_12v_in>;
 527         };
 528
 529         vdd_5v0_reg: vdd_5v0_reg {
 530                 compatible = "regulator-fixed";
 531                 regulator-name = "vdd_5v0";
 532                 regulator-min-microvolt = <5000000>;
 533                 regulator-max-microvolt = <5000000>;
 534                 enable-active-high;
 535                 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 536                 regulator-always-on;
 537                 regulator-boot-on;
 538                 vin-supply = <&vdd_12v_in>;
 539         };
 540
 541         vdd_smsc: vdd_smsc {
 542                 compatible = "regulator-fixed";
 543                 regulator-name = "vdd_smsc";
 544                 enable-active-high;
 545                 gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>;
 546         };
 547
 548         usb3_vbus_reg: usb3_vbus_reg {
 549                 compatible = "regulator-fixed";
 550                 regulator-name = "usb3_vbus";
 551                 regulator-min-microvolt = <5000000>;
 552                 regulator-max-microvolt = <5000000>;
 553                 enable-active-high;
 554                 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
 555                 vin-supply = <&vdd_5v0_reg>;
 556         };
 557
 558         gpio-keys {
 559                 compatible = "gpio-keys";
 560
 561                 power {
 562                         gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
 563                         debounce-interval = <10>;
 564                         linux,code = <KEY_POWER>;
 565                         wakeup-event-action = <EV_ACT_ASSERTED>;
 566                         wakeup-source;
 567                 };
 568         };
 569
 570
 571         leds {
 572                 compatible = "gpio-leds";
 573
 574                 led-power {
 575                         label = "power-led";
 576                         gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
 577                         default-state = "on";
 578                         linux,default-trigger = "heartbeat";
 579                         retain-state-suspended;
 580                 };
 581         };
 582 };
 583 &mc_timings {
 584         emc-timings-0 {
 585                 nvidia,ram-code = <0>; /* Samsung RAM */
 586                 timing-25500000 {
 587                         clock-frequency = <25500000>;
 588                         nvidia,emem-configuration = <
 589                                 0x00030003 /* MC_EMEM_ARB_CFG */
 590                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 591                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 592                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 593                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 594                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 595                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 596                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 597                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 598                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 599                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 600                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 601                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 602                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 603                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 604                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 605                                 0x75830303 /* MC_EMEM_ARB_MISC0 */
 606                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 607                         >;
 608                 };
 609                 timing-51000000 {
 610                         clock-frequency = <51000000>;
 611                         nvidia,emem-configuration = <
 612                                 0x00010003 /* MC_EMEM_ARB_CFG */
 613                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 614                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 615                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 616                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 617                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 618                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 619                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 620                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 621                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 622                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 623                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 624                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 625                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 626                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 627                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 628                                 0x74630303 /* MC_EMEM_ARB_MISC0 */
 629                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 630                         >;
 631                 };
 632                 timing-102000000 {
 633                         clock-frequency = <102000000>;
 634                         nvidia,emem-configuration = <
 635                                 0x00000003 /* MC_EMEM_ARB_CFG */
 636                                 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 637                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 638                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 639                                 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 640                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 641                                 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 642                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 643                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 644                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 645                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 646                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 647                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 648                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 649                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 650                                 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 651                                 0x73c30504 /* MC_EMEM_ARB_MISC0 */
 652                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 653                         >;
 654                 };
 655                 timing-204000000 {
 656                         clock-frequency = <204000000>;
 657                         nvidia,emem-configuration = <
 658                                 0x00000006 /* MC_EMEM_ARB_CFG */
 659                                 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 660                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 661                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 662                                 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 663                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 664                                 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 665                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 666                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 667                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 668                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 669                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 670                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 671                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 672                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 673                                 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 674                                 0x73840a06 /* MC_EMEM_ARB_MISC0 */
 675                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 676                         >;
 677                 };
 678                 timing-400000000 {
 679                         clock-frequency = <400000000>;
 680                         nvidia,emem-configuration = <
 681                                 0x0000000c /* MC_EMEM_ARB_CFG */
 682                                 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 683                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 684                                 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 685                                 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 686                                 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 687                                 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 688                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 689                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 690                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 691                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 692                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 693                                 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 694                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 695                                 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 696                                 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 697                                 0x7086120a /* MC_EMEM_ARB_MISC0 */
 698                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 699                         >;
 700                 };
 701                 timing-800000000 {
 702                         clock-frequency = <800000000>;
 703                         nvidia,emem-configuration = <
 704                                 0x00000018 /* MC_EMEM_ARB_CFG */
 705                                 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 706                                 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 707                                 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
 708                                 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
 709                                 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
 710                                 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
 711                                 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
 712                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 713                                 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
 714                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 715                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 716                                 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
 717                                 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
 718                                 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
 719                                 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
 720                                 0x712c2414 /* MC_EMEM_ARB_MISC0 */
 721                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 722                         >;
 723                 };
 724         };
 725         emc-timings-1 {
 726                 nvidia,ram-code = <1>; /* Hynix M RAM */
 727                 timing-25500000 {
 728                         clock-frequency = <25500000>;
 729                         nvidia,emem-configuration = <
 730                                 0x00030003 /* MC_EMEM_ARB_CFG */
 731                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 732                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 733                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 734                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 735                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 736                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 737                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 738                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 739                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 740                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 741                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 742                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 743                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 744                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 745                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 746                                 0x75830303 /* MC_EMEM_ARB_MISC0 */
 747                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 748                         >;
 749                 };
 750                 timing-51000000 {
 751                         clock-frequency = <51000000>;
 752                         nvidia,emem-configuration = <
 753                                 0x00010003 /* MC_EMEM_ARB_CFG */
 754                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 755                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 756                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 757                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 758                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 759                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 760                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 761                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 762                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 763                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 764                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 765                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 766                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 767                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 768                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 769                                 0x74630303 /* MC_EMEM_ARB_MISC0 */
 770                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 771                         >;
 772                 };
 773                 timing-102000000 {
 774                         clock-frequency = <102000000>;
 775                         nvidia,emem-configuration = <
 776                                 0x00000003 /* MC_EMEM_ARB_CFG */
 777                                 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 778                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 779                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 780                                 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 781                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 782                                 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 783                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 784                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 785                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 786                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 787                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 788                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 789                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 790                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 791                                 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 792                                 0x73c30504 /* MC_EMEM_ARB_MISC0 */
 793                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 794                         >;
 795                 };
 796                 timing-204000000 {
 797                         clock-frequency = <204000000>;
 798                         nvidia,emem-configuration = <
 799                                 0x00000006 /* MC_EMEM_ARB_CFG */
 800                                 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 801                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 802                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 803                                 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 804                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 805                                 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 806                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 807                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 808                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 809                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 810                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 811                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 812                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 813                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 814                                 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 815                                 0x73840a06 /* MC_EMEM_ARB_MISC0 */
 816                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 817                         >;
 818                 };
 819                 timing-400000000 {
 820                         clock-frequency = <400000000>;
 821                         nvidia,emem-configuration = <
 822                                 0x0000000c /* MC_EMEM_ARB_CFG */
 823                                 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 824                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 825                                 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 826                                 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 827                                 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 828                                 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 829                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 830                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 831                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 832                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 833                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 834                                 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 835                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 836                                 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 837                                 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 838                                 0x7086120a /* MC_EMEM_ARB_MISC0 */
 839                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 840                         >;
 841                 };
 842                 timing-800000000 {
 843                         clock-frequency = <800000000>;
 844                         nvidia,emem-configuration = <
 845                                 0x00000018 /* MC_EMEM_ARB_CFG */
 846                                 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 847                                 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 848                                 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
 849                                 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
 850                                 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
 851                                 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
 852                                 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
 853                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 854                                 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
 855                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 856                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 857                                 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
 858                                 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
 859                                 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
 860                                 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
 861                                 0x712c2414 /* MC_EMEM_ARB_MISC0 */
 862                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 863                         >;
 864                 };
 865         };
 866         emc-timings-2 {
 867                 nvidia,ram-code = <2>; /* Hynix A RAM */
 868                 timing-25500000 {
 869                         clock-frequency = <25500000>;
 870                         nvidia,emem-configuration = <
 871                                 0x00030003 /* MC_EMEM_ARB_CFG */
 872                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 873                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 874                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 875                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 876                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 877                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 878                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 879                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 880                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 881                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 882                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 883                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 884                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 885                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 886                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 887                                 0x75e30303 /* MC_EMEM_ARB_MISC0 */
 888                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 889                         >;
 890                 };
 891                 timing-51000000 {
 892                         clock-frequency = <51000000>;
 893                         nvidia,emem-configuration = <
 894                                 0x00010003 /* MC_EMEM_ARB_CFG */
 895                                 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 896                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 897                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 898                                 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 899                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 900                                 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 901                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 902                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 903                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 904                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 905                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 906                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 907                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 908                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 909                                 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 910                                 0x74e30303 /* MC_EMEM_ARB_MISC0 */
 911                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 912                         >;
 913                 };
 914                 timing-102000000 {
 915                         clock-frequency = <102000000>;
 916                         nvidia,emem-configuration = <
 917                                 0x00000003 /* MC_EMEM_ARB_CFG */
 918                                 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 919                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 920                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 921                                 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 922                                 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 923                                 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 924                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 925                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 926                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 927                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 928                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 929                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 930                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 931                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 932                                 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 933                                 0x74430504 /* MC_EMEM_ARB_MISC0 */
 934                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 935                         >;
 936                 };
 937                 timing-204000000 {
 938                         clock-frequency = <204000000>;
 939                         nvidia,emem-configuration = <
 940                                 0x00000006 /* MC_EMEM_ARB_CFG */
 941                                 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 942                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 943                                 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 944                                 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 945                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 946                                 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 947                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 948                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 949                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 950                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 951                                 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 952                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 953                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 954                                 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 955                                 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 956                                 0x74040a06 /* MC_EMEM_ARB_MISC0 */
 957                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 958                         >;
 959                 };
 960                 timing-400000000 {
 961                         clock-frequency = <400000000>;
 962                         nvidia,emem-configuration = <
 963                                 0x0000000c /* MC_EMEM_ARB_CFG */
 964                                 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 965                                 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 966                                 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 967                                 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 968                                 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 969                                 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 970                                 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 971                                 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 972                                 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 973                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 974                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 975                                 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 976                                 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 977                                 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 978                                 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 979                                 0x7086120a /* MC_EMEM_ARB_MISC0 */
 980                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 981                         >;
 982                 };
 983                 timing-800000000 {
 984                         clock-frequency = <800000000>;
 985                         nvidia,emem-configuration = <
 986                                 0x00000018 /* MC_EMEM_ARB_CFG */
 987                                 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 988                                 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 989                                 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
 990                                 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
 991                                 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
 992                                 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
 993                                 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
 994                                 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 995                                 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
 996                                 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 997                                 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 998                                 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
 999                                 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
1000                                 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
1001                                 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
1002                                 0x712c2414 /* MC_EMEM_ARB_MISC0 */
1003                                 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
1004                         >;
1005                 };
1006         };
1007 };
1008 &emc_timings {
1009         emc-timings-0 {
1010                 nvidia,ram-code = <0>;  /* Samsung RAM */
1011                 timing-25500000 {
1012                         clock-frequency = <25500000>;
1013                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1014                         nvidia,emc-mode-1 = <0x80100003>;
1015                         nvidia,emc-mode-2 = <0x80200008>;
1016                         nvidia,emc-mode-reset = <0x80001221>;
1017                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1018                         nvidia,emc-cfg-periodic-qrst;
1019                         nvidia,emc-cfg-dyn-self-ref;
1020                         nvidia,emc-configuration = <
1021                                 0x00000001 /* EMC_RC */
1022                                 0x00000006 /* EMC_RFC */
1023                                 0x00000000 /* EMC_RAS */
1024                                 0x00000000 /* EMC_RP */
1025                                 0x00000002 /* EMC_R2W */
1026                                 0x0000000a /* EMC_W2R */
1027                                 0x00000005 /* EMC_R2P */
1028                                 0x0000000b /* EMC_W2P */
1029                                 0x00000000 /* EMC_RD_RCD */
1030                                 0x00000000 /* EMC_WR_RCD */
1031                                 0x00000003 /* EMC_RRD */
1032                                 0x00000001 /* EMC_REXT */
1033                                 0x00000000 /* EMC_WEXT */
1034                                 0x00000005 /* EMC_WDV */
1035                                 0x00000005 /* EMC_QUSE */
1036                                 0x00000004 /* EMC_QRST */
1037                                 0x0000000a /* EMC_QSAFE */
1038                                 0x0000000b /* EMC_RDV */
1039                                 0x000000c0 /* EMC_REFRESH */
1040                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1041                                 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
1042                                 0x00000002 /* EMC_PDEX2WR */
1043                                 0x00000002 /* EMC_PDEX2RD */
1044                                 0x00000001 /* EMC_PCHG2PDEN */
1045                                 0x00000000 /* EMC_ACT2PDEN */
1046                                 0x00000007 /* EMC_AR2PDEN */
1047                                 0x0000000f /* EMC_RW2PDEN */
1048                                 0x00000007 /* EMC_TXSR */
1049                                 0x00000007 /* EMC_TXSRDLL */
1050                                 0x00000004 /* EMC_TCKE */
1051                                 0x00000002 /* EMC_TFAW */
1052                                 0x00000000 /* EMC_TRPAB */
1053                                 0x00000004 /* EMC_TCLKSTABLE */
1054                                 0x00000005 /* EMC_TCLKSTOP */
1055                                 0x000000c7 /* EMC_TREFBW */
1056                                 0x00000006 /* EMC_QUSE_EXTRA */
1057                                 0x00000004 /* EMC_FBIO_CFG6 */
1058                                 0x00000000 /* EMC_ODT_WRITE */
1059                                 0x00000000 /* EMC_ODT_READ */
1060                                 0x00004288 /* EMC_FBIO_CFG5 */
1061                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1062                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1063                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1064                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1065                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1066                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1067                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1068                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1069                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1070                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1071                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1072                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1073                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1074                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1075                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1076                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1077                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1078                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1079                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1080                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1081                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1082                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1083                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1084                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1085                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1086                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1087                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1088                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1089                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1090                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1091                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1092                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1093                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1094                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1095                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1096                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1097                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1098                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1099                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1100                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1101                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1102                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1103                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1104                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1105                                 0x00000000 /* EMC_CTT */
1106                                 0x00000000 /* EMC_CTT_DURATION */
1107                                 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
1108                                 0xe8000000 /* EMC_FBIO_SPARE */
1109                                 0xff00ff00 /* EMC_CFG_RSV */
1110                         >;
1111                 };
1112                 timing-51000000 {
1113                         clock-frequency = <51000000>;
1114                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1115                         nvidia,emc-mode-1 = <0x80100003>;
1116                         nvidia,emc-mode-2 = <0x80200008>;
1117                         nvidia,emc-mode-reset = <0x80001221>;
1118                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1119                         nvidia,emc-cfg-periodic-qrst;
1120                         nvidia,emc-cfg-dyn-self-ref;
1121                         nvidia,emc-configuration = <
1122                                 0x00000002 /* EMC_RC */
1123                                 0x0000000d /* EMC_RFC */
1124                                 0x00000001 /* EMC_RAS */
1125                                 0x00000000 /* EMC_RP */
1126                                 0x00000002 /* EMC_R2W */
1127                                 0x0000000a /* EMC_W2R */
1128                                 0x00000005 /* EMC_R2P */
1129                                 0x0000000b /* EMC_W2P */
1130                                 0x00000000 /* EMC_RD_RCD */
1131                                 0x00000000 /* EMC_WR_RCD */
1132                                 0x00000003 /* EMC_RRD */
1133                                 0x00000001 /* EMC_REXT */
1134                                 0x00000000 /* EMC_WEXT */
1135                                 0x00000005 /* EMC_WDV */
1136                                 0x00000005 /* EMC_QUSE */
1137                                 0x00000004 /* EMC_QRST */
1138                                 0x0000000a /* EMC_QSAFE */
1139                                 0x0000000b /* EMC_RDV */
1140                                 0x00000181 /* EMC_REFRESH */
1141                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1142                                 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
1143                                 0x00000002 /* EMC_PDEX2WR */
1144                                 0x00000002 /* EMC_PDEX2RD */
1145                                 0x00000001 /* EMC_PCHG2PDEN */
1146                                 0x00000000 /* EMC_ACT2PDEN */
1147                                 0x00000007 /* EMC_AR2PDEN */
1148                                 0x0000000f /* EMC_RW2PDEN */
1149                                 0x0000000e /* EMC_TXSR */
1150                                 0x0000000e /* EMC_TXSRDLL */
1151                                 0x00000004 /* EMC_TCKE */
1152                                 0x00000003 /* EMC_TFAW */
1153                                 0x00000000 /* EMC_TRPAB */
1154                                 0x00000004 /* EMC_TCLKSTABLE */
1155                                 0x00000005 /* EMC_TCLKSTOP */
1156                                 0x0000018e /* EMC_TREFBW */
1157                                 0x00000006 /* EMC_QUSE_EXTRA */
1158                                 0x00000004 /* EMC_FBIO_CFG6 */
1159                                 0x00000000 /* EMC_ODT_WRITE */
1160                                 0x00000000 /* EMC_ODT_READ */
1161                                 0x00004288 /* EMC_FBIO_CFG5 */
1162                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1163                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1164                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1165                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1166                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1167                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1168                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1169                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1170                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1171                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1172                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1173                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1174                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1175                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1176                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1177                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1178                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1179                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1180                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1181                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1182                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1183                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1184                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1185                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1186                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1187                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1188                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1189                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1190                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1191                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1192                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1193                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1194                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1195                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1196                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1197                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1198                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1199                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1200                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1201                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1202                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1203                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1204                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1205                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1206                                 0x00000000 /* EMC_CTT */
1207                                 0x00000000 /* EMC_CTT_DURATION */
1208                                 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
1209                                 0xe8000000 /* EMC_FBIO_SPARE */
1210                                 0xff00ff00 /* EMC_CFG_RSV */
1211                         >;
1212                 };
1213                 timing-102000000 {
1214                         clock-frequency = <102000000>;
1215                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1216                         nvidia,emc-mode-1 = <0x80100003>;
1217                         nvidia,emc-mode-2 = <0x80200008>;
1218                         nvidia,emc-mode-reset = <0x80001221>;
1219                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1220                         nvidia,emc-cfg-periodic-qrst;
1221                         nvidia,emc-cfg-dyn-self-ref;
1222                         nvidia,emc-configuration = <
1223                                 0x00000004 /* EMC_RC */
1224                                 0x0000001a /* EMC_RFC */
1225                                 0x00000003 /* EMC_RAS */
1226                                 0x00000001 /* EMC_RP */
1227                                 0x00000002 /* EMC_R2W */
1228                                 0x0000000a /* EMC_W2R */
1229                                 0x00000005 /* EMC_R2P */
1230                                 0x0000000b /* EMC_W2P */
1231                                 0x00000001 /* EMC_RD_RCD */
1232                                 0x00000001 /* EMC_WR_RCD */
1233                                 0x00000003 /* EMC_RRD */
1234                                 0x00000001 /* EMC_REXT */
1235                                 0x00000000 /* EMC_WEXT */
1236                                 0x00000005 /* EMC_WDV */
1237                                 0x00000005 /* EMC_QUSE */
1238                                 0x00000004 /* EMC_QRST */
1239                                 0x0000000a /* EMC_QSAFE */
1240                                 0x0000000b /* EMC_RDV */
1241                                 0x00000303 /* EMC_REFRESH */
1242                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1243                                 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
1244                                 0x00000002 /* EMC_PDEX2WR */
1245                                 0x00000002 /* EMC_PDEX2RD */
1246                                 0x00000001 /* EMC_PCHG2PDEN */
1247                                 0x00000000 /* EMC_ACT2PDEN */
1248                                 0x00000007 /* EMC_AR2PDEN */
1249                                 0x0000000f /* EMC_RW2PDEN */
1250                                 0x0000001c /* EMC_TXSR */
1251                                 0x0000001c /* EMC_TXSRDLL */
1252                                 0x00000004 /* EMC_TCKE */
1253                                 0x00000005 /* EMC_TFAW */
1254                                 0x00000000 /* EMC_TRPAB */
1255                                 0x00000004 /* EMC_TCLKSTABLE */
1256                                 0x00000005 /* EMC_TCLKSTOP */
1257                                 0x0000031c /* EMC_TREFBW */
1258                                 0x00000006 /* EMC_QUSE_EXTRA */
1259                                 0x00000004 /* EMC_FBIO_CFG6 */
1260                                 0x00000000 /* EMC_ODT_WRITE */
1261                                 0x00000000 /* EMC_ODT_READ */
1262                                 0x00004288 /* EMC_FBIO_CFG5 */
1263                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1264                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1265                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1266                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1267                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1268                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1269                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1270                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1271                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1272                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1273                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1274                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1275                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1276                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1277                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1278                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1279                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1280                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1281                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1282                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1283                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1284                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1285                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1286                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1287                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1288                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1289                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1290                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1291                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1292                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1293                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1294                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1295                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1296                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1297                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1298                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1299                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1300                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1301                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1302                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1303                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1304                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1305                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1306                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1307                                 0x00000000 /* EMC_CTT */
1308                                 0x00000000 /* EMC_CTT_DURATION */
1309                                 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
1310                                 0xe8000000 /* EMC_FBIO_SPARE */
1311                                 0xff00ff00 /* EMC_CFG_RSV */
1312                         >;
1313                 };
1314                 timing-204000000 {
1315                         clock-frequency = <204000000>;
1316                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1317                         nvidia,emc-mode-1 = <0x80100003>;
1318                         nvidia,emc-mode-2 = <0x80200008>;
1319                         nvidia,emc-mode-reset = <0x80001221>;
1320                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1321                         nvidia,emc-cfg-periodic-qrst;
1322                         nvidia,emc-cfg-dyn-self-ref;
1323                         nvidia,emc-configuration = <
1324                                 0x00000009 /* EMC_RC */
1325                                 0x00000035 /* EMC_RFC */
1326                                 0x00000007 /* EMC_RAS */
1327                                 0x00000002 /* EMC_RP */
1328                                 0x00000002 /* EMC_R2W */
1329                                 0x0000000a /* EMC_W2R */
1330                                 0x00000005 /* EMC_R2P */
1331                                 0x0000000b /* EMC_W2P */
1332                                 0x00000002 /* EMC_RD_RCD */
1333                                 0x00000002 /* EMC_WR_RCD */
1334                                 0x00000003 /* EMC_RRD */
1335                                 0x00000001 /* EMC_REXT */
1336                                 0x00000000 /* EMC_WEXT */
1337                                 0x00000005 /* EMC_WDV */
1338                                 0x00000005 /* EMC_QUSE */
1339                                 0x00000004 /* EMC_QRST */
1340                                 0x0000000a /* EMC_QSAFE */
1341                                 0x0000000b /* EMC_RDV */
1342                                 0x00000607 /* EMC_REFRESH */
1343                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1344                                 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
1345                                 0x00000002 /* EMC_PDEX2WR */
1346                                 0x00000002 /* EMC_PDEX2RD */
1347                                 0x00000001 /* EMC_PCHG2PDEN */
1348                                 0x00000000 /* EMC_ACT2PDEN */
1349                                 0x00000007 /* EMC_AR2PDEN */
1350                                 0x0000000f /* EMC_RW2PDEN */
1351                                 0x00000038 /* EMC_TXSR */
1352                                 0x00000038 /* EMC_TXSRDLL */
1353                                 0x00000004 /* EMC_TCKE */
1354                                 0x00000009 /* EMC_TFAW */
1355                                 0x00000000 /* EMC_TRPAB */
1356                                 0x00000004 /* EMC_TCLKSTABLE */
1357                                 0x00000005 /* EMC_TCLKSTOP */
1358                                 0x00000638 /* EMC_TREFBW */
1359                                 0x00000006 /* EMC_QUSE_EXTRA */
1360                                 0x00000006 /* EMC_FBIO_CFG6 */
1361                                 0x00000000 /* EMC_ODT_WRITE */
1362                                 0x00000000 /* EMC_ODT_READ */
1363                                 0x00004288 /* EMC_FBIO_CFG5 */
1364                                 0x004400a4 /* EMC_CFG_DIG_DLL */
1365                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1366                                 0x00080000 /* EMC_DLL_XFORM_DQS0 */
1367                                 0x00080000 /* EMC_DLL_XFORM_DQS1 */
1368                                 0x00080000 /* EMC_DLL_XFORM_DQS2 */
1369                                 0x00080000 /* EMC_DLL_XFORM_DQS3 */
1370                                 0x00080000 /* EMC_DLL_XFORM_DQS4 */
1371                                 0x00080000 /* EMC_DLL_XFORM_DQS5 */
1372                                 0x00080000 /* EMC_DLL_XFORM_DQS6 */
1373                                 0x00080000 /* EMC_DLL_XFORM_DQS7 */
1374                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1375                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1376                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1377                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1378                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1379                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1380                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1381                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1382                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1383                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1384                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1385                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1386                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1387                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1388                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1389                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1390                                 0x00080000 /* EMC_DLL_XFORM_DQ0 */
1391                                 0x00080000 /* EMC_DLL_XFORM_DQ1 */
1392                                 0x00080000 /* EMC_DLL_XFORM_DQ2 */
1393                                 0x00080000 /* EMC_DLL_XFORM_DQ3 */
1394                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1395                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1396                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1397                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1398                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1399                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1400                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1401                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1402                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1403                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1404                                 0x00020000 /* EMC_ZCAL_INTERVAL */
1405                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
1406                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1407                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1408                                 0x00000000 /* EMC_CTT */
1409                                 0x00000000 /* EMC_CTT_DURATION */
1410                                 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
1411                                 0xe8000000 /* EMC_FBIO_SPARE */
1412                                 0xff00ff00 /* EMC_CFG_RSV */
1413                         >;
1414                 };
1415                 timing-400000000 {
1416                         clock-frequency = <400000000>;
1417                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1418                         nvidia,emc-mode-1 = <0x80100002>;
1419                         nvidia,emc-mode-2 = <0x80200000>;
1420                         nvidia,emc-mode-reset = <0x80000521>;
1421                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1422                         nvidia,emc-configuration = <
1423                                 0x00000012 /* EMC_RC */
1424                                 0x00000066 /* EMC_RFC */
1425                                 0x0000000c /* EMC_RAS */
1426                                 0x00000004 /* EMC_RP */
1427                                 0x00000003 /* EMC_R2W */
1428                                 0x00000008 /* EMC_W2R */
1429                                 0x00000002 /* EMC_R2P */
1430                                 0x0000000a /* EMC_W2P */
1431                                 0x00000004 /* EMC_RD_RCD */
1432                                 0x00000004 /* EMC_WR_RCD */
1433                                 0x00000002 /* EMC_RRD */
1434                                 0x00000001 /* EMC_REXT */
1435                                 0x00000000 /* EMC_WEXT */
1436                                 0x00000004 /* EMC_WDV */
1437                                 0x00000006 /* EMC_QUSE */
1438                                 0x00000004 /* EMC_QRST */
1439                                 0x0000000a /* EMC_QSAFE */
1440                                 0x0000000c /* EMC_RDV */
1441                                 0x00000bf0 /* EMC_REFRESH */
1442                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1443                                 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
1444                                 0x00000001 /* EMC_PDEX2WR */
1445                                 0x00000008 /* EMC_PDEX2RD */
1446                                 0x00000001 /* EMC_PCHG2PDEN */
1447                                 0x00000000 /* EMC_ACT2PDEN */
1448                                 0x00000008 /* EMC_AR2PDEN */
1449                                 0x0000000f /* EMC_RW2PDEN */
1450                                 0x0000006c /* EMC_TXSR */
1451                                 0x00000200 /* EMC_TXSRDLL */
1452                                 0x00000004 /* EMC_TCKE */
1453                                 0x00000010 /* EMC_TFAW */
1454                                 0x00000000 /* EMC_TRPAB */
1455                                 0x00000004 /* EMC_TCLKSTABLE */
1456                                 0x00000005 /* EMC_TCLKSTOP */
1457                                 0x00000c30 /* EMC_TREFBW */
1458                                 0x00000000 /* EMC_QUSE_EXTRA */
1459                                 0x00000004 /* EMC_FBIO_CFG6 */
1460                                 0x00000000 /* EMC_ODT_WRITE */
1461                                 0x00000000 /* EMC_ODT_READ */
1462                                 0x00007088 /* EMC_FBIO_CFG5 */
1463                                 0x001d0084 /* EMC_CFG_DIG_DLL */
1464                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1465                                 0x0003c000 /* EMC_DLL_XFORM_DQS0 */
1466                                 0x0003c000 /* EMC_DLL_XFORM_DQS1 */
1467                                 0x0003c000 /* EMC_DLL_XFORM_DQS2 */
1468                                 0x0003c000 /* EMC_DLL_XFORM_DQS3 */
1469                                 0x0003c000 /* EMC_DLL_XFORM_DQS4 */
1470                                 0x0003c000 /* EMC_DLL_XFORM_DQS5 */
1471                                 0x0003c000 /* EMC_DLL_XFORM_DQS6 */
1472                                 0x0003c000 /* EMC_DLL_XFORM_DQS7 */
1473                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1474                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1475                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1476                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1477                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1478                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1479                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1480                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1481                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1482                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1483                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1484                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1485                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1486                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1487                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1488                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1489                                 0x00048000 /* EMC_DLL_XFORM_DQ0 */
1490                                 0x00048000 /* EMC_DLL_XFORM_DQ1 */
1491                                 0x00048000 /* EMC_DLL_XFORM_DQ2 */
1492                                 0x00048000 /* EMC_DLL_XFORM_DQ3 */
1493                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1494                                 0x0800013d /* EMC_XM2DQSPADCTRL2 */
1495                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1496                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1497                                 0x01f1f508 /* EMC_XM2COMPPADCTRL */
1498                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1499                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1500                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
1501                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
1502                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1503                                 0x00020000 /* EMC_ZCAL_INTERVAL */
1504                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
1505                                 0x0158000c /* EMC_MRS_WAIT_CNT */
1506                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1507                                 0x00000000 /* EMC_CTT */
1508                                 0x00000000 /* EMC_CTT_DURATION */
1509                                 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
1510                                 0xe8000000 /* EMC_FBIO_SPARE */
1511                                 0xff00ff89 /* EMC_CFG_RSV */
1512                         >;
1513                 };
1514                 timing-800000000 {
1515                         clock-frequency = <800000000>;
1516                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1517                         nvidia,emc-mode-1 = <0x80100002>;
1518                         nvidia,emc-mode-2 = <0x80200018>;
1519                         nvidia,emc-mode-reset = <0x80000d71>;
1520                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1521                         nvidia,emc-cfg-periodic-qrst;
1522                         nvidia,emc-configuration = <
1523                                 0x00000025 /* EMC_RC */
1524                                 0x000000ce /* EMC_RFC */
1525                                 0x0000001a /* EMC_RAS */
1526                                 0x00000009 /* EMC_RP */
1527                                 0x00000005 /* EMC_R2W */
1528                                 0x0000000d /* EMC_W2R */
1529                                 0x00000004 /* EMC_R2P */
1530                                 0x00000013 /* EMC_W2P */
1531                                 0x00000009 /* EMC_RD_RCD */
1532                                 0x00000009 /* EMC_WR_RCD */
1533                                 0x00000004 /* EMC_RRD */
1534                                 0x00000001 /* EMC_REXT */
1535                                 0x00000000 /* EMC_WEXT */
1536                                 0x00000007 /* EMC_WDV */
1537                                 0x0000000a /* EMC_QUSE */
1538                                 0x00000009 /* EMC_QRST */
1539                                 0x0000000b /* EMC_QSAFE */
1540                                 0x00000011 /* EMC_RDV */
1541                                 0x00001820 /* EMC_REFRESH */
1542                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1543                                 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
1544                                 0x00000003 /* EMC_PDEX2WR */
1545                                 0x00000012 /* EMC_PDEX2RD */
1546                                 0x00000001 /* EMC_PCHG2PDEN */
1547                                 0x00000000 /* EMC_ACT2PDEN */
1548                                 0x0000000f /* EMC_AR2PDEN */
1549                                 0x00000018 /* EMC_RW2PDEN */
1550                                 0x000000d8 /* EMC_TXSR */
1551                                 0x00000200 /* EMC_TXSRDLL */
1552                                 0x00000005 /* EMC_TCKE */
1553                                 0x00000020 /* EMC_TFAW */
1554                                 0x00000000 /* EMC_TRPAB */
1555                                 0x00000007 /* EMC_TCLKSTABLE */
1556                                 0x00000008 /* EMC_TCLKSTOP */
1557                                 0x00001860 /* EMC_TREFBW */
1558                                 0x0000000b /* EMC_QUSE_EXTRA */
1559                                 0x00000006 /* EMC_FBIO_CFG6 */
1560                                 0x00000000 /* EMC_ODT_WRITE */
1561                                 0x00000000 /* EMC_ODT_READ */
1562                                 0x00005088 /* EMC_FBIO_CFG5 */
1563                                 0xf0070191 /* EMC_CFG_DIG_DLL */
1564                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1565                                 0x0000800a /* EMC_DLL_XFORM_DQS0 */
1566                                 0x0000000a /* EMC_DLL_XFORM_DQS1 */
1567                                 0x0000000a /* EMC_DLL_XFORM_DQS2 */
1568                                 0x0000000a /* EMC_DLL_XFORM_DQS3 */
1569                                 0x0000000a /* EMC_DLL_XFORM_DQS4 */
1570                                 0x0000000a /* EMC_DLL_XFORM_DQS5 */
1571                                 0x0000000a /* EMC_DLL_XFORM_DQS6 */
1572                                 0x0000000a /* EMC_DLL_XFORM_DQS7 */
1573                                 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
1574                                 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
1575                                 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
1576                                 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
1577                                 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
1578                                 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
1579                                 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
1580                                 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
1581                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1582                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1583                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1584                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1585                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1586                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1587                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1588                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1589                                 0x0000000a /* EMC_DLL_XFORM_DQ0 */
1590                                 0x0000000a /* EMC_DLL_XFORM_DQ1 */
1591                                 0x0000000a /* EMC_DLL_XFORM_DQ2 */
1592                                 0x0000000a /* EMC_DLL_XFORM_DQ3 */
1593                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1594                                 0x0600013d /* EMC_XM2DQSPADCTRL2 */
1595                                 0x22220000 /* EMC_XM2DQPADCTRL2 */
1596                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1597                                 0x01f1f501 /* EMC_XM2COMPPADCTRL */
1598                                 0x07077404 /* EMC_XM2VTTGENPADCTRL */
1599                                 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
1600                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
1601                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
1602                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1603                                 0x00020000 /* EMC_ZCAL_INTERVAL */
1604                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
1605                                 0x00f0000c /* EMC_MRS_WAIT_CNT */
1606                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1607                                 0x00000000 /* EMC_CTT */
1608                                 0x00000000 /* EMC_CTT_DURATION */
1609                                 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
1610                                 0xe8000000 /* EMC_FBIO_SPARE */
1611                                 0xff00ff49 /* EMC_CFG_RSV */
1612                         >;
1613                 };
1614         };
1615         emc-timings-1 {
1616                 nvidia,ram-code = <1>;  /* Hynix M RAM */
1617                 timing-25500000 {
1618                         clock-frequency = <25500000>;
1619                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1620                         nvidia,emc-mode-1 = <0x80100003>;
1621                         nvidia,emc-mode-2 = <0x80200008>;
1622                         nvidia,emc-mode-reset = <0x80001221>;
1623                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1624                         nvidia,emc-cfg-periodic-qrst;
1625                         nvidia,emc-cfg-dyn-self-ref;
1626                         nvidia,emc-configuration = <
1627                                 0x00000001 /* EMC_RC */
1628                                 0x00000006 /* EMC_RFC */
1629                                 0x00000000 /* EMC_RAS */
1630                                 0x00000000 /* EMC_RP */
1631                                 0x00000002 /* EMC_R2W */
1632                                 0x0000000a /* EMC_W2R */
1633                                 0x00000005 /* EMC_R2P */
1634                                 0x0000000b /* EMC_W2P */
1635                                 0x00000000 /* EMC_RD_RCD */
1636                                 0x00000000 /* EMC_WR_RCD */
1637                                 0x00000003 /* EMC_RRD */
1638                                 0x00000001 /* EMC_REXT */
1639                                 0x00000000 /* EMC_WEXT */
1640                                 0x00000005 /* EMC_WDV */
1641                                 0x00000005 /* EMC_QUSE */
1642                                 0x00000004 /* EMC_QRST */
1643                                 0x0000000a /* EMC_QSAFE */
1644                                 0x0000000b /* EMC_RDV */
1645                                 0x000000c0 /* EMC_REFRESH */
1646                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1647                                 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
1648                                 0x00000002 /* EMC_PDEX2WR */
1649                                 0x00000002 /* EMC_PDEX2RD */
1650                                 0x00000001 /* EMC_PCHG2PDEN */
1651                                 0x00000000 /* EMC_ACT2PDEN */
1652                                 0x00000007 /* EMC_AR2PDEN */
1653                                 0x0000000f /* EMC_RW2PDEN */
1654                                 0x00000007 /* EMC_TXSR */
1655                                 0x00000007 /* EMC_TXSRDLL */
1656                                 0x00000004 /* EMC_TCKE */
1657                                 0x00000002 /* EMC_TFAW */
1658                                 0x00000000 /* EMC_TRPAB */
1659                                 0x00000004 /* EMC_TCLKSTABLE */
1660                                 0x00000005 /* EMC_TCLKSTOP */
1661                                 0x000000c7 /* EMC_TREFBW */
1662                                 0x00000006 /* EMC_QUSE_EXTRA */
1663                                 0x00000004 /* EMC_FBIO_CFG6 */
1664                                 0x00000000 /* EMC_ODT_WRITE */
1665                                 0x00000000 /* EMC_ODT_READ */
1666                                 0x00004288 /* EMC_FBIO_CFG5 */
1667                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1668                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1669                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1670                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1671                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1672                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1673                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1674                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1675                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1676                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1677                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1678                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1679                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1680                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1681                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1682                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1683                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1684                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1685                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1686                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1687                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1688                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1689                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1690                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1691                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1692                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1693                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1694                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1695                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1696                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1697                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1698                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1699                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1700                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1701                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1702                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1703                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1704                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1705                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1706                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1707                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1708                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1709                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1710                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1711                                 0x00000000 /* EMC_CTT */
1712                                 0x00000000 /* EMC_CTT_DURATION */
1713                                 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
1714                                 0xe8000000 /* EMC_FBIO_SPARE */
1715                                 0xff00ff00 /* EMC_CFG_RSV */
1716                         >;
1717                 };
1718                 timing-51000000 {
1719                         clock-frequency = <51000000>;
1720                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1721                         nvidia,emc-mode-1 = <0x80100003>;
1722                         nvidia,emc-mode-2 = <0x80200008>;
1723                         nvidia,emc-mode-reset = <0x80001221>;
1724                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1725                         nvidia,emc-cfg-periodic-qrst;
1726                         nvidia,emc-cfg-dyn-self-ref;
1727                         nvidia,emc-configuration = <
1728                                 0x00000002 /* EMC_RC */
1729                                 0x0000000d /* EMC_RFC */
1730                                 0x00000001 /* EMC_RAS */
1731                                 0x00000000 /* EMC_RP */
1732                                 0x00000002 /* EMC_R2W */
1733                                 0x0000000a /* EMC_W2R */
1734                                 0x00000005 /* EMC_R2P */
1735                                 0x0000000b /* EMC_W2P */
1736                                 0x00000000 /* EMC_RD_RCD */
1737                                 0x00000000 /* EMC_WR_RCD */
1738                                 0x00000003 /* EMC_RRD */
1739                                 0x00000001 /* EMC_REXT */
1740                                 0x00000000 /* EMC_WEXT */
1741                                 0x00000005 /* EMC_WDV */
1742                                 0x00000005 /* EMC_QUSE */
1743                                 0x00000004 /* EMC_QRST */
1744                                 0x0000000a /* EMC_QSAFE */
1745                                 0x0000000b /* EMC_RDV */
1746                                 0x00000181 /* EMC_REFRESH */
1747                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1748                                 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
1749                                 0x00000002 /* EMC_PDEX2WR */
1750                                 0x00000002 /* EMC_PDEX2RD */
1751                                 0x00000001 /* EMC_PCHG2PDEN */
1752                                 0x00000000 /* EMC_ACT2PDEN */
1753                                 0x00000007 /* EMC_AR2PDEN */
1754                                 0x0000000f /* EMC_RW2PDEN */
1755                                 0x0000000e /* EMC_TXSR */
1756                                 0x0000000e /* EMC_TXSRDLL */
1757                                 0x00000004 /* EMC_TCKE */
1758                                 0x00000003 /* EMC_TFAW */
1759                                 0x00000000 /* EMC_TRPAB */
1760                                 0x00000004 /* EMC_TCLKSTABLE */
1761                                 0x00000005 /* EMC_TCLKSTOP */
1762                                 0x0000018e /* EMC_TREFBW */
1763                                 0x00000006 /* EMC_QUSE_EXTRA */
1764                                 0x00000004 /* EMC_FBIO_CFG6 */
1765                                 0x00000000 /* EMC_ODT_WRITE */
1766                                 0x00000000 /* EMC_ODT_READ */
1767                                 0x00004288 /* EMC_FBIO_CFG5 */
1768                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1769                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1770                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1771                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1772                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1773                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1774                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1775                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1776                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1777                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1778                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1779                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1780                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1781                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1782                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1783                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1784                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1785                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1786                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1787                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1788                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1789                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1790                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1791                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1792                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1793                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1794                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1795                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1796                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1797                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1798                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1799                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1800                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1801                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1802                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1803                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1804                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1805                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1806                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1807                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1808                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1809                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1810                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1811                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1812                                 0x00000000 /* EMC_CTT */
1813                                 0x00000000 /* EMC_CTT_DURATION */
1814                                 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
1815                                 0xe8000000 /* EMC_FBIO_SPARE */
1816                                 0xff00ff00 /* EMC_CFG_RSV */
1817                         >;
1818                 };
1819                 timing-102000000 {
1820                         clock-frequency = <102000000>;
1821                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1822                         nvidia,emc-mode-1 = <0x80100003>;
1823                         nvidia,emc-mode-2 = <0x80200008>;
1824                         nvidia,emc-mode-reset = <0x80001221>;
1825                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1826                         nvidia,emc-cfg-periodic-qrst;
1827                         nvidia,emc-cfg-dyn-self-ref;
1828                         nvidia,emc-configuration = <
1829                                 0x00000004 /* EMC_RC */
1830                                 0x0000001a /* EMC_RFC */
1831                                 0x00000003 /* EMC_RAS */
1832                                 0x00000001 /* EMC_RP */
1833                                 0x00000002 /* EMC_R2W */
1834                                 0x0000000a /* EMC_W2R */
1835                                 0x00000005 /* EMC_R2P */
1836                                 0x0000000b /* EMC_W2P */
1837                                 0x00000001 /* EMC_RD_RCD */
1838                                 0x00000001 /* EMC_WR_RCD */
1839                                 0x00000003 /* EMC_RRD */
1840                                 0x00000001 /* EMC_REXT */
1841                                 0x00000000 /* EMC_WEXT */
1842                                 0x00000005 /* EMC_WDV */
1843                                 0x00000005 /* EMC_QUSE */
1844                                 0x00000004 /* EMC_QRST */
1845                                 0x0000000a /* EMC_QSAFE */
1846                                 0x0000000b /* EMC_RDV */
1847                                 0x00000303 /* EMC_REFRESH */
1848                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1849                                 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
1850                                 0x00000002 /* EMC_PDEX2WR */
1851                                 0x00000002 /* EMC_PDEX2RD */
1852                                 0x00000001 /* EMC_PCHG2PDEN */
1853                                 0x00000000 /* EMC_ACT2PDEN */
1854                                 0x00000007 /* EMC_AR2PDEN */
1855                                 0x0000000f /* EMC_RW2PDEN */
1856                                 0x0000001c /* EMC_TXSR */
1857                                 0x0000001c /* EMC_TXSRDLL */
1858                                 0x00000004 /* EMC_TCKE */
1859                                 0x00000005 /* EMC_TFAW */
1860                                 0x00000000 /* EMC_TRPAB */
1861                                 0x00000004 /* EMC_TCLKSTABLE */
1862                                 0x00000005 /* EMC_TCLKSTOP */
1863                                 0x0000031c /* EMC_TREFBW */
1864                                 0x00000006 /* EMC_QUSE_EXTRA */
1865                                 0x00000004 /* EMC_FBIO_CFG6 */
1866                                 0x00000000 /* EMC_ODT_WRITE */
1867                                 0x00000000 /* EMC_ODT_READ */
1868                                 0x00004288 /* EMC_FBIO_CFG5 */
1869                                 0x007800a4 /* EMC_CFG_DIG_DLL */
1870                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1871                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
1872                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
1873                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
1874                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
1875                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
1876                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
1877                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
1878                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
1879                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1880                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1881                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1882                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1883                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1884                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1885                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1886                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1887                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1888                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1889                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1890                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1891                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1892                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1893                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1894                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1895                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
1896                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
1897                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
1898                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
1899                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
1900                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
1901                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
1902                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
1903                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
1904                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
1905                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
1906                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
1907                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1908                                 0x00000802 /* EMC_CTT_TERM_CTRL */
1909                                 0x00000000 /* EMC_ZCAL_INTERVAL */
1910                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
1911                                 0x000c000c /* EMC_MRS_WAIT_CNT */
1912                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
1913                                 0x00000000 /* EMC_CTT */
1914                                 0x00000000 /* EMC_CTT_DURATION */
1915                                 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
1916                                 0xe8000000 /* EMC_FBIO_SPARE */
1917                                 0xff00ff00 /* EMC_CFG_RSV */
1918                         >;
1919                 };
1920                 timing-204000000 {
1921                         clock-frequency = <204000000>;
1922                         nvidia,emc-auto-cal-interval = <0x001fffff>;
1923                         nvidia,emc-mode-1 = <0x80100003>;
1924                         nvidia,emc-mode-2 = <0x80200008>;
1925                         nvidia,emc-mode-reset = <0x80001221>;
1926                         nvidia,emc-zcal-cnt-long = <0x00000040>;
1927                         nvidia,emc-cfg-periodic-qrst;
1928                         nvidia,emc-cfg-dyn-self-ref;
1929                         nvidia,emc-configuration = <
1930                                 0x00000009 /* EMC_RC */
1931                                 0x00000035 /* EMC_RFC */
1932                                 0x00000007 /* EMC_RAS */
1933                                 0x00000002 /* EMC_RP */
1934                                 0x00000002 /* EMC_R2W */
1935                                 0x0000000a /* EMC_W2R */
1936                                 0x00000005 /* EMC_R2P */
1937                                 0x0000000b /* EMC_W2P */
1938                                 0x00000002 /* EMC_RD_RCD */
1939                                 0x00000002 /* EMC_WR_RCD */
1940                                 0x00000003 /* EMC_RRD */
1941                                 0x00000001 /* EMC_REXT */
1942                                 0x00000000 /* EMC_WEXT */
1943                                 0x00000005 /* EMC_WDV */
1944                                 0x00000005 /* EMC_QUSE */
1945                                 0x00000004 /* EMC_QRST */
1946                                 0x0000000a /* EMC_QSAFE */
1947                                 0x0000000b /* EMC_RDV */
1948                                 0x00000607 /* EMC_REFRESH */
1949                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
1950                                 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
1951                                 0x00000002 /* EMC_PDEX2WR */
1952                                 0x00000002 /* EMC_PDEX2RD */
1953                                 0x00000001 /* EMC_PCHG2PDEN */
1954                                 0x00000000 /* EMC_ACT2PDEN */
1955                                 0x00000007 /* EMC_AR2PDEN */
1956                                 0x0000000f /* EMC_RW2PDEN */
1957                                 0x00000038 /* EMC_TXSR */
1958                                 0x00000038 /* EMC_TXSRDLL */
1959                                 0x00000004 /* EMC_TCKE */
1960                                 0x00000009 /* EMC_TFAW */
1961                                 0x00000000 /* EMC_TRPAB */
1962                                 0x00000004 /* EMC_TCLKSTABLE */
1963                                 0x00000005 /* EMC_TCLKSTOP */
1964                                 0x00000638 /* EMC_TREFBW */
1965                                 0x00000006 /* EMC_QUSE_EXTRA */
1966                                 0x00000006 /* EMC_FBIO_CFG6 */
1967                                 0x00000000 /* EMC_ODT_WRITE */
1968                                 0x00000000 /* EMC_ODT_READ */
1969                                 0x00004288 /* EMC_FBIO_CFG5 */
1970                                 0x004400a4 /* EMC_CFG_DIG_DLL */
1971                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
1972                                 0x00080000 /* EMC_DLL_XFORM_DQS0 */
1973                                 0x00080000 /* EMC_DLL_XFORM_DQS1 */
1974                                 0x00080000 /* EMC_DLL_XFORM_DQS2 */
1975                                 0x00080000 /* EMC_DLL_XFORM_DQS3 */
1976                                 0x00080000 /* EMC_DLL_XFORM_DQS4 */
1977                                 0x00080000 /* EMC_DLL_XFORM_DQS5 */
1978                                 0x00080000 /* EMC_DLL_XFORM_DQS6 */
1979                                 0x00080000 /* EMC_DLL_XFORM_DQS7 */
1980                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
1981                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
1982                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
1983                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
1984                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
1985                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
1986                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
1987                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
1988                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
1989                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
1990                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
1991                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
1992                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
1993                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
1994                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
1995                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
1996                                 0x00080000 /* EMC_DLL_XFORM_DQ0 */
1997                                 0x00080000 /* EMC_DLL_XFORM_DQ1 */
1998                                 0x00080000 /* EMC_DLL_XFORM_DQ2 */
1999                                 0x00080000 /* EMC_DLL_XFORM_DQ3 */
2000                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2001                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2002                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2003                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2004                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2005                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2006                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2007                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2008                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2009                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2010                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2011                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2012                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2013                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2014                                 0x00000000 /* EMC_CTT */
2015                                 0x00000000 /* EMC_CTT_DURATION */
2016                                 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
2017                                 0xe8000000 /* EMC_FBIO_SPARE */
2018                                 0xff00ff00 /* EMC_CFG_RSV */
2019                         >;
2020                 };
2021                 timing-400000000 {
2022                         clock-frequency = <400000000>;
2023                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2024                         nvidia,emc-mode-1 = <0x80100002>;
2025                         nvidia,emc-mode-2 = <0x80200000>;
2026                         nvidia,emc-mode-reset = <0x80000521>;
2027                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2028                         nvidia,emc-configuration = <
2029                                 0x00000012 /* EMC_RC */
2030                                 0x00000066 /* EMC_RFC */
2031                                 0x0000000c /* EMC_RAS */
2032                                 0x00000004 /* EMC_RP */
2033                                 0x00000003 /* EMC_R2W */
2034                                 0x00000008 /* EMC_W2R */
2035                                 0x00000002 /* EMC_R2P */
2036                                 0x0000000a /* EMC_W2P */
2037                                 0x00000004 /* EMC_RD_RCD */
2038                                 0x00000004 /* EMC_WR_RCD */
2039                                 0x00000002 /* EMC_RRD */
2040                                 0x00000001 /* EMC_REXT */
2041                                 0x00000000 /* EMC_WEXT */
2042                                 0x00000004 /* EMC_WDV */
2043                                 0x00000006 /* EMC_QUSE */
2044                                 0x00000004 /* EMC_QRST */
2045                                 0x0000000a /* EMC_QSAFE */
2046                                 0x0000000c /* EMC_RDV */
2047                                 0x00000bf0 /* EMC_REFRESH */
2048                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2049                                 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
2050                                 0x00000001 /* EMC_PDEX2WR */
2051                                 0x00000008 /* EMC_PDEX2RD */
2052                                 0x00000001 /* EMC_PCHG2PDEN */
2053                                 0x00000000 /* EMC_ACT2PDEN */
2054                                 0x00000008 /* EMC_AR2PDEN */
2055                                 0x0000000f /* EMC_RW2PDEN */
2056                                 0x0000006c /* EMC_TXSR */
2057                                 0x00000200 /* EMC_TXSRDLL */
2058                                 0x00000004 /* EMC_TCKE */
2059                                 0x00000010 /* EMC_TFAW */
2060                                 0x00000000 /* EMC_TRPAB */
2061                                 0x00000004 /* EMC_TCLKSTABLE */
2062                                 0x00000005 /* EMC_TCLKSTOP */
2063                                 0x00000c30 /* EMC_TREFBW */
2064                                 0x00000000 /* EMC_QUSE_EXTRA */
2065                                 0x00000004 /* EMC_FBIO_CFG6 */
2066                                 0x00000000 /* EMC_ODT_WRITE */
2067                                 0x00000000 /* EMC_ODT_READ */
2068                                 0x00007088 /* EMC_FBIO_CFG5 */
2069                                 0x001d0084 /* EMC_CFG_DIG_DLL */
2070                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2071                                 0x0003c000 /* EMC_DLL_XFORM_DQS0 */
2072                                 0x0003c000 /* EMC_DLL_XFORM_DQS1 */
2073                                 0x0003c000 /* EMC_DLL_XFORM_DQS2 */
2074                                 0x0003c000 /* EMC_DLL_XFORM_DQS3 */
2075                                 0x0003c000 /* EMC_DLL_XFORM_DQS4 */
2076                                 0x0003c000 /* EMC_DLL_XFORM_DQS5 */
2077                                 0x0003c000 /* EMC_DLL_XFORM_DQS6 */
2078                                 0x0003c000 /* EMC_DLL_XFORM_DQS7 */
2079                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2080                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2081                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2082                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2083                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2084                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2085                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2086                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2087                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2088                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2089                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2090                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2091                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2092                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2093                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2094                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2095                                 0x00048000 /* EMC_DLL_XFORM_DQ0 */
2096                                 0x00048000 /* EMC_DLL_XFORM_DQ1 */
2097                                 0x00048000 /* EMC_DLL_XFORM_DQ2 */
2098                                 0x00048000 /* EMC_DLL_XFORM_DQ3 */
2099                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2100                                 0x0800013d /* EMC_XM2DQSPADCTRL2 */
2101                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2102                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2103                                 0x01f1f508 /* EMC_XM2COMPPADCTRL */
2104                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2105                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2106                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2107                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
2108                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2109                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2110                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2111                                 0x0158000c /* EMC_MRS_WAIT_CNT */
2112                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2113                                 0x00000000 /* EMC_CTT */
2114                                 0x00000000 /* EMC_CTT_DURATION */
2115                                 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
2116                                 0xe8000000 /* EMC_FBIO_SPARE */
2117                                 0xff00ff89 /* EMC_CFG_RSV */
2118                         >;
2119                 };
2120                 timing-800000000 {
2121                         clock-frequency = <800000000>;
2122                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2123                         nvidia,emc-mode-1 = <0x80100002>;
2124                         nvidia,emc-mode-2 = <0x80200018>;
2125                         nvidia,emc-mode-reset = <0x80000d71>;
2126                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2127                         nvidia,emc-cfg-periodic-qrst;
2128                         nvidia,emc-configuration = <
2129                                 0x00000025 /* EMC_RC */
2130                                 0x000000ce /* EMC_RFC */
2131                                 0x0000001a /* EMC_RAS */
2132                                 0x00000009 /* EMC_RP */
2133                                 0x00000005 /* EMC_R2W */
2134                                 0x0000000d /* EMC_W2R */
2135                                 0x00000004 /* EMC_R2P */
2136                                 0x00000013 /* EMC_W2P */
2137                                 0x00000009 /* EMC_RD_RCD */
2138                                 0x00000009 /* EMC_WR_RCD */
2139                                 0x00000004 /* EMC_RRD */
2140                                 0x00000001 /* EMC_REXT */
2141                                 0x00000000 /* EMC_WEXT */
2142                                 0x00000007 /* EMC_WDV */
2143                                 0x0000000a /* EMC_QUSE */
2144                                 0x00000009 /* EMC_QRST */
2145                                 0x0000000b /* EMC_QSAFE */
2146                                 0x00000011 /* EMC_RDV */
2147                                 0x00001820 /* EMC_REFRESH */
2148                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2149                                 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
2150                                 0x00000003 /* EMC_PDEX2WR */
2151                                 0x00000012 /* EMC_PDEX2RD */
2152                                 0x00000001 /* EMC_PCHG2PDEN */
2153                                 0x00000000 /* EMC_ACT2PDEN */
2154                                 0x0000000f /* EMC_AR2PDEN */
2155                                 0x00000018 /* EMC_RW2PDEN */
2156                                 0x000000d8 /* EMC_TXSR */
2157                                 0x00000200 /* EMC_TXSRDLL */
2158                                 0x00000005 /* EMC_TCKE */
2159                                 0x00000020 /* EMC_TFAW */
2160                                 0x00000000 /* EMC_TRPAB */
2161                                 0x00000007 /* EMC_TCLKSTABLE */
2162                                 0x00000008 /* EMC_TCLKSTOP */
2163                                 0x00001860 /* EMC_TREFBW */
2164                                 0x0000000b /* EMC_QUSE_EXTRA */
2165                                 0x00000006 /* EMC_FBIO_CFG6 */
2166                                 0x00000000 /* EMC_ODT_WRITE */
2167                                 0x00000000 /* EMC_ODT_READ */
2168                                 0x00005088 /* EMC_FBIO_CFG5 */
2169                                 0xf0070191 /* EMC_CFG_DIG_DLL */
2170                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2171                                 0x0000800a /* EMC_DLL_XFORM_DQS0 */
2172                                 0x0000000a /* EMC_DLL_XFORM_DQS1 */
2173                                 0x0000000a /* EMC_DLL_XFORM_DQS2 */
2174                                 0x0000000a /* EMC_DLL_XFORM_DQS3 */
2175                                 0x0000000a /* EMC_DLL_XFORM_DQS4 */
2176                                 0x0000000a /* EMC_DLL_XFORM_DQS5 */
2177                                 0x0000000a /* EMC_DLL_XFORM_DQS6 */
2178                                 0x0000000a /* EMC_DLL_XFORM_DQS7 */
2179                                 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
2180                                 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
2181                                 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
2182                                 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
2183                                 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
2184                                 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
2185                                 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
2186                                 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
2187                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2188                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2189                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2190                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2191                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2192                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2193                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2194                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2195                                 0x0000000a /* EMC_DLL_XFORM_DQ0 */
2196                                 0x0000000a /* EMC_DLL_XFORM_DQ1 */
2197                                 0x0000000a /* EMC_DLL_XFORM_DQ2 */
2198                                 0x0000000a /* EMC_DLL_XFORM_DQ3 */
2199                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2200                                 0x0600013d /* EMC_XM2DQSPADCTRL2 */
2201                                 0x22220000 /* EMC_XM2DQPADCTRL2 */
2202                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2203                                 0x01f1f501 /* EMC_XM2COMPPADCTRL */
2204                                 0x07077404 /* EMC_XM2VTTGENPADCTRL */
2205                                 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
2206                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2207                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
2208                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2209                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2210                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2211                                 0x00f0000c /* EMC_MRS_WAIT_CNT */
2212                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2213                                 0x00000000 /* EMC_CTT */
2214                                 0x00000000 /* EMC_CTT_DURATION */
2215                                 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
2216                                 0xe8000000 /* EMC_FBIO_SPARE */
2217                                 0xff00ff49 /* EMC_CFG_RSV */
2218                         >;
2219                 };
2220         };
2221         emc-timings-2 {
2222                 nvidia,ram-code = <2>;  /* Hynix A RAM */
2223                 timing-25500000 {
2224                         clock-frequency = <25500000>;
2225                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2226                         nvidia,emc-mode-1 = <0x80100003>;
2227                         nvidia,emc-mode-2 = <0x80200008>;
2228                         nvidia,emc-mode-reset = <0x80001221>;
2229                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2230                         nvidia,emc-cfg-periodic-qrst;
2231                         nvidia,emc-cfg-dyn-self-ref;
2232                         nvidia,emc-configuration = <
2233                                 0x00000001 /* EMC_RC */
2234                                 0x00000007 /* EMC_RFC */
2235                                 0x00000000 /* EMC_RAS */
2236                                 0x00000000 /* EMC_RP */
2237                                 0x00000002 /* EMC_R2W */
2238                                 0x0000000a /* EMC_W2R */
2239                                 0x00000005 /* EMC_R2P */
2240                                 0x0000000b /* EMC_W2P */
2241                                 0x00000000 /* EMC_RD_RCD */
2242                                 0x00000000 /* EMC_WR_RCD */
2243                                 0x00000003 /* EMC_RRD */
2244                                 0x00000001 /* EMC_REXT */
2245                                 0x00000000 /* EMC_WEXT */
2246                                 0x00000005 /* EMC_WDV */
2247                                 0x00000005 /* EMC_QUSE */
2248                                 0x00000004 /* EMC_QRST */
2249                                 0x0000000a /* EMC_QSAFE */
2250                                 0x0000000b /* EMC_RDV */
2251                                 0x000000c0 /* EMC_REFRESH */
2252                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2253                                 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
2254                                 0x00000002 /* EMC_PDEX2WR */
2255                                 0x00000002 /* EMC_PDEX2RD */
2256                                 0x00000001 /* EMC_PCHG2PDEN */
2257                                 0x00000000 /* EMC_ACT2PDEN */
2258                                 0x00000007 /* EMC_AR2PDEN */
2259                                 0x0000000f /* EMC_RW2PDEN */
2260                                 0x00000008 /* EMC_TXSR */
2261                                 0x00000008 /* EMC_TXSRDLL */
2262                                 0x00000004 /* EMC_TCKE */
2263                                 0x00000002 /* EMC_TFAW */
2264                                 0x00000000 /* EMC_TRPAB */
2265                                 0x00000004 /* EMC_TCLKSTABLE */
2266                                 0x00000005 /* EMC_TCLKSTOP */
2267                                 0x000000c7 /* EMC_TREFBW */
2268                                 0x00000006 /* EMC_QUSE_EXTRA */
2269                                 0x00000004 /* EMC_FBIO_CFG6 */
2270                                 0x00000000 /* EMC_ODT_WRITE */
2271                                 0x00000000 /* EMC_ODT_READ */
2272                                 0x00004288 /* EMC_FBIO_CFG5 */
2273                                 0x007800a4 /* EMC_CFG_DIG_DLL */
2274                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2275                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2276                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2277                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2278                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2279                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2280                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2281                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2282                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2283                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2284                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2285                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2286                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2287                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2288                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2289                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2290                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2291                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2292                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2293                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2294                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2295                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2296                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2297                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2298                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2299                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2300                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2301                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2302                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2303                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2304                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2305                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2306                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2307                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2308                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2309                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2310                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2311                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2312                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2313                                 0x00000000 /* EMC_ZCAL_INTERVAL */
2314                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
2315                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2316                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2317                                 0x00000000 /* EMC_CTT */
2318                                 0x00000000 /* EMC_CTT_DURATION */
2319                                 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
2320                                 0xe8000000 /* EMC_FBIO_SPARE */
2321                                 0xff00ff00 /* EMC_CFG_RSV */
2322                         >;
2323                 };
2324                 timing-51000000 {
2325                         clock-frequency = <51000000>;
2326                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2327                         nvidia,emc-mode-1 = <0x80100003>;
2328                         nvidia,emc-mode-2 = <0x80200008>;
2329                         nvidia,emc-mode-reset = <0x80001221>;
2330                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2331                         nvidia,emc-cfg-periodic-qrst;
2332                         nvidia,emc-cfg-dyn-self-ref;
2333                         nvidia,emc-configuration = <
2334                                 0x00000002 /* EMC_RC */
2335                                 0x0000000f /* EMC_RFC */
2336                                 0x00000001 /* EMC_RAS */
2337                                 0x00000000 /* EMC_RP */
2338                                 0x00000002 /* EMC_R2W */
2339                                 0x0000000a /* EMC_W2R */
2340                                 0x00000005 /* EMC_R2P */
2341                                 0x0000000b /* EMC_W2P */
2342                                 0x00000000 /* EMC_RD_RCD */
2343                                 0x00000000 /* EMC_WR_RCD */
2344                                 0x00000003 /* EMC_RRD */
2345                                 0x00000001 /* EMC_REXT */
2346                                 0x00000000 /* EMC_WEXT */
2347                                 0x00000005 /* EMC_WDV */
2348                                 0x00000005 /* EMC_QUSE */
2349                                 0x00000004 /* EMC_QRST */
2350                                 0x0000000a /* EMC_QSAFE */
2351                                 0x0000000b /* EMC_RDV */
2352                                 0x00000181 /* EMC_REFRESH */
2353                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2354                                 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
2355                                 0x00000002 /* EMC_PDEX2WR */
2356                                 0x00000002 /* EMC_PDEX2RD */
2357                                 0x00000001 /* EMC_PCHG2PDEN */
2358                                 0x00000000 /* EMC_ACT2PDEN */
2359                                 0x00000007 /* EMC_AR2PDEN */
2360                                 0x0000000f /* EMC_RW2PDEN */
2361                                 0x00000010 /* EMC_TXSR */
2362                                 0x00000010 /* EMC_TXSRDLL */
2363                                 0x00000004 /* EMC_TCKE */
2364                                 0x00000003 /* EMC_TFAW */
2365                                 0x00000000 /* EMC_TRPAB */
2366                                 0x00000004 /* EMC_TCLKSTABLE */
2367                                 0x00000005 /* EMC_TCLKSTOP */
2368                                 0x0000018e /* EMC_TREFBW */
2369                                 0x00000006 /* EMC_QUSE_EXTRA */
2370                                 0x00000004 /* EMC_FBIO_CFG6 */
2371                                 0x00000000 /* EMC_ODT_WRITE */
2372                                 0x00000000 /* EMC_ODT_READ */
2373                                 0x00004288 /* EMC_FBIO_CFG5 */
2374                                 0x007800a4 /* EMC_CFG_DIG_DLL */
2375                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2376                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2377                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2378                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2379                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2380                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2381                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2382                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2383                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2384                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2385                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2386                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2387                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2388                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2389                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2390                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2391                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2392                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2393                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2394                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2395                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2396                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2397                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2398                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2399                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2400                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2401                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2402                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2403                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2404                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2405                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2406                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2407                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2408                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2409                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2410                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2411                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2412                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2413                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2414                                 0x00000000 /* EMC_ZCAL_INTERVAL */
2415                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
2416                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2417                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2418                                 0x00000000 /* EMC_CTT */
2419                                 0x00000000 /* EMC_CTT_DURATION */
2420                                 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
2421                                 0xe8000000 /* EMC_FBIO_SPARE */
2422                                 0xff00ff00 /* EMC_CFG_RSV */
2423                         >;
2424                 };
2425                 timing-102000000 {
2426                         clock-frequency = <102000000>;
2427                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2428                         nvidia,emc-mode-1 = <0x80100003>;
2429                         nvidia,emc-mode-2 = <0x80200008>;
2430                         nvidia,emc-mode-reset = <0x80001221>;
2431                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2432                         nvidia,emc-cfg-periodic-qrst;
2433                         nvidia,emc-cfg-dyn-self-ref;
2434                         nvidia,emc-configuration = <
2435                                 0x00000004 /* EMC_RC */
2436                                 0x0000001e /* EMC_RFC */
2437                                 0x00000003 /* EMC_RAS */
2438                                 0x00000001 /* EMC_RP */
2439                                 0x00000002 /* EMC_R2W */
2440                                 0x0000000a /* EMC_W2R */
2441                                 0x00000005 /* EMC_R2P */
2442                                 0x0000000b /* EMC_W2P */
2443                                 0x00000001 /* EMC_RD_RCD */
2444                                 0x00000001 /* EMC_WR_RCD */
2445                                 0x00000003 /* EMC_RRD */
2446                                 0x00000001 /* EMC_REXT */
2447                                 0x00000000 /* EMC_WEXT */
2448                                 0x00000005 /* EMC_WDV */
2449                                 0x00000005 /* EMC_QUSE */
2450                                 0x00000004 /* EMC_QRST */
2451                                 0x0000000a /* EMC_QSAFE */
2452                                 0x0000000b /* EMC_RDV */
2453                                 0x00000303 /* EMC_REFRESH */
2454                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2455                                 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
2456                                 0x00000002 /* EMC_PDEX2WR */
2457                                 0x00000002 /* EMC_PDEX2RD */
2458                                 0x00000001 /* EMC_PCHG2PDEN */
2459                                 0x00000000 /* EMC_ACT2PDEN */
2460                                 0x00000007 /* EMC_AR2PDEN */
2461                                 0x0000000f /* EMC_RW2PDEN */
2462                                 0x00000020 /* EMC_TXSR */
2463                                 0x00000020 /* EMC_TXSRDLL */
2464                                 0x00000004 /* EMC_TCKE */
2465                                 0x00000005 /* EMC_TFAW */
2466                                 0x00000000 /* EMC_TRPAB */
2467                                 0x00000004 /* EMC_TCLKSTABLE */
2468                                 0x00000005 /* EMC_TCLKSTOP */
2469                                 0x0000031c /* EMC_TREFBW */
2470                                 0x00000006 /* EMC_QUSE_EXTRA */
2471                                 0x00000004 /* EMC_FBIO_CFG6 */
2472                                 0x00000000 /* EMC_ODT_WRITE */
2473                                 0x00000000 /* EMC_ODT_READ */
2474                                 0x00004288 /* EMC_FBIO_CFG5 */
2475                                 0x007800a4 /* EMC_CFG_DIG_DLL */
2476                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2477                                 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2478                                 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2479                                 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2480                                 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2481                                 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2482                                 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2483                                 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2484                                 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2485                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2486                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2487                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2488                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2489                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2490                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2491                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2492                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2493                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2494                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2495                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2496                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2497                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2498                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2499                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2500                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2501                                 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2502                                 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2503                                 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2504                                 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2505                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2506                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2507                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2508                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2509                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2510                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2511                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2512                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2513                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2514                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2515                                 0x00000000 /* EMC_ZCAL_INTERVAL */
2516                                 0x00000040 /* EMC_ZCAL_WAIT_CNT */
2517                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2518                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2519                                 0x00000000 /* EMC_CTT */
2520                                 0x00000000 /* EMC_CTT_DURATION */
2521                                 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
2522                                 0xe8000000 /* EMC_FBIO_SPARE */
2523                                 0xff00ff00 /* EMC_CFG_RSV */
2524                         >;
2525                 };
2526                 timing-204000000 {
2527                         clock-frequency = <204000000>;
2528                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2529                         nvidia,emc-mode-1 = <0x80100003>;
2530                         nvidia,emc-mode-2 = <0x80200008>;
2531                         nvidia,emc-mode-reset = <0x80001221>;
2532                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2533                         nvidia,emc-cfg-periodic-qrst;
2534                         nvidia,emc-cfg-dyn-self-ref;
2535                         nvidia,emc-configuration = <
2536                                 0x00000009 /* EMC_RC */
2537                                 0x0000003d /* EMC_RFC */
2538                                 0x00000007 /* EMC_RAS */
2539                                 0x00000002 /* EMC_RP */
2540                                 0x00000002 /* EMC_R2W */
2541                                 0x0000000a /* EMC_W2R */
2542                                 0x00000005 /* EMC_R2P */
2543                                 0x0000000b /* EMC_W2P */
2544                                 0x00000002 /* EMC_RD_RCD */
2545                                 0x00000002 /* EMC_WR_RCD */
2546                                 0x00000003 /* EMC_RRD */
2547                                 0x00000001 /* EMC_REXT */
2548                                 0x00000000 /* EMC_WEXT */
2549                                 0x00000005 /* EMC_WDV */
2550                                 0x00000005 /* EMC_QUSE */
2551                                 0x00000004 /* EMC_QRST */
2552                                 0x0000000a /* EMC_QSAFE */
2553                                 0x0000000b /* EMC_RDV */
2554                                 0x00000607 /* EMC_REFRESH */
2555                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2556                                 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
2557                                 0x00000002 /* EMC_PDEX2WR */
2558                                 0x00000002 /* EMC_PDEX2RD */
2559                                 0x00000001 /* EMC_PCHG2PDEN */
2560                                 0x00000000 /* EMC_ACT2PDEN */
2561                                 0x00000007 /* EMC_AR2PDEN */
2562                                 0x0000000f /* EMC_RW2PDEN */
2563                                 0x00000040 /* EMC_TXSR */
2564                                 0x00000040 /* EMC_TXSRDLL */
2565                                 0x00000004 /* EMC_TCKE */
2566                                 0x00000009 /* EMC_TFAW */
2567                                 0x00000000 /* EMC_TRPAB */
2568                                 0x00000004 /* EMC_TCLKSTABLE */
2569                                 0x00000005 /* EMC_TCLKSTOP */
2570                                 0x00000638 /* EMC_TREFBW */
2571                                 0x00000006 /* EMC_QUSE_EXTRA */
2572                                 0x00000006 /* EMC_FBIO_CFG6 */
2573                                 0x00000000 /* EMC_ODT_WRITE */
2574                                 0x00000000 /* EMC_ODT_READ */
2575                                 0x00004288 /* EMC_FBIO_CFG5 */
2576                                 0x004400a4 /* EMC_CFG_DIG_DLL */
2577                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2578                                 0x00080000 /* EMC_DLL_XFORM_DQS0 */
2579                                 0x00080000 /* EMC_DLL_XFORM_DQS1 */
2580                                 0x00080000 /* EMC_DLL_XFORM_DQS2 */
2581                                 0x00080000 /* EMC_DLL_XFORM_DQS3 */
2582                                 0x00080000 /* EMC_DLL_XFORM_DQS4 */
2583                                 0x00080000 /* EMC_DLL_XFORM_DQS5 */
2584                                 0x00080000 /* EMC_DLL_XFORM_DQS6 */
2585                                 0x00080000 /* EMC_DLL_XFORM_DQS7 */
2586                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2587                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2588                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2589                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2590                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2591                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2592                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2593                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2594                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2595                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2596                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2597                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2598                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2599                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2600                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2601                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2602                                 0x00080000 /* EMC_DLL_XFORM_DQ0 */
2603                                 0x00080000 /* EMC_DLL_XFORM_DQ1 */
2604                                 0x00080000 /* EMC_DLL_XFORM_DQ2 */
2605                                 0x00080000 /* EMC_DLL_XFORM_DQ3 */
2606                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2607                                 0x0800211c /* EMC_XM2DQSPADCTRL2 */
2608                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2609                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2610                                 0x01f1f108 /* EMC_XM2COMPPADCTRL */
2611                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2612                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2613                                 0x08000168 /* EMC_XM2QUSEPADCTRL */
2614                                 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2615                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2616                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2617                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2618                                 0x000c000c /* EMC_MRS_WAIT_CNT */
2619                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2620                                 0x00000000 /* EMC_CTT */
2621                                 0x00000000 /* EMC_CTT_DURATION */
2622                                 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
2623                                 0xe8000000 /* EMC_FBIO_SPARE */
2624                                 0xff00ff00 /* EMC_CFG_RSV */
2625                         >;
2626                 };
2627                 timing-400000000 {
2628                         clock-frequency = <400000000>;
2629                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2630                         nvidia,emc-mode-1 = <0x80100002>;
2631                         nvidia,emc-mode-2 = <0x80200000>;
2632                         nvidia,emc-mode-reset = <0x80000521>;
2633                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2634                         nvidia,emc-configuration = <
2635                                 0x00000012 /* EMC_RC */
2636                                 0x00000076 /* EMC_RFC */
2637                                 0x0000000c /* EMC_RAS */
2638                                 0x00000004 /* EMC_RP */
2639                                 0x00000003 /* EMC_R2W */
2640                                 0x00000008 /* EMC_W2R */
2641                                 0x00000002 /* EMC_R2P */
2642                                 0x0000000a /* EMC_W2P */
2643                                 0x00000004 /* EMC_RD_RCD */
2644                                 0x00000004 /* EMC_WR_RCD */
2645                                 0x00000002 /* EMC_RRD */
2646                                 0x00000001 /* EMC_REXT */
2647                                 0x00000000 /* EMC_WEXT */
2648                                 0x00000004 /* EMC_WDV */
2649                                 0x00000006 /* EMC_QUSE */
2650                                 0x00000004 /* EMC_QRST */
2651                                 0x0000000a /* EMC_QSAFE */
2652                                 0x0000000c /* EMC_RDV */
2653                                 0x00000bf0 /* EMC_REFRESH */
2654                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2655                                 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
2656                                 0x00000001 /* EMC_PDEX2WR */
2657                                 0x00000008 /* EMC_PDEX2RD */
2658                                 0x00000001 /* EMC_PCHG2PDEN */
2659                                 0x00000000 /* EMC_ACT2PDEN */
2660                                 0x00000008 /* EMC_AR2PDEN */
2661                                 0x0000000f /* EMC_RW2PDEN */
2662                                 0x0000007c /* EMC_TXSR */
2663                                 0x00000200 /* EMC_TXSRDLL */
2664                                 0x00000004 /* EMC_TCKE */
2665                                 0x00000010 /* EMC_TFAW */
2666                                 0x00000000 /* EMC_TRPAB */
2667                                 0x00000004 /* EMC_TCLKSTABLE */
2668                                 0x00000005 /* EMC_TCLKSTOP */
2669                                 0x00000c30 /* EMC_TREFBW */
2670                                 0x00000000 /* EMC_QUSE_EXTRA */
2671                                 0x00000004 /* EMC_FBIO_CFG6 */
2672                                 0x00000000 /* EMC_ODT_WRITE */
2673                                 0x00000000 /* EMC_ODT_READ */
2674                                 0x00007088 /* EMC_FBIO_CFG5 */
2675                                 0x001d0084 /* EMC_CFG_DIG_DLL */
2676                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2677                                 0x00044000 /* EMC_DLL_XFORM_DQS0 */
2678                                 0x00044000 /* EMC_DLL_XFORM_DQS1 */
2679                                 0x00044000 /* EMC_DLL_XFORM_DQS2 */
2680                                 0x00044000 /* EMC_DLL_XFORM_DQS3 */
2681                                 0x00044000 /* EMC_DLL_XFORM_DQS4 */
2682                                 0x00044000 /* EMC_DLL_XFORM_DQS5 */
2683                                 0x00044000 /* EMC_DLL_XFORM_DQS6 */
2684                                 0x00044000 /* EMC_DLL_XFORM_DQS7 */
2685                                 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2686                                 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2687                                 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2688                                 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2689                                 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2690                                 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2691                                 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2692                                 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2693                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2694                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2695                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2696                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2697                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2698                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2699                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2700                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2701                                 0x00058000 /* EMC_DLL_XFORM_DQ0 */
2702                                 0x00058000 /* EMC_DLL_XFORM_DQ1 */
2703                                 0x00058000 /* EMC_DLL_XFORM_DQ2 */
2704                                 0x00058000 /* EMC_DLL_XFORM_DQ3 */
2705                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2706                                 0x0800013d /* EMC_XM2DQSPADCTRL2 */
2707                                 0x00000000 /* EMC_XM2DQPADCTRL2 */
2708                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2709                                 0x01f1f508 /* EMC_XM2COMPPADCTRL */
2710                                 0x05057404 /* EMC_XM2VTTGENPADCTRL */
2711                                 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2712                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2713                                 0x08000021 /* EMC_XM2DQSPADCTRL3 */
2714                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2715                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2716                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2717                                 0x0148000c /* EMC_MRS_WAIT_CNT */
2718                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2719                                 0x00000000 /* EMC_CTT */
2720                                 0x00000000 /* EMC_CTT_DURATION */
2721                                 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
2722                                 0xe8000000 /* EMC_FBIO_SPARE */
2723                                 0xff00ff89 /* EMC_CFG_RSV */
2724                         >;
2725                 };
2726                 timing-800000000 {
2727                         clock-frequency = <800000000>;
2728                         nvidia,emc-auto-cal-interval = <0x001fffff>;
2729                         nvidia,emc-mode-1 = <0x80100002>;
2730                         nvidia,emc-mode-2 = <0x80200018>;
2731                         nvidia,emc-mode-reset = <0x80000d71>;
2732                         nvidia,emc-zcal-cnt-long = <0x00000040>;
2733                         nvidia,emc-cfg-periodic-qrst;
2734                         nvidia,emc-configuration = <
2735                                 0x00000025 /* EMC_RC */
2736                                 0x000000ee /* EMC_RFC */
2737                                 0x0000001a /* EMC_RAS */
2738                                 0x00000009 /* EMC_RP */
2739                                 0x00000005 /* EMC_R2W */
2740                                 0x0000000d /* EMC_W2R */
2741                                 0x00000004 /* EMC_R2P */
2742                                 0x00000013 /* EMC_W2P */
2743                                 0x00000009 /* EMC_RD_RCD */
2744                                 0x00000009 /* EMC_WR_RCD */
2745                                 0x00000003 /* EMC_RRD */
2746                                 0x00000001 /* EMC_REXT */
2747                                 0x00000000 /* EMC_WEXT */
2748                                 0x00000007 /* EMC_WDV */
2749                                 0x0000000a /* EMC_QUSE */
2750                                 0x00000009 /* EMC_QRST */
2751                                 0x0000000b /* EMC_QSAFE */
2752                                 0x00000011 /* EMC_RDV */
2753                                 0x00001820 /* EMC_REFRESH */
2754                                 0x00000000 /* EMC_BURST_REFRESH_NUM */
2755                                 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
2756                                 0x00000003 /* EMC_PDEX2WR */
2757                                 0x00000012 /* EMC_PDEX2RD */
2758                                 0x00000001 /* EMC_PCHG2PDEN */
2759                                 0x00000000 /* EMC_ACT2PDEN */
2760                                 0x0000000f /* EMC_AR2PDEN */
2761                                 0x00000018 /* EMC_RW2PDEN */
2762                                 0x000000f8 /* EMC_TXSR */
2763                                 0x00000200 /* EMC_TXSRDLL */
2764                                 0x00000005 /* EMC_TCKE */
2765                                 0x00000020 /* EMC_TFAW */
2766                                 0x00000000 /* EMC_TRPAB */
2767                                 0x00000007 /* EMC_TCLKSTABLE */
2768                                 0x00000008 /* EMC_TCLKSTOP */
2769                                 0x00001860 /* EMC_TREFBW */
2770                                 0x0000000b /* EMC_QUSE_EXTRA */
2771                                 0x00000006 /* EMC_FBIO_CFG6 */
2772                                 0x00000000 /* EMC_ODT_WRITE */
2773                                 0x00000000 /* EMC_ODT_READ */
2774                                 0x00005088 /* EMC_FBIO_CFG5 */
2775                                 0xf0070191 /* EMC_CFG_DIG_DLL */
2776                                 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2777                                 0x0000000c /* EMC_DLL_XFORM_DQS0 */
2778                                 0x007fc00a /* EMC_DLL_XFORM_DQS1 */
2779                                 0x00000008 /* EMC_DLL_XFORM_DQS2 */
2780                                 0x0000000a /* EMC_DLL_XFORM_DQS3 */
2781                                 0x0000000a /* EMC_DLL_XFORM_DQS4 */
2782                                 0x0000000a /* EMC_DLL_XFORM_DQS5 */
2783                                 0x0000000a /* EMC_DLL_XFORM_DQS6 */
2784                                 0x0000000a /* EMC_DLL_XFORM_DQS7 */
2785                                 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
2786                                 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
2787                                 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
2788                                 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
2789                                 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
2790                                 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
2791                                 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
2792                                 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
2793                                 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2794                                 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2795                                 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2796                                 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2797                                 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2798                                 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2799                                 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2800                                 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2801                                 0x0000000a /* EMC_DLL_XFORM_DQ0 */
2802                                 0x0000000c /* EMC_DLL_XFORM_DQ1 */
2803                                 0x0000000a /* EMC_DLL_XFORM_DQ2 */
2804                                 0x0000000a /* EMC_DLL_XFORM_DQ3 */
2805                                 0x000002a0 /* EMC_XM2CMDPADCTRL */
2806                                 0x0600013d /* EMC_XM2DQSPADCTRL2 */
2807                                 0x22220000 /* EMC_XM2DQPADCTRL2 */
2808                                 0x77fff884 /* EMC_XM2CLKPADCTRL */
2809                                 0x01f1f501 /* EMC_XM2COMPPADCTRL */
2810                                 0x07077404 /* EMC_XM2VTTGENPADCTRL */
2811                                 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
2812                                 0x080001e8 /* EMC_XM2QUSEPADCTRL */
2813                                 0x0a000021 /* EMC_XM2DQSPADCTRL3 */
2814                                 0x00000802 /* EMC_CTT_TERM_CTRL */
2815                                 0x00020000 /* EMC_ZCAL_INTERVAL */
2816                                 0x00000100 /* EMC_ZCAL_WAIT_CNT */
2817                                 0x00d0000c /* EMC_MRS_WAIT_CNT */
2818                                 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2819                                 0x00000000 /* EMC_CTT */
2820                                 0x00000000 /* EMC_CTT_DURATION */
2821                                 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
2822                                 0xe8000000 /* EMC_FBIO_SPARE */
2823                                 0xff00ff49 /* EMC_CFG_RSV */
2824                         >;
2825                 };
2826         };
2827 };
2828 &state_default {
2829         clk_32k_out_pa0 {
2830                 nvidia,pins = "clk_32k_out_pa0";
2831                 nvidia,function = "blink";
2832                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2833                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2834                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2835         };
2836         uart3_cts_n_pa1 {
2837                 nvidia,pins = "uart3_cts_n_pa1";
2838                 nvidia,function = "uartc";
2839                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2840                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2841                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2842         };
2843         dap2_fs_pa2 {
2844                 nvidia,pins = "dap2_fs_pa2";
2845                 nvidia,function = "i2s1";
2846                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2847                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2848                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2849         };
2850         dap2_sclk_pa3 {
2851                 nvidia,pins = "dap2_sclk_pa3";
2852                 nvidia,function = "i2s1";
2853                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2854                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2855                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2856         };
2857         dap2_din_pa4 {
2858                 nvidia,pins = "dap2_din_pa4";
2859                 nvidia,function = "i2s1";
2860                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2861                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2862                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2863         };
2864         dap2_dout_pa5 {
2865                 nvidia,pins = "dap2_dout_pa5";
2866                 nvidia,function = "i2s1";
2867                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2868                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2869                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2870         };
2871         sdmmc3_clk_pa6 {
2872                 nvidia,pins = "sdmmc3_clk_pa6";
2873                 nvidia,function = "sdmmc3";
2874                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2875                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2876                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2877         };
2878         sdmmc3_cmd_pa7 {
2879                 nvidia,pins = "sdmmc3_cmd_pa7";
2880                 nvidia,function = "sdmmc3";
2881                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2882                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2883                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2884         };
2885         gmi_a17_pb0 {
2886                 nvidia,pins = "gmi_a17_pb0";
2887                 nvidia,function = "spi4";
2888                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2889                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2890                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2891         };
2892         gmi_a18_pb1 {
2893                 nvidia,pins = "gmi_a18_pb1";
2894                 nvidia,function = "spi4";
2895                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2896                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2897                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2898         };
2899         lcd_pwr0_pb2 {
2900                 nvidia,pins = "lcd_pwr0_pb2";
2901                 nvidia,function = "displaya";
2902                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2903                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2904                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2905         };
2906         lcd_pclk_pb3 {
2907                 nvidia,pins = "lcd_pclk_pb3";
2908                 nvidia,function = "displaya";
2909                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2910                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2911                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2912         };
2913         sdmmc3_dat3_pb4 {
2914                 nvidia,pins = "sdmmc3_dat3_pb4";
2915                 nvidia,function = "sdmmc3";
2916                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2917                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2918                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2919         };
2920         sdmmc3_dat2_pb5 {
2921                 nvidia,pins = "sdmmc3_dat2_pb5";
2922                 nvidia,function = "sdmmc3";
2923                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2924                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2925                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2926         };
2927         sdmmc3_dat1_pb6 {
2928                 nvidia,pins = "sdmmc3_dat1_pb6";
2929                 nvidia,function = "sdmmc3";
2930                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2931                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2932                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2933         };
2934         sdmmc3_dat0_pb7 {
2935                 nvidia,pins = "sdmmc3_dat0_pb7";
2936                 nvidia,function = "sdmmc3";
2937                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
2938                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2939                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2940         };
2941         uart3_rts_n_pc0 {
2942                 nvidia,pins = "uart3_rts_n_pc0";
2943                 nvidia,function = "uartc";
2944                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2945                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2946                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2947         };
2948         lcd_pwr1_pc1 {
2949                 nvidia,pins = "lcd_pwr1_pc1";
2950                 nvidia,function = "displaya";
2951                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2952                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2953                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2954         };
2955         uart2_txd_pc2 {
2956                 nvidia,pins = "uart2_txd_pc2";
2957                 nvidia,function = "uartb";
2958                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2959                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2960                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2961         };
2962         uart2_rxd_pc3 {
2963                 nvidia,pins = "uart2_rxd_pc3";
2964                 nvidia,function = "uartb";
2965                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2966                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2967                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2968         };
2969         gen1_i2c_scl_pc4 {
2970                 nvidia,pins = "gen1_i2c_scl_pc4";
2971                 nvidia,function = "i2c1";
2972                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2973                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2974                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2975                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2976         };
2977         gen1_i2c_sda_pc5 {
2978                 nvidia,pins = "gen1_i2c_sda_pc5";
2979                 nvidia,function = "i2c1";
2980                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2981                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2982                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2983                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
2984         };
2985         lcd_pwr2_pc6 {
2986                 nvidia,pins = "lcd_pwr2_pc6";
2987                 nvidia,function = "displaya";
2988                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2989                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
2990                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
2991         };
2992         gmi_wp_n_pc7 {
2993                 nvidia,pins = "gmi_wp_n_pc7";
2994                 nvidia,function = "gmi";
2995                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
2996                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
2997                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
2998         };
2999         sdmmc3_dat5_pd0 {
3000                 nvidia,pins = "sdmmc3_dat5_pd0";
3001                 nvidia,function = "sdmmc3";
3002                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3003                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3004                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3005         };
3006         sdmmc3_dat4_pd1 {
3007                 nvidia,pins = "sdmmc3_dat4_pd1";
3008                 nvidia,function = "sdmmc3";
3009                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3010                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3011                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3012         };
3013         lcd_dc1_pd2 {
3014                 nvidia,pins = "lcd_dc1_pd2";
3015                 nvidia,function = "displaya";
3016                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3017                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3018                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3019         };
3020         sdmmc3_dat6_pd3 {
3021                 nvidia,pins = "sdmmc3_dat6_pd3";
3022                 nvidia,function = "spi4";
3023                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3024                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3025                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3026         };
3027         sdmmc3_dat7_pd4 {
3028                 nvidia,pins = "sdmmc3_dat7_pd4";
3029                 nvidia,function = "spi4";
3030                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3031                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3032                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3033         };
3034         vi_d1_pd5 {
3035                 nvidia,pins = "vi_d1_pd5";
3036                 nvidia,function = "sdmmc2";
3037                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3038                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3039                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3040         };
3041         vi_vsync_pd6 {
3042                 nvidia,pins = "vi_vsync_pd6";
3043                 nvidia,function = "ddr";
3044                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3045                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3046                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3047         };
3048         vi_hsync_pd7 {
3049                 nvidia,pins = "vi_hsync_pd7";
3050                 nvidia,function = "ddr";
3051                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3052                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3053                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3054         };
3055         lcd_d0_pe0 {
3056                 nvidia,pins = "lcd_d0_pe0";
3057                 nvidia,function = "displaya";
3058                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3059                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3060                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3061         };
3062         lcd_d1_pe1 {
3063                 nvidia,pins = "lcd_d1_pe1";
3064                 nvidia,function = "displaya";
3065                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3066                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3067                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3068         };
3069         lcd_d2_pe2 {
3070                 nvidia,pins = "lcd_d2_pe2";
3071                 nvidia,function = "displaya";
3072                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3073                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3074                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3075         };
3076         lcd_d3_pe3 {
3077                 nvidia,pins = "lcd_d3_pe3";
3078                 nvidia,function = "displaya";
3079                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3080                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3081                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3082         };
3083         lcd_d4_pe4 {
3084                 nvidia,pins = "lcd_d4_pe4";
3085                 nvidia,function = "displaya";
3086                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3087                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3088                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3089         };
3090         lcd_d5_pe5 {
3091                 nvidia,pins = "lcd_d5_pe5";
3092                 nvidia,function = "displaya";
3093                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3094                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3095                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3096         };
3097         lcd_d6_pe6 {
3098                 nvidia,pins = "lcd_d6_pe6";
3099                 nvidia,function = "displaya";
3100                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3101                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3102                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3103         };
3104         lcd_d7_pe7 {
3105                 nvidia,pins = "lcd_d7_pe7";
3106                 nvidia,function = "displaya";
3107                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3108                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3109                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3110         };
3111         lcd_d8_pf0 {
3112                 nvidia,pins = "lcd_d8_pf0";
3113                 nvidia,function = "displaya";
3114                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3115                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3116                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3117         };
3118         lcd_d9_pf1 {
3119                 nvidia,pins = "lcd_d9_pf1";
3120                 nvidia,function = "displaya";
3121                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3122                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3123                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3124         };
3125         lcd_d10_pf2 {
3126                 nvidia,pins = "lcd_d10_pf2";
3127                 nvidia,function = "displaya";
3128                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3129                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3130                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3131         };
3132         lcd_d11_pf3 {
3133                 nvidia,pins = "lcd_d11_pf3";
3134                 nvidia,function = "displaya";
3135                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3136                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3137                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3138         };
3139         lcd_d12_pf4 {
3140                 nvidia,pins = "lcd_d12_pf4";
3141                 nvidia,function = "displaya";
3142                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3143                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3144                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3145         };
3146         lcd_d13_pf5 {
3147                 nvidia,pins = "lcd_d13_pf5";
3148                 nvidia,function = "displaya";
3149                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3150                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3151                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3152         };
3153         lcd_d14_pf6 {
3154                 nvidia,pins = "lcd_d14_pf6";
3155                 nvidia,function = "displaya";
3156                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3157                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3158                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3159         };
3160         lcd_d15_pf7 {
3161                 nvidia,pins = "lcd_d15_pf7";
3162                 nvidia,function = "displaya";
3163                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3164                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3165                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3166         };
3167         gmi_ad0_pg0 {
3168                 nvidia,pins = "gmi_ad0_pg0";
3169                 nvidia,function = "nand";
3170                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3171                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3172                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3173         };
3174         gmi_ad1_pg1 {
3175                 nvidia,pins = "gmi_ad1_pg1";
3176                 nvidia,function = "nand";
3177                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3178                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3179                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3180         };
3181         gmi_ad2_pg2 {
3182                 nvidia,pins = "gmi_ad2_pg2";
3183                 nvidia,function = "nand";
3184                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3185                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3186                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3187         };
3188         gmi_ad3_pg3 {
3189                 nvidia,pins = "gmi_ad3_pg3";
3190                 nvidia,function = "nand";
3191                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3192                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3193                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3194         };
3195         gmi_ad4_pg4 {
3196                 nvidia,pins = "gmi_ad4_pg4";
3197                 nvidia,function = "nand";
3198                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3199                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3200                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3201         };
3202         gmi_ad5_pg5 {
3203                 nvidia,pins = "gmi_ad5_pg5";
3204                 nvidia,function = "nand";
3205                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3206                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3207                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3208         };
3209         gmi_ad6_pg6 {
3210                 nvidia,pins = "gmi_ad6_pg6";
3211                 nvidia,function = "nand";
3212                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3213                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3214                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3215         };
3216         gmi_ad7_pg7 {
3217                 nvidia,pins = "gmi_ad7_pg7";
3218                 nvidia,function = "nand";
3219                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3220                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3221                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3222         };
3223         gmi_ad8_ph0 {
3224                 nvidia,pins = "gmi_ad8_ph0";
3225                 nvidia,function = "pwm0";
3226                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3227                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3228                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3229         };
3230         gmi_ad9_ph1 {
3231                 nvidia,pins = "gmi_ad9_ph1";
3232                 nvidia,function = "pwm1";
3233                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3234                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3235                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3236         };
3237         gmi_ad10_ph2 {
3238                 nvidia,pins = "gmi_ad10_ph2";
3239                 nvidia,function = "pwm2";
3240                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3241                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3242                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3243         };
3244         gmi_ad11_ph3 {
3245                 nvidia,pins = "gmi_ad11_ph3";
3246                 nvidia,function = "nand";
3247                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3248                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3249                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3250         };
3251         gmi_ad12_ph4 {
3252                 nvidia,pins = "gmi_ad12_ph4";
3253                 nvidia,function = "nand";
3254                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3255                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3256                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3257         };
3258         gmi_ad13_ph5 {
3259                 nvidia,pins = "gmi_ad13_ph5";
3260                 nvidia,function = "nand";
3261                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3262                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3263                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3264         };
3265         gmi_ad14_ph6 {
3266                 nvidia,pins = "gmi_ad14_ph6";
3267                 nvidia,function = "nand";
3268                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3269                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3270                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3271         };
3272         gmi_wr_n_pi0 {
3273                 nvidia,pins = "gmi_wr_n_pi0";
3274                 nvidia,function = "nand";
3275                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3276                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3277                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3278         };
3279         gmi_oe_n_pi1 {
3280                 nvidia,pins = "gmi_oe_n_pi1";
3281                 nvidia,function = "nand";
3282                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3283                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3284                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3285         };
3286         gmi_dqs_pi2 {
3287                 nvidia,pins = "gmi_dqs_pi2";
3288                 nvidia,function = "nand";
3289                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3290                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3291                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3292         };
3293         gmi_iordy_pi5 {
3294                 nvidia,pins = "gmi_iordy_pi5";
3295                 nvidia,function = "rsvd1";
3296                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3297                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3298                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3299         };
3300         gmi_cs7_n_pi6 {
3301                 nvidia,pins = "gmi_cs7_n_pi6";
3302                 nvidia,function = "nand";
3303                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3304                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3305                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3306         };
3307         gmi_wait_pi7 {
3308                 nvidia,pins = "gmi_wait_pi7";
3309                 nvidia,function = "nand";
3310                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3311                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3312                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3313         };
3314         lcd_de_pj1 {
3315                 nvidia,pins = "lcd_de_pj1";
3316                 nvidia,function = "displaya";
3317                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3318                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3319                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3320         };
3321         gmi_cs1_n_pj2 {
3322                 nvidia,pins = "gmi_cs1_n_pj2";
3323                 nvidia,function = "rsvd1";
3324                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3325                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3326                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3327         };
3328         lcd_hsync_pj3 {
3329                 nvidia,pins = "lcd_hsync_pj3";
3330                 nvidia,function = "displaya";
3331                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3332                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3333                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3334         };
3335         lcd_vsync_pj4 {
3336                 nvidia,pins = "lcd_vsync_pj4";
3337                 nvidia,function = "displaya";
3338                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3339                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3340                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3341         };
3342         uart2_cts_n_pj5 {
3343                 nvidia,pins = "uart2_cts_n_pj5";
3344                 nvidia,function = "uartb";
3345                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
3346                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3347                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3348         };
3349         uart2_rts_n_pj6 {
3350                 nvidia,pins = "uart2_rts_n_pj6";
3351                 nvidia,function = "uartb";
3352                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3353                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3354                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3355         };
3356         gmi_a16_pj7 {
3357                 nvidia,pins = "gmi_a16_pj7";
3358                 nvidia,function = "spi4";
3359                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3360                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3361                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3362         };
3363         gmi_adv_n_pk0 {
3364                 nvidia,pins = "gmi_adv_n_pk0";
3365                 nvidia,function = "nand";
3366                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3367                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3368                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3369         };
3370         gmi_clk_pk1 {
3371                 nvidia,pins = "gmi_clk_pk1";
3372                 nvidia,function = "nand";
3373                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3374                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3375                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3376         };
3377         gmi_cs2_n_pk3 {
3378                 nvidia,pins = "gmi_cs2_n_pk3";
3379                 nvidia,function = "rsvd1";
3380                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3381                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3382                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3383         };
3384         gmi_cs3_n_pk4 {
3385                 nvidia,pins = "gmi_cs3_n_pk4";
3386                 nvidia,function = "nand";
3387                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3388                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3389                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3390         };
3391         spdif_out_pk5 {
3392                 nvidia,pins = "spdif_out_pk5";
3393                 nvidia,function = "spdif";
3394                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3395                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3396                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3397         };
3398         spdif_in_pk6 {
3399                 nvidia,pins = "spdif_in_pk6";
3400                 nvidia,function = "spdif";
3401                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3402                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3403                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3404         };
3405         gmi_a19_pk7 {
3406                 nvidia,pins = "gmi_a19_pk7";
3407                 nvidia,function = "spi4";
3408                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3409                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3410                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3411         };
3412         vi_d2_pl0 {
3413                 nvidia,pins = "vi_d2_pl0";
3414                 nvidia,function = "sdmmc2";
3415                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3416                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3417                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3418         };
3419         vi_d3_pl1 {
3420                 nvidia,pins = "vi_d3_pl1";
3421                 nvidia,function = "sdmmc2";
3422                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3423                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3424                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3425         };
3426         vi_d4_pl2 {
3427                 nvidia,pins = "vi_d4_pl2";
3428                 nvidia,function = "vi";
3429                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3430                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3431                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3432         };
3433         vi_d5_pl3 {
3434                 nvidia,pins = "vi_d5_pl3";
3435                 nvidia,function = "sdmmc2";
3436                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3437                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3438                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3439         };
3440         vi_d6_pl4 {
3441                 nvidia,pins = "vi_d6_pl4";
3442                 nvidia,function = "vi";
3443                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3444                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3445                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3446         };
3447         vi_d7_pl5 {
3448                 nvidia,pins = "vi_d7_pl5";
3449                 nvidia,function = "sdmmc2";
3450                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3451                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3452                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3453         };
3454         vi_d8_pl6 {
3455                 nvidia,pins = "vi_d8_pl6";
3456                 nvidia,function = "sdmmc2";
3457                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3458                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3459                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3460         };
3461         vi_d9_pl7 {
3462                 nvidia,pins = "vi_d9_pl7";
3463                 nvidia,function = "sdmmc2";
3464                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3465                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3466                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3467         };
3468         lcd_d16_pm0 {
3469                 nvidia,pins = "lcd_d16_pm0";
3470                 nvidia,function = "displaya";
3471                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3472                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3473                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3474         };
3475         lcd_d17_pm1 {
3476                 nvidia,pins = "lcd_d17_pm1";
3477                 nvidia,function = "displaya";
3478                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3479                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3480                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3481         };
3482         lcd_d18_pm2 {
3483                 nvidia,pins = "lcd_d18_pm2";
3484                 nvidia,function = "displaya";
3485                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3486                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3487                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3488         };
3489         lcd_d19_pm3 {
3490                 nvidia,pins = "lcd_d19_pm3";
3491                 nvidia,function = "displaya";
3492                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3493                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3494                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3495         };
3496         lcd_d20_pm4 {
3497                 nvidia,pins = "lcd_d20_pm4";
3498                 nvidia,function = "displaya";
3499                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3500                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3501                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3502         };
3503         lcd_d21_pm5 {
3504                 nvidia,pins = "lcd_d21_pm5";
3505                 nvidia,function = "displaya";
3506                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3507                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3508                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3509         };
3510         lcd_d22_pm6 {
3511                 nvidia,pins = "lcd_d22_pm6";
3512                 nvidia,function = "displaya";
3513                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3514                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3515                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3516         };
3517         lcd_d23_pm7 {
3518                 nvidia,pins = "lcd_d23_pm7";
3519                 nvidia,function = "displaya";
3520                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3521                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3522                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3523         };
3524         dap1_fs_pn0 {
3525                 nvidia,pins = "dap1_fs_pn0";
3526                 nvidia,function = "i2s0";
3527                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3528                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3529                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3530         };
3531         dap1_din_pn1 {
3532                 nvidia,pins = "dap1_din_pn1";
3533                 nvidia,function = "i2s0";
3534                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3535                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3536                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3537         };
3538         dap1_dout_pn2 {
3539                 nvidia,pins = "dap1_dout_pn2";
3540                 nvidia,function = "i2s0";
3541                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3542                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3543                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3544         };
3545         dap1_sclk_pn3 {
3546                 nvidia,pins = "dap1_sclk_pn3";
3547                 nvidia,function = "i2s0";
3548                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3549                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3550                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3551         };
3552         lcd_cs0_n_pn4 {
3553                 nvidia,pins = "lcd_cs0_n_pn4";
3554                 nvidia,function = "displaya";
3555                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3556                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3557                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3558         };
3559         lcd_sdout_pn5 {
3560                 nvidia,pins = "lcd_sdout_pn5";
3561                 nvidia,function = "displaya";
3562                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3563                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3564                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3565         };
3566         lcd_dc0_pn6 {
3567                 nvidia,pins = "lcd_dc0_pn6";
3568                 nvidia,function = "displaya";
3569                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3570                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3571                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3572         };
3573         hdmi_int_pn7 {
3574                 nvidia,pins = "hdmi_int_pn7";
3575                 nvidia,function = "hdmi";
3576                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3577                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3578                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3579         };
3580         ulpi_data7_po0 {
3581                 nvidia,pins = "ulpi_data7_po0";
3582                 nvidia,function = "uarta";
3583                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
3584                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3585                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3586         };
3587         ulpi_data0_po1 {
3588                 nvidia,pins = "ulpi_data0_po1";
3589                 nvidia,function = "uarta";
3590                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3591                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3592                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3593         };
3594         ulpi_data1_po2 {
3595                 nvidia,pins = "ulpi_data1_po2";
3596                 nvidia,function = "uarta";
3597                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3598                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3599                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3600         };
3601         ulpi_data2_po3 {
3602                 nvidia,pins = "ulpi_data2_po3";
3603                 nvidia,function = "uarta";
3604                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3605                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3606                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3607         };
3608         ulpi_data3_po4 {
3609                 nvidia,pins = "ulpi_data3_po4";
3610                 nvidia,function = "uarta";
3611                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3612                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3613                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3614         };
3615         ulpi_data4_po5 {
3616                 nvidia,pins = "ulpi_data4_po5";
3617                 nvidia,function = "uarta";
3618                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3619                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3620                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3621         };
3622         ulpi_data5_po6 {
3623                 nvidia,pins = "ulpi_data5_po6";
3624                 nvidia,function = "uarta";
3625                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3626                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3627                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3628         };
3629         ulpi_data6_po7 {
3630                 nvidia,pins = "ulpi_data6_po7";
3631                 nvidia,function = "uarta";
3632                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3633                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3634                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3635         };
3636         dap3_fs_pp0 {
3637                 nvidia,pins = "dap3_fs_pp0";
3638                 nvidia,function = "i2s2";
3639                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3640                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3641                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3642         };
3643         dap3_din_pp1 {
3644                 nvidia,pins = "dap3_din_pp1";
3645                 nvidia,function = "i2s2";
3646                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3647                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3648                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3649         };
3650         dap3_dout_pp2 {
3651                 nvidia,pins = "dap3_dout_pp2";
3652                 nvidia,function = "i2s2";
3653                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3654                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3655                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3656         };
3657         dap3_sclk_pp3 {
3658                 nvidia,pins = "dap3_sclk_pp3";
3659                 nvidia,function = "i2s2";
3660                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3661                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3662                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3663         };
3664         dap4_fs_pp4 {
3665                 nvidia,pins = "dap4_fs_pp4";
3666                 nvidia,function = "i2s3";
3667                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3668                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3669                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3670         };
3671         dap4_din_pp5 {
3672                 nvidia,pins = "dap4_din_pp5";
3673                 nvidia,function = "i2s3";
3674                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3675                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3676                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3677         };
3678         dap4_dout_pp6 {
3679                 nvidia,pins = "dap4_dout_pp6";
3680                 nvidia,function = "i2s3";
3681                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3682                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3683                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3684         };
3685         dap4_sclk_pp7 {
3686                 nvidia,pins = "dap4_sclk_pp7";
3687                 nvidia,function = "i2s3";
3688                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3689                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3690                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3691         };
3692         kb_col0_pq0 {
3693                 nvidia,pins = "kb_col0_pq0";
3694                 nvidia,function = "kbc";
3695                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3696                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3697                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3698         };
3699         kb_col1_pq1 {
3700                 nvidia,pins = "kb_col1_pq1";
3701                 nvidia,function = "kbc";
3702                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3703                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3704                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3705         };
3706         kb_col2_pq2 {
3707                 nvidia,pins = "kb_col2_pq2";
3708                 nvidia,function = "kbc";
3709                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3710                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3711                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3712         };
3713         kb_col3_pq3 {
3714                 nvidia,pins = "kb_col3_pq3";
3715                 nvidia,function = "kbc";
3716                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3717                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3718                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3719         };
3720         kb_col4_pq4 {
3721                 nvidia,pins = "kb_col4_pq4";
3722                 nvidia,function = "kbc";
3723                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3724                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3725                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3726         };
3727         kb_col5_pq5 {
3728                 nvidia,pins = "kb_col5_pq5";
3729                 nvidia,function = "kbc";
3730                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3731                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3732                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3733         };
3734         kb_col6_pq6 {
3735                 nvidia,pins = "kb_col6_pq6";
3736                 nvidia,function = "kbc";
3737                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3738                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3739                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3740         };
3741         kb_col7_pq7 {
3742                 nvidia,pins = "kb_col7_pq7";
3743                 nvidia,function = "kbc";
3744                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3745                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3746                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3747         };
3748         kb_row0_pr0 {
3749                 nvidia,pins = "kb_row0_pr0";
3750                 nvidia,function = "kbc";
3751                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3752                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3753                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3754         };
3755         kb_row1_pr1 {
3756                 nvidia,pins = "kb_row1_pr1";
3757                 nvidia,function = "kbc";
3758                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3759                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3760                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3761         };
3762         kb_row2_pr2 {
3763                 nvidia,pins = "kb_row2_pr2";
3764                 nvidia,function = "kbc";
3765                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3766                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3767                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3768         };
3769         kb_row3_pr3 {
3770                 nvidia,pins = "kb_row3_pr3";
3771                 nvidia,function = "kbc";
3772                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3773                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3774                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3775         };
3776         kb_row4_pr4 {
3777                 nvidia,pins = "kb_row4_pr4";
3778                 nvidia,function = "kbc";
3779                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3780                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3781                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3782         };
3783         kb_row5_pr5 {
3784                 nvidia,pins = "kb_row5_pr5";
3785                 nvidia,function = "kbc";
3786                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3787                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3788                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3789         };
3790         kb_row6_pr6 {
3791                 nvidia,pins = "kb_row6_pr6";
3792                 nvidia,function = "kbc";
3793                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3794                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3795                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3796         };
3797         kb_row7_pr7 {
3798                 nvidia,pins = "kb_row7_pr7";
3799                 nvidia,function = "kbc";
3800                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3801                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3802                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3803         };
3804         kb_row8_ps0 {
3805                 nvidia,pins = "kb_row8_ps0";
3806                 nvidia,function = "kbc";
3807                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3808                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3809                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3810         };
3811         kb_row9_ps1 {
3812                 nvidia,pins = "kb_row9_ps1";
3813                 nvidia,function = "kbc";
3814                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3815                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3816                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3817         };
3818         kb_row10_ps2 {
3819                 nvidia,pins = "kb_row10_ps2";
3820                 nvidia,function = "kbc";
3821                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3822                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3823                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3824         };
3825         kb_row11_ps3 {
3826                 nvidia,pins = "kb_row11_ps3";
3827                 nvidia,function = "kbc";
3828                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3829                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3830                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3831         };
3832         kb_row12_ps4 {
3833                 nvidia,pins = "kb_row12_ps4";
3834                 nvidia,function = "kbc";
3835                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3836                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3837                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3838         };
3839         kb_row13_ps5 {
3840                 nvidia,pins = "kb_row13_ps5";
3841                 nvidia,function = "kbc";
3842                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3843                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3844                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3845         };
3846         kb_row14_ps6 {
3847                 nvidia,pins = "kb_row14_ps6";
3848                 nvidia,function = "kbc";
3849                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3850                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3851                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3852         };
3853         kb_row15_ps7 {
3854                 nvidia,pins = "kb_row15_ps7";
3855                 nvidia,function = "kbc";
3856                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3857                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3858                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3859         };
3860         vi_pclk_pt0 {
3861                 nvidia,pins = "vi_pclk_pt0";
3862                 nvidia,function = "rsvd1";
3863                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3864                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3865                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3866         };
3867         vi_mclk_pt1 {
3868                 nvidia,pins = "vi_mclk_pt1";
3869                 nvidia,function = "vi";
3870                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3871                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3872                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3873         };
3874         vi_d10_pt2 {
3875                 nvidia,pins = "vi_d10_pt2";
3876                 nvidia,function = "ddr";
3877                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3878                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3879                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3880         };
3881         vi_d11_pt3 {
3882                 nvidia,pins = "vi_d11_pt3";
3883                 nvidia,function = "ddr";
3884                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3885                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3886                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3887         };
3888         vi_d0_pt4 {
3889                 nvidia,pins = "vi_d0_pt4";
3890                 nvidia,function = "ddr";
3891                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3892                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3893                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3894         };
3895         gen2_i2c_scl_pt5 {
3896                 nvidia,pins = "gen2_i2c_scl_pt5";
3897                 nvidia,function = "i2c2";
3898                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3899                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3900                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3901                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
3902         };
3903         gen2_i2c_sda_pt6 {
3904                 nvidia,pins = "gen2_i2c_sda_pt6";
3905                 nvidia,function = "i2c2";
3906                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3907                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3908                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3909                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
3910         };
3911         sdmmc4_cmd_pt7 {
3912                 nvidia,pins = "sdmmc4_cmd_pt7";
3913                 nvidia,function = "sdmmc4";
3914                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3915                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3916                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3917                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
3918         };
3919         pu0 {
3920                 nvidia,pins = "pu0";
3921                 nvidia,function = "owr";
3922                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3923                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3924                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3925         };
3926         pu1 {
3927                 nvidia,pins = "pu1";
3928                 nvidia,function = "rsvd1";
3929                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3930                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3931                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3932         };
3933         pu2 {
3934                 nvidia,pins = "pu2";
3935                 nvidia,function = "rsvd1";
3936                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3937                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3938                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3939         };
3940         pu3 {
3941                 nvidia,pins = "pu3";
3942                 nvidia,function = "pwm0";
3943                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3944                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3945                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3946         };
3947         pu4 {
3948                 nvidia,pins = "pu4";
3949                 nvidia,function = "pwm1";
3950                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3951                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3952                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3953         };
3954         pu5 {
3955                 nvidia,pins = "pu5";
3956                 nvidia,function = "rsvd4";
3957                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3958                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3959                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3960         };
3961         pu6 {
3962                 nvidia,pins = "pu6";
3963                 nvidia,function = "pwm3";
3964                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3965                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3966                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3967         };
3968         jtag_rtck_pu7 {
3969                 nvidia,pins = "jtag_rtck_pu7";
3970                 nvidia,function = "rtck";
3971                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3972                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3973                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3974         };
3975         pv0 {
3976                 nvidia,pins = "pv0";
3977                 nvidia,function = "rsvd1";
3978                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
3979                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
3980                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
3981         };
3982         pv1 {
3983                 nvidia,pins = "pv1";
3984                 nvidia,function = "rsvd1";
3985                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3986                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3987                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3988         };
3989         pv2 {
3990                 nvidia,pins = "pv2";
3991                 nvidia,function = "owr";
3992                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3993                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
3994                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
3995         };
3996         pv3 {
3997                 nvidia,pins = "pv3";
3998                 nvidia,function = "clk_12m_out";
3999                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4000                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4001                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4002         };
4003         ddc_scl_pv4 {
4004                 nvidia,pins = "ddc_scl_pv4";
4005                 nvidia,function = "i2c4";
4006                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4007                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4008                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4009         };
4010         ddc_sda_pv5 {
4011                 nvidia,pins = "ddc_sda_pv5";
4012                 nvidia,function = "i2c4";
4013                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4014                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4015                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4016         };
4017         crt_hsync_pv6 {
4018                 nvidia,pins = "crt_hsync_pv6";
4019                 nvidia,function = "crt";
4020                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4021                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4022                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4023         };
4024         crt_vsync_pv7 {
4025                 nvidia,pins = "crt_vsync_pv7";
4026                 nvidia,function = "crt";
4027                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4028                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4029                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4030         };
4031         lcd_cs1_n_pw0 {
4032                 nvidia,pins = "lcd_cs1_n_pw0";
4033                 nvidia,function = "displaya";
4034                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4035                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4036                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4037         };
4038         lcd_m1_pw1 {
4039                 nvidia,pins = "lcd_m1_pw1";
4040                 nvidia,function = "displaya";
4041                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
4042                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4043                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4044         };
4045         spi2_cs1_n_pw2 {
4046                 nvidia,pins = "spi2_cs1_n_pw2";
4047                 nvidia,function = "spi2";
4048                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4049                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4050                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4051         };
4052         clk1_out_pw4 {
4053                 nvidia,pins = "clk1_out_pw4";
4054                 nvidia,function = "extperiph1";
4055                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4056                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4057                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4058         };
4059         clk2_out_pw5 {
4060                 nvidia,pins = "clk2_out_pw5";
4061                 nvidia,function = "extperiph2";
4062                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4063                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4064                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4065         };
4066         uart3_txd_pw6 {
4067                 nvidia,pins = "uart3_txd_pw6";
4068                 nvidia,function = "uartc";
4069                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4070                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4071                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4072         };
4073         uart3_rxd_pw7 {
4074                 nvidia,pins = "uart3_rxd_pw7";
4075                 nvidia,function = "uartc";
4076                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4077                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4078                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4079         };
4080         spi2_sck_px2 {
4081                 nvidia,pins = "spi2_sck_px2";
4082                 nvidia,function = "gmi";
4083                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4084                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4085                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4086         };
4087         spi1_mosi_px4 {
4088                 nvidia,pins = "spi1_mosi_px4";
4089                 nvidia,function = "spi1";
4090                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4091                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4092                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4093         };
4094         spi1_sck_px5 {
4095                 nvidia,pins = "spi1_sck_px5";
4096                 nvidia,function = "spi1";
4097                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4098                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4099                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4100         };
4101         spi1_cs0_n_px6 {
4102                 nvidia,pins = "spi1_cs0_n_px6";
4103                 nvidia,function = "spi1";
4104                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4105                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4106                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4107         };
4108         spi1_miso_px7 {
4109                 nvidia,pins = "spi1_miso_px7";
4110                 nvidia,function = "spi1";
4111                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4112                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4113                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4114         };
4115         ulpi_clk_py0 {
4116                 nvidia,pins = "ulpi_clk_py0";
4117                 nvidia,function = "uartd";
4118                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4119                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4120                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4121         };
4122         ulpi_dir_py1 {
4123                 nvidia,pins = "ulpi_dir_py1";
4124                 nvidia,function = "uartd";
4125                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4126                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4127                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4128         };
4129         ulpi_nxt_py2 {
4130                 nvidia,pins = "ulpi_nxt_py2";
4131                 nvidia,function = "uartd";
4132                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4133                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4134                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4135         };
4136         ulpi_stp_py3 {
4137                 nvidia,pins = "ulpi_stp_py3";
4138                 nvidia,function = "uartd";
4139                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4140                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4141                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4142         };
4143         sdmmc1_dat3_py4 {
4144                 nvidia,pins = "sdmmc1_dat3_py4";
4145                 nvidia,function = "sdmmc1";
4146                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4147                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4148                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4149         };
4150         sdmmc1_dat2_py5 {
4151                 nvidia,pins = "sdmmc1_dat2_py5";
4152                 nvidia,function = "sdmmc1";
4153                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4154                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4155                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4156         };
4157         sdmmc1_dat1_py6 {
4158                 nvidia,pins = "sdmmc1_dat1_py6";
4159                 nvidia,function = "sdmmc1";
4160                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4161                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4162                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4163         };
4164         sdmmc1_dat0_py7 {
4165                 nvidia,pins = "sdmmc1_dat0_py7";
4166                 nvidia,function = "sdmmc1";
4167                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4168                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4169                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4170         };
4171         sdmmc1_clk_pz0 {
4172                 nvidia,pins = "sdmmc1_clk_pz0";
4173                 nvidia,function = "sdmmc1";
4174                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4175                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4176                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4177         };
4178         sdmmc1_cmd_pz1 {
4179                 nvidia,pins = "sdmmc1_cmd_pz1";
4180                 nvidia,function = "sdmmc1";
4181                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4182                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4183                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4184         };
4185         lcd_sdin_pz2 {
4186                 nvidia,pins = "lcd_sdin_pz2";
4187                 nvidia,function = "displaya";
4188                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4189                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4190                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4191         };
4192         lcd_wr_n_pz3 {
4193                 nvidia,pins = "lcd_wr_n_pz3";
4194                 nvidia,function = "displaya";
4195                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4196                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4197                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4198         };
4199         lcd_sck_pz4 {
4200                 nvidia,pins = "lcd_sck_pz4";
4201                 nvidia,function = "displaya";
4202                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4203                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4204                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4205         };
4206         sys_clk_req_pz5 {
4207                 nvidia,pins = "sys_clk_req_pz5";
4208                 nvidia,function = "sysclk";
4209                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4210                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4211                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4212         };
4213         pwr_i2c_scl_pz6 {
4214                 nvidia,pins = "pwr_i2c_scl_pz6";
4215                 nvidia,function = "i2cpwr";
4216                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4217                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4218                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4219                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4220         };
4221         pwr_i2c_sda_pz7 {
4222                 nvidia,pins = "pwr_i2c_sda_pz7";
4223                 nvidia,function = "i2cpwr";
4224                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4225                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4226                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4227                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
4228         };
4229         sdmmc4_dat0_paa0 {
4230                 nvidia,pins = "sdmmc4_dat0_paa0";
4231                 nvidia,function = "sdmmc4";
4232                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4233                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4234                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4235                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4236         };
4237         sdmmc4_dat1_paa1 {
4238                 nvidia,pins = "sdmmc4_dat1_paa1";
4239                 nvidia,function = "sdmmc4";
4240                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4241                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4242                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4243                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4244         };
4245         sdmmc4_dat2_paa2 {
4246                 nvidia,pins = "sdmmc4_dat2_paa2";
4247                 nvidia,function = "sdmmc4";
4248                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4249                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4250                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4251                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4252         };
4253         sdmmc4_dat3_paa3 {
4254                 nvidia,pins = "sdmmc4_dat3_paa3";
4255                 nvidia,function = "sdmmc4";
4256                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4257                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4258                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4259                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4260         };
4261         sdmmc4_dat4_paa4 {
4262                 nvidia,pins = "sdmmc4_dat4_paa4";
4263                 nvidia,function = "sdmmc4";
4264                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4265                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4266                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4267                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4268         };
4269         sdmmc4_dat5_paa5 {
4270                 nvidia,pins = "sdmmc4_dat5_paa5";
4271                 nvidia,function = "sdmmc4";
4272                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4273                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4274                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4275                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4276         };
4277         sdmmc4_dat6_paa6 {
4278                 nvidia,pins = "sdmmc4_dat6_paa6";
4279                 nvidia,function = "sdmmc4";
4280                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4281                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4282                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4283                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4284         };
4285         sdmmc4_dat7_paa7 {
4286                 nvidia,pins = "sdmmc4_dat7_paa7";
4287                 nvidia,function = "sdmmc4";
4288                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
4289                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4290                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4291                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4292         };
4293         pbb0 {
4294                 nvidia,pins = "pbb0";
4295                 nvidia,function = "i2s4";
4296                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4297                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4298                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4299         };
4300         cam_i2c_scl_pbb1 {
4301                 nvidia,pins = "cam_i2c_scl_pbb1";
4302                 nvidia,function = "i2c3";
4303                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4304                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4305                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4306                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
4307         };
4308         cam_i2c_sda_pbb2 {
4309                 nvidia,pins = "cam_i2c_sda_pbb2";
4310                 nvidia,function = "i2c3";
4311                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4312                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4313                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4314                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
4315         };
4316         pbb3 {
4317                 nvidia,pins = "pbb3";
4318                 nvidia,function = "vgp3";
4319                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4320                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4321                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4322         };
4323         pbb4 {
4324                 nvidia,pins = "pbb4";
4325                 nvidia,function = "vgp4";
4326                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4327                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4328                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4329         };
4330         pbb5 {
4331                 nvidia,pins = "pbb5";
4332                 nvidia,function = "vgp5";
4333                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4334                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4335                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4336         };
4337         pbb6 {
4338                 nvidia,pins = "pbb6";
4339                 nvidia,function = "vgp6";
4340                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4341                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4342                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4343         };
4344         pbb7 {
4345                 nvidia,pins = "pbb7";
4346                 nvidia,function = "i2s4";
4347                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4348                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4349                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4350         };
4351         cam_mclk_pcc0 {
4352                 nvidia,pins = "cam_mclk_pcc0";
4353                 nvidia,function = "vi_alt3";
4354                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4355                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4356                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4357         };
4358         pcc1 {
4359                 nvidia,pins = "pcc1";
4360                 nvidia,function = "i2s4";
4361                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4362                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4363                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4364         };
4365         pcc2 {
4366                 nvidia,pins = "pcc2";
4367                 nvidia,function = "i2s4";
4368                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4369                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4370                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4371         };
4372         sdmmc4_rst_n_pcc3 {
4373                 nvidia,pins = "sdmmc4_rst_n_pcc3";
4374                 nvidia,function = "sdmmc4";
4375                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
4376                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4377                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4378                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4379         };
4380         sdmmc4_clk_pcc4 {
4381                 nvidia,pins = "sdmmc4_clk_pcc4";
4382                 nvidia,function = "sdmmc4";
4383                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4384                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4385                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4386                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
4387         };
4388         clk2_req_pcc5 {
4389                 nvidia,pins = "clk2_req_pcc5";
4390                 nvidia,function = "dap";
4391                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4392                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4393                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4394         };
4395         pex_l2_rst_n_pcc6 {
4396                 nvidia,pins = "pex_l2_rst_n_pcc6";
4397                 nvidia,function = "pcie";
4398                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4399                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4400                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4401         };
4402         pex_l2_clkreq_n_pcc7 {
4403                 nvidia,pins = "pex_l2_clkreq_n_pcc7";
4404                 nvidia,function = "pcie";
4405                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4406                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4407                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4408         };
4409         pex_l0_prsnt_n_pdd0 {
4410                 nvidia,pins = "pex_l0_prsnt_n_pdd0";
4411                 nvidia,function = "pcie";
4412                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4413                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4414                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4415         };
4416         pex_l0_rst_n_pdd1 {
4417                 nvidia,pins = "pex_l0_rst_n_pdd1";
4418                 nvidia,function = "pcie";
4419                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4420                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4421                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4422         };
4423         pex_l0_clkreq_n_pdd2 {
4424                 nvidia,pins = "pex_l0_clkreq_n_pdd2";
4425                 nvidia,function = "pcie";
4426                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4427                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4428                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4429         };
4430         pex_wake_n_pdd3 {
4431                 nvidia,pins = "pex_wake_n_pdd3";
4432                 nvidia,function = "pcie";
4433                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4434                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4435                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4436         };
4437         pex_l1_prsnt_n_pdd4 {
4438                 nvidia,pins = "pex_l1_prsnt_n_pdd4";
4439                 nvidia,function = "pcie";
4440                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4441                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4442                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4443         };
4444         pex_l1_rst_n_pdd5 {
4445                 nvidia,pins = "pex_l1_rst_n_pdd5";
4446                 nvidia,function = "pcie";
4447                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4448                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4449                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4450         };
4451         pex_l1_clkreq_n_pdd6 {
4452                 nvidia,pins = "pex_l1_clkreq_n_pdd6";
4453                 nvidia,function = "pcie";
4454                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4455                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4456                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4457         };
4458         pex_l2_prsnt_n_pdd7 {
4459                 nvidia,pins = "pex_l2_prsnt_n_pdd7";
4460                 nvidia,function = "pcie";
4461                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4462                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4463                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4464         };
4465         clk3_out_pee0 {
4466                 nvidia,pins = "clk3_out_pee0";
4467                 nvidia,function = "extperiph3";
4468                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4469                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4470                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4471         };
4472         clk3_req_pee1 {
4473                 nvidia,pins = "clk3_req_pee1";
4474                 nvidia,function = "dev3";
4475                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4476                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4477                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4478         };
4479         clk1_req_pee2 {
4480                 nvidia,pins = "clk1_req_pee2";
4481                 nvidia,function = "dap";
4482                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4483                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4484                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4485         };
4486         hdmi_cec_pee3 {
4487                 nvidia,pins = "hdmi_cec_pee3";
4488                 nvidia,function = "cec";
4489                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4490                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
4491                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
4492                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
4493         };
4494         owr {
4495                 nvidia,pins = "owr";
4496                 nvidia,function = "owr";
4497                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4498                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
4499                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4500         };
4501         drive_groups {
4502                 nvidia,pins = "drive_gma",
4503                               "drive_gmb",
4504                               "drive_gmc",
4505                               "drive_gmd";
4506                 nvidia,pull-down-strength = <9>;
4507                 nvidia,pull-up-strength = <9>;
4508                 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
4509                 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
4510         };
4511 };
4512
4513 &emc_icc_dvfs_opp_table {
4514         /delete-node/ opp@900000000,1350;
4515 };
4516
4517 &emc_bw_dfs_opp_table {
4518         /delete-node/ opp@900000000;
4519 };