arch/arm/boot/dts/tegra30-cardhu.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/input/input.h>
   3 #include <dt-bindings/thermal/thermal.h>
   4 #include "tegra30.dtsi"
   5 #include "tegra30-cpu-opp.dtsi"
   6 #include "tegra30-cpu-opp-microvolt.dtsi"
   7
   8 /**
   9  * This file contains common DT entry for all fab version of Cardhu.
  10  * There is multiple fab version of Cardhu starting from A01 to A07.
  11  * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
  12  * A02 will have different sets of GPIOs for fixed regulator compare to
  13  * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
  14  * compatible with fab version A04. Based on Cardhu fab version, the
  15  * related dts file need to be chosen like for Cardhu fab version A02,
  16  * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
  17  * tegra30-cardhu-a04.dts.
  18  * The identification of board is done in two ways, by looking the sticker
  19  * on PCB and by reading board id eeprom.
  20  * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
  21  * number is the fab version like here it is 002 and hence fab version A02.
  22  * The (downstream internal) U-Boot of Cardhu display the board-id as
  23  * follows:
  24  * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
  25  * In this Fab version is 02 i.e. A02.
  26  * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
  27  * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
  28  * wide.
  29  */
  30
  31 / {
  32         model = "NVIDIA Tegra30 Cardhu evaluation board";
  33         compatible = "nvidia,cardhu", "nvidia,tegra30";
  34
  35         aliases {
  36                 rtc0 = "/i2c@7000d000/tps65911@2d";
  37                 rtc1 = "/rtc@7000e000";
  38                 serial0 = &uarta;
  39                 serial1 = &uartc;
  40         };
  41
  42         chosen {
  43                 stdout-path = "serial0:115200n8";
  44         };
  45
  46         memory@80000000 {
  47                 reg = <0x80000000 0x40000000>;
  48         };
  49
  50         pcie@3000 {
  51                 status = "okay";
  52
  53                 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
  54                 avdd-pexb-supply = <&ldo1_reg>;
  55                 vdd-pexb-supply = <&ldo1_reg>;
  56                 avdd-pex-pll-supply = <&ldo1_reg>;
  57                 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
  58                 vddio-pex-ctl-supply = <&sys_3v3_reg>;
  59                 avdd-plle-supply = <&ldo2_reg>;
  60
  61                 pci@1,0 {
  62                         nvidia,num-lanes = <4>;
  63                 };
  64
  65                 pci@2,0 {
  66                         nvidia,num-lanes = <1>;
  67                 };
  68
  69                 pci@3,0 {
  70                         status = "okay";
  71                         nvidia,num-lanes = <1>;
  72                 };
  73         };
  74
  75         host1x@50000000 {
  76                 dc@54200000 {
  77                         rgb {
  78                                 status = "okay";
  79
  80                                 nvidia,panel = <&panel>;
  81                         };
  82                 };
  83         };
  84
  85         pinmux@70000868 {
  86                 pinctrl-names = "default";
  87                 pinctrl-0 = <&state_default>;
  88
  89                 state_default: pinmux {
  90                         sdmmc1_clk_pz0 {
  91                                 nvidia,pins = "sdmmc1_clk_pz0";
  92                                 nvidia,function = "sdmmc1";
  93                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  94                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  95                         };
  96                         sdmmc1_cmd_pz1 {
  97                                 nvidia,pins =   "sdmmc1_cmd_pz1",
  98                                                 "sdmmc1_dat0_py7",
  99                                                 "sdmmc1_dat1_py6",
 100                                                 "sdmmc1_dat2_py5",
 101                                                 "sdmmc1_dat3_py4";
 102                                 nvidia,function = "sdmmc1";
 103                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 104                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 105                         };
 106                         sdmmc3_clk_pa6 {
 107                                 nvidia,pins = "sdmmc3_clk_pa6";
 108                                 nvidia,function = "sdmmc3";
 109                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 110                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 111                         };
 112                         sdmmc3_cmd_pa7 {
 113                                 nvidia,pins =   "sdmmc3_cmd_pa7",
 114                                                 "sdmmc3_dat0_pb7",
 115                                                 "sdmmc3_dat1_pb6",
 116                                                 "sdmmc3_dat2_pb5",
 117                                                 "sdmmc3_dat3_pb4";
 118                                 nvidia,function = "sdmmc3";
 119                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 120                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 121                         };
 122                         sdmmc4_clk_pcc4 {
 123                                 nvidia,pins =   "sdmmc4_clk_pcc4",
 124                                                 "sdmmc4_rst_n_pcc3";
 125                                 nvidia,function = "sdmmc4";
 126                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 127                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 128                         };
 129                         sdmmc4_dat0_paa0 {
 130                                 nvidia,pins =   "sdmmc4_dat0_paa0",
 131                                                 "sdmmc4_dat1_paa1",
 132                                                 "sdmmc4_dat2_paa2",
 133                                                 "sdmmc4_dat3_paa3",
 134                                                 "sdmmc4_dat4_paa4",
 135                                                 "sdmmc4_dat5_paa5",
 136                                                 "sdmmc4_dat6_paa6",
 137                                                 "sdmmc4_dat7_paa7";
 138                                 nvidia,function = "sdmmc4";
 139                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 140                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 141                         };
 142                         dap2_fs_pa2 {
 143                                 nvidia,pins =   "dap2_fs_pa2",
 144                                                 "dap2_sclk_pa3",
 145                                                 "dap2_din_pa4",
 146                                                 "dap2_dout_pa5";
 147                                 nvidia,function = "i2s1";
 148                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 149                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 150                         };
 151                         sdio3 {
 152                                 nvidia,pins = "drive_sdio3";
 153                                 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
 154                                 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 155                                 nvidia,pull-down-strength = <46>;
 156                                 nvidia,pull-up-strength = <42>;
 157                                 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
 158                                 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
 159                         };
 160                         uart3_txd_pw6 {
 161                                 nvidia,pins =   "uart3_txd_pw6",
 162                                                 "uart3_cts_n_pa1",
 163                                                 "uart3_rts_n_pc0",
 164                                                 "uart3_rxd_pw7";
 165                                 nvidia,function = "uartc";
 166                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 167                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 168                         };
 169                 };
 170         };
 171
 172         serial@70006000 {
 173                 status = "okay";
 174         };
 175
 176         serial@70006200 {
 177                 compatible = "nvidia,tegra30-hsuart";
 178                 status = "okay";
 179         };
 180
 181         pwm@7000a000 {
 182                 status = "okay";
 183         };
 184
 185         panelddc: i2c@7000c000 {
 186                 status = "okay";
 187                 clock-frequency = <100000>;
 188         };
 189
 190         i2c@7000c400 {
 191                 status = "okay";
 192                 clock-frequency = <100000>;
 193         };
 194
 195         i2c@7000c500 {
 196                 status = "okay";
 197                 clock-frequency = <100000>;
 198
 199                 /* ALS and Proximity sensor */
 200                 isl29028@44 {
 201                         compatible = "isil,isl29028";
 202                         reg = <0x44>;
 203                         interrupt-parent = <&gpio>;
 204                         interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
 205                 };
 206
 207                 i2cmux@70 {
 208                         compatible = "nxp,pca9546";
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                         reg = <0x70>;
 212                         reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>;
 213                 };
 214         };
 215
 216         i2c@7000c700 {
 217                 status = "okay";
 218                 clock-frequency = <100000>;
 219         };
 220
 221         i2c@7000d000 {
 222                 status = "okay";
 223                 clock-frequency = <100000>;
 224
 225                 wm8903: wm8903@1a {
 226                         compatible = "wlf,wm8903";
 227                         reg = <0x1a>;
 228                         interrupt-parent = <&gpio>;
 229                         interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
 230
 231                         gpio-controller;
 232                         #gpio-cells = <2>;
 233
 234                         micdet-cfg = <0>;
 235                         micdet-delay = <100>;
 236                         gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
 237                 };
 238
 239                 pmic: tps65911@2d {
 240                         compatible = "ti,tps65911";
 241                         reg = <0x2d>;
 242
 243                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 244                         #interrupt-cells = <2>;
 245                         interrupt-controller;
 246                         wakeup-source;
 247
 248                         ti,system-power-controller;
 249
 250                         #gpio-cells = <2>;
 251                         gpio-controller;
 252
 253                         vcc1-supply = <&vdd_ac_bat_reg>;
 254                         vcc2-supply = <&vdd_ac_bat_reg>;
 255                         vcc3-supply = <&vio_reg>;
 256                         vcc4-supply = <&vdd_5v0_reg>;
 257                         vcc5-supply = <&vdd_ac_bat_reg>;
 258                         vcc6-supply = <&vdd2_reg>;
 259                         vcc7-supply = <&vdd_ac_bat_reg>;
 260                         vccio-supply = <&vdd_ac_bat_reg>;
 261
 262                         regulators {
 263                                 vdd1_reg: vdd1 {
 264                                         regulator-name = "vddio_ddr_1v2";
 265                                         regulator-min-microvolt = <1200000>;
 266                                         regulator-max-microvolt = <1200000>;
 267                                         regulator-always-on;
 268                                 };
 269
 270                                 vdd2_reg: vdd2 {
 271                                         regulator-name = "vdd_1v5_gen";
 272                                         regulator-min-microvolt = <1500000>;
 273                                         regulator-max-microvolt = <1500000>;
 274                                         regulator-always-on;
 275                                 };
 276
 277                                 vddctrl_reg: vddctrl {
 278                                         regulator-name = "vdd_cpu,vdd_sys";
 279                                         regulator-min-microvolt = <800000>;
 280                                         regulator-max-microvolt = <1250000>;
 281                                         regulator-coupled-with = <&vdd_core>;
 282                                         regulator-coupled-max-spread = <300000>;
 283                                         regulator-max-step-microvolt = <100000>;
 284                                         regulator-always-on;
 285
 286                                         nvidia,tegra-cpu-regulator;
 287                                 };
 288
 289                                 vio_reg: vio {
 290                                         regulator-name = "vdd_1v8_gen";
 291                                         regulator-min-microvolt = <1800000>;
 292                                         regulator-max-microvolt = <1800000>;
 293                                         regulator-always-on;
 294                                 };
 295
 296                                 ldo1_reg: ldo1 {
 297                                         regulator-name = "vdd_pexa,vdd_pexb";
 298                                         regulator-min-microvolt = <1050000>;
 299                                         regulator-max-microvolt = <1050000>;
 300                                 };
 301
 302                                 ldo2_reg: ldo2 {
 303                                         regulator-name = "vdd_sata,avdd_plle";
 304                                         regulator-min-microvolt = <1050000>;
 305                                         regulator-max-microvolt = <1050000>;
 306                                 };
 307
 308                                 /* LDO3 is not connected to anything */
 309
 310                                 ldo4_reg: ldo4 {
 311                                         regulator-name = "vdd_rtc";
 312                                         regulator-min-microvolt = <1200000>;
 313                                         regulator-max-microvolt = <1200000>;
 314                                         regulator-always-on;
 315                                 };
 316
 317                                 ldo5_reg: ldo5 {
 318                                         regulator-name = "vddio_sdmmc,avdd_vdac";
 319                                         regulator-min-microvolt = <3300000>;
 320                                         regulator-max-microvolt = <3300000>;
 321                                         regulator-always-on;
 322                                 };
 323
 324                                 ldo6_reg: ldo6 {
 325                                         regulator-name = "avdd_dsi_csi,pwrdet_mipi";
 326                                         regulator-min-microvolt = <1200000>;
 327                                         regulator-max-microvolt = <1200000>;
 328                                 };
 329
 330                                 ldo7_reg: ldo7 {
 331                                         regulator-name = "vdd_pllm,x,u,a_p_c_s";
 332                                         regulator-min-microvolt = <1200000>;
 333                                         regulator-max-microvolt = <1200000>;
 334                                         regulator-always-on;
 335                                 };
 336
 337                                 ldo8_reg: ldo8 {
 338                                         regulator-name = "vdd_ddr_hs";
 339                                         regulator-min-microvolt = <1000000>;
 340                                         regulator-max-microvolt = <1000000>;
 341                                         regulator-always-on;
 342                                 };
 343                         };
 344                 };
 345
 346                 nct1008: temperature-sensor@4c {
 347                         compatible = "onnn,nct1008";
 348                         reg = <0x4c>;
 349                         vcc-supply = <&sys_3v3_reg>;
 350                         interrupt-parent = <&gpio>;
 351                         interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
 352                         #thermal-sensor-cells = <1>;
 353                 };
 354
 355                 vdd_core: tps62361@60 {
 356                         compatible = "ti,tps62361";
 357                         reg = <0x60>;
 358
 359                         regulator-name = "tps62361-vout";
 360                         regulator-min-microvolt = <500000>;
 361                         regulator-max-microvolt = <1500000>;
 362                         regulator-coupled-with = <&vddctrl_reg>;
 363                         regulator-coupled-max-spread = <300000>;
 364                         regulator-max-step-microvolt = <100000>;
 365                         regulator-boot-on;
 366                         regulator-always-on;
 367                         ti,vsel0-state-high;
 368                         ti,vsel1-state-high;
 369
 370                         nvidia,tegra-core-regulator;
 371                 };
 372         };
 373
 374         spi@7000da00 {
 375                 status = "okay";
 376                 spi-max-frequency = <25000000>;
 377                 spi-flash@1 {
 378                         compatible = "winbond,w25q32", "jedec,spi-nor";
 379                         reg = <1>;
 380                         spi-max-frequency = <20000000>;
 381                 };
 382         };
 383
 384         pmc@7000e400 {
 385                 status = "okay";
 386                 nvidia,invert-interrupt;
 387                 nvidia,suspend-mode = <1>;
 388                 nvidia,cpu-pwr-good-time = <2000>;
 389                 nvidia,cpu-pwr-off-time = <200>;
 390                 nvidia,core-pwr-good-time = <3845 3845>;
 391                 nvidia,core-pwr-off-time = <0>;
 392                 nvidia,core-power-req-active-high;
 393                 nvidia,sys-clock-req-active-high;
 394         };
 395
 396         ahub@70080000 {
 397                 i2s@70080400 {
 398                         status = "okay";
 399                 };
 400         };
 401
 402         mmc@78000000 {
 403                 status = "okay";
 404                 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
 405                 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
 406                 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
 407                 bus-width = <4>;
 408         };
 409
 410         mmc@78000600 {
 411                 status = "okay";
 412                 bus-width = <8>;
 413                 non-removable;
 414         };
 415
 416         usb@7d008000 {
 417                 status = "okay";
 418         };
 419
 420         usb-phy@7d008000 {
 421                 vbus-supply = <&usb3_vbus_reg>;
 422                 status = "okay";
 423         };
 424
 425         backlight: backlight {
 426                 compatible = "pwm-backlight";
 427
 428                 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
 429                 power-supply = <&vdd_bl_reg>;
 430                 pwms = <&pwm 0 5000000>;
 431
 432                 brightness-levels = <0 4 8 16 32 64 128 255>;
 433                 default-brightness-level = <6>;
 434         };
 435
 436         clk32k_in: clock@0 {
 437                 compatible = "fixed-clock";
 438                 clock-frequency = <32768>;
 439                 #clock-cells = <0>;
 440         };
 441
 442         cpus {
 443                 cpu0: cpu@0 {
 444                         cpu-supply = <&vddctrl_reg>;
 445                         operating-points-v2 = <&cpu0_opp_table>;
 446                         #cooling-cells = <2>;
 447                 };
 448
 449                 cpu1: cpu@1 {
 450                         cpu-supply = <&vddctrl_reg>;
 451                         operating-points-v2 = <&cpu0_opp_table>;
 452                         #cooling-cells = <2>;
 453                 };
 454
 455                 cpu2: cpu@2 {
 456                         cpu-supply = <&vddctrl_reg>;
 457                         operating-points-v2 = <&cpu0_opp_table>;
 458                         #cooling-cells = <2>;
 459                 };
 460
 461                 cpu3: cpu@3 {
 462                         cpu-supply = <&vddctrl_reg>;
 463                         operating-points-v2 = <&cpu0_opp_table>;
 464                         #cooling-cells = <2>;
 465                 };
 466         };
 467
 468         panel: panel {
 469                 compatible = "chunghwa,claa101wb01";
 470                 ddc-i2c-bus = <&panelddc>;
 471
 472                 power-supply = <&vdd_pnl1_reg>;
 473                 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
 474
 475                 backlight = <&backlight>;
 476         };
 477
 478         vdd_ac_bat_reg: regulator@0 {
 479                 compatible = "regulator-fixed";
 480                 regulator-name = "vdd_ac_bat";
 481                 regulator-min-microvolt = <5000000>;
 482                 regulator-max-microvolt = <5000000>;
 483                 regulator-always-on;
 484         };
 485
 486         cam_1v8_reg: regulator@1 {
 487                 compatible = "regulator-fixed";
 488                 regulator-name = "cam_1v8";
 489                 regulator-min-microvolt = <1800000>;
 490                 regulator-max-microvolt = <1800000>;
 491                 enable-active-high;
 492                 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
 493                 vin-supply = <&vio_reg>;
 494         };
 495
 496         cp_5v_reg: regulator@2 {
 497                 compatible = "regulator-fixed";
 498                 regulator-name = "cp_5v";
 499                 regulator-min-microvolt = <5000000>;
 500                 regulator-max-microvolt = <5000000>;
 501                 regulator-boot-on;
 502                 regulator-always-on;
 503                 enable-active-high;
 504                 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 505         };
 506
 507         emmc_3v3_reg: regulator@3 {
 508                 compatible = "regulator-fixed";
 509                 regulator-name = "emmc_3v3";
 510                 regulator-min-microvolt = <3300000>;
 511                 regulator-max-microvolt = <3300000>;
 512                 regulator-always-on;
 513                 regulator-boot-on;
 514                 enable-active-high;
 515                 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
 516                 vin-supply = <&sys_3v3_reg>;
 517         };
 518
 519         modem_3v3_reg: regulator@4 {
 520                 compatible = "regulator-fixed";
 521                 regulator-name = "modem_3v3";
 522                 regulator-min-microvolt = <3300000>;
 523                 regulator-max-microvolt = <3300000>;
 524                 enable-active-high;
 525                 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
 526         };
 527
 528         pex_hvdd_3v3_reg: regulator@5 {
 529                 compatible = "regulator-fixed";
 530                 regulator-name = "pex_hvdd_3v3";
 531                 regulator-min-microvolt = <3300000>;
 532                 regulator-max-microvolt = <3300000>;
 533                 enable-active-high;
 534                 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
 535                 vin-supply = <&sys_3v3_reg>;
 536         };
 537
 538         vdd_cam1_ldo_reg: regulator@6 {
 539                 compatible = "regulator-fixed";
 540                 regulator-name = "vdd_cam1_ldo";
 541                 regulator-min-microvolt = <2800000>;
 542                 regulator-max-microvolt = <2800000>;
 543                 enable-active-high;
 544                 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
 545                 vin-supply = <&sys_3v3_reg>;
 546         };
 547
 548         vdd_cam2_ldo_reg: regulator@7 {
 549                 compatible = "regulator-fixed";
 550                 regulator-name = "vdd_cam2_ldo";
 551                 regulator-min-microvolt = <2800000>;
 552                 regulator-max-microvolt = <2800000>;
 553                 enable-active-high;
 554                 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
 555                 vin-supply = <&sys_3v3_reg>;
 556         };
 557
 558         vdd_cam3_ldo_reg: regulator@8 {
 559                 compatible = "regulator-fixed";
 560                 regulator-name = "vdd_cam3_ldo";
 561                 regulator-min-microvolt = <3300000>;
 562                 regulator-max-microvolt = <3300000>;
 563                 enable-active-high;
 564                 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
 565                 vin-supply = <&sys_3v3_reg>;
 566         };
 567
 568         vdd_com_reg: regulator@9 {
 569                 compatible = "regulator-fixed";
 570                 regulator-name = "vdd_com";
 571                 regulator-min-microvolt = <3300000>;
 572                 regulator-max-microvolt = <3300000>;
 573                 regulator-always-on;
 574                 regulator-boot-on;
 575                 enable-active-high;
 576                 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
 577                 vin-supply = <&sys_3v3_reg>;
 578         };
 579
 580         vdd_fuse_3v3_reg: regulator@10 {
 581                 compatible = "regulator-fixed";
 582                 regulator-name = "vdd_fuse_3v3";
 583                 regulator-min-microvolt = <3300000>;
 584                 regulator-max-microvolt = <3300000>;
 585                 enable-active-high;
 586                 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
 587                 vin-supply = <&sys_3v3_reg>;
 588         };
 589
 590         vdd_pnl1_reg: regulator@11 {
 591                 compatible = "regulator-fixed";
 592                 regulator-name = "vdd_pnl1";
 593                 regulator-min-microvolt = <3300000>;
 594                 regulator-max-microvolt = <3300000>;
 595                 regulator-always-on;
 596                 regulator-boot-on;
 597                 enable-active-high;
 598                 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
 599                 vin-supply = <&sys_3v3_reg>;
 600         };
 601
 602         vdd_vid_reg: regulator@12 {
 603                 compatible = "regulator-fixed";
 604                 regulator-name = "vddio_vid";
 605                 regulator-min-microvolt = <5000000>;
 606                 regulator-max-microvolt = <5000000>;
 607                 enable-active-high;
 608                 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
 609                 gpio-open-drain;
 610                 vin-supply = <&vdd_5v0_reg>;
 611         };
 612
 613         sound {
 614                 compatible = "nvidia,tegra-audio-wm8903-cardhu",
 615                              "nvidia,tegra-audio-wm8903";
 616                 nvidia,model = "NVIDIA Tegra Cardhu";
 617
 618                 nvidia,audio-routing =
 619                         "Headphone Jack", "HPOUTR",
 620                         "Headphone Jack", "HPOUTL",
 621                         "Int Spk", "ROP",
 622                         "Int Spk", "RON",
 623                         "Int Spk", "LOP",
 624                         "Int Spk", "LON",
 625                         "Mic Jack", "MICBIAS",
 626                         "IN1L", "Mic Jack";
 627
 628                 nvidia,i2s-controller = <&tegra_i2s1>;
 629                 nvidia,audio-codec = <&wm8903>;
 630
 631                 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
 632                 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
 633                         GPIO_ACTIVE_LOW>;
 634
 635                 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
 636                          <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
 637                          <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
 638                 clock-names = "pll_a", "pll_a_out0", "mclk";
 639
 640                 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
 641                                   <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
 642
 643                 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
 644                                          <&tegra_car TEGRA30_CLK_EXTERN1>;
 645         };
 646
 647         thermal-zones {
 648                 cpu-thermal {
 649                         polling-delay-passive = <1000>; /* milliseconds */
 650                         polling-delay = <5000>; /* milliseconds */
 651
 652                         thermal-sensors = <&nct1008 1>;
 653
 654                         trips {
 655                                 trip0: cpu-alert0 {
 656                                         /* throttle at 57C until temperature drops to 56.8C */
 657                                         temperature = <57000>;
 658                                         hysteresis = <200>;
 659                                         type = "passive";
 660                                 };
 661
 662                                 trip1: cpu-crit {
 663                                         /* shut down at 60C */
 664                                         temperature = <60000>;
 665                                         hysteresis = <2000>;
 666                                         type = "critical";
 667                                 };
 668                         };
 669
 670                         cooling-maps {
 671                                 map0 {
 672                                         trip = <&trip0>;
 673                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 674                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 675                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 676                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 677                                 };
 678                         };
 679                 };
 680         };
 681
 682         gpio-keys {
 683                 compatible = "gpio-keys";
 684
 685                 power {
 686                         label = "Power";
 687                         interrupt-parent = <&pmic>;
 688                         interrupts = <2 0>;
 689                         linux,code = <KEY_POWER>;
 690                         debounce-interval = <100>;
 691                         wakeup-source;
 692                 };
 693
 694                 volume-down {
 695                         label = "Volume Down";
 696                         gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
 697                         linux,code = <KEY_VOLUMEDOWN>;
 698                         debounce-interval = <10>;
 699                 };
 700
 701                 volume-up {
 702                         label = "Volume Up";
 703                         gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
 704                         linux,code = <KEY_VOLUMEUP>;
 705                         debounce-interval = <10>;
 706                 };
 707         };
 708 };