Merge tag 'block-5.14-2021-08-07' of git://git.kernel.dk/linux-block
[linux-2.6-microblaze.git] / arch / arm / boot / dts / tegra20-paz00.dts
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
6
7 #include "tegra20.dtsi"
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
10
11 / {
12         model = "Toshiba AC100 / Dynabook AZ";
13         compatible = "compal,paz00", "nvidia,tegra20";
14
15         aliases {
16                 rtc0 = "/i2c@7000d000/tps6586x@34";
17                 rtc1 = "/rtc@7000e000";
18                 serial0 = &uarta;
19                 serial1 = &uartc;
20         };
21
22         chosen {
23                 stdout-path = "serial0:115200n8";
24         };
25
26         memory@0 {
27                 reg = <0x00000000 0x20000000>;
28         };
29
30         host1x@50000000 {
31                 dc@54200000 {
32                         rgb {
33                                 status = "okay";
34
35                                 nvidia,panel = <&panel>;
36                         };
37                 };
38
39                 hdmi@54280000 {
40                         status = "okay";
41
42                         vdd-supply = <&hdmi_vdd_reg>;
43                         pll-supply = <&hdmi_pll_reg>;
44
45                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
46                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
47                                 GPIO_ACTIVE_HIGH>;
48                 };
49         };
50
51         pinmux@70000014 {
52                 pinctrl-names = "default";
53                 pinctrl-0 = <&state_default>;
54
55                 state_default: pinmux {
56                         ata {
57                                 nvidia,pins = "ata", "atc", "atd", "ate",
58                                         "dap2", "gmb", "gmc", "gmd", "spia",
59                                         "spib", "spic", "spid", "spie";
60                                 nvidia,function = "gmi";
61                         };
62                         atb {
63                                 nvidia,pins = "atb", "gma", "gme";
64                                 nvidia,function = "sdio4";
65                         };
66                         cdev1 {
67                                 nvidia,pins = "cdev1";
68                                 nvidia,function = "plla_out";
69                         };
70                         cdev2 {
71                                 nvidia,pins = "cdev2";
72                                 nvidia,function = "pllp_out4";
73                         };
74                         crtp {
75                                 nvidia,pins = "crtp";
76                                 nvidia,function = "crt";
77                         };
78                         csus {
79                                 nvidia,pins = "csus";
80                                 nvidia,function = "pllc_out1";
81                         };
82                         dap1 {
83                                 nvidia,pins = "dap1";
84                                 nvidia,function = "dap1";
85                         };
86                         dap3 {
87                                 nvidia,pins = "dap3";
88                                 nvidia,function = "dap3";
89                         };
90                         dap4 {
91                                 nvidia,pins = "dap4";
92                                 nvidia,function = "dap4";
93                         };
94                         ddc {
95                                 nvidia,pins = "ddc";
96                                 nvidia,function = "i2c2";
97                         };
98                         dta {
99                                 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
100                                 nvidia,function = "rsvd1";
101                         };
102                         dtf {
103                                 nvidia,pins = "dtf";
104                                 nvidia,function = "i2c3";
105                         };
106                         gpu {
107                                 nvidia,pins = "gpu", "sdb", "sdd";
108                                 nvidia,function = "pwm";
109                         };
110                         gpu7 {
111                                 nvidia,pins = "gpu7";
112                                 nvidia,function = "rtck";
113                         };
114                         gpv {
115                                 nvidia,pins = "gpv", "slxa", "slxk";
116                                 nvidia,function = "pcie";
117                         };
118                         hdint {
119                                 nvidia,pins = "hdint", "pta";
120                                 nvidia,function = "hdmi";
121                         };
122                         i2cp {
123                                 nvidia,pins = "i2cp";
124                                 nvidia,function = "i2cp";
125                         };
126                         irrx {
127                                 nvidia,pins = "irrx", "irtx";
128                                 nvidia,function = "uarta";
129                         };
130                         kbca {
131                                 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
132                                 nvidia,function = "kbc";
133                         };
134                         kbcb {
135                                 nvidia,pins = "kbcb", "kbcd";
136                                 nvidia,function = "sdio2";
137                         };
138                         lcsn {
139                                 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
140                                         "ld3", "ld4", "ld5", "ld6", "ld7",
141                                         "ld8", "ld9", "ld10", "ld11", "ld12",
142                                         "ld13", "ld14", "ld15", "ld16", "ld17",
143                                         "ldc", "ldi", "lhp0", "lhp1", "lhp2",
144                                         "lhs", "lm0", "lm1", "lpp", "lpw0",
145                                         "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
146                                         "lsda", "lsdi", "lspi", "lvp0", "lvp1",
147                                         "lvs";
148                                 nvidia,function = "displaya";
149                         };
150                         owc {
151                                 nvidia,pins = "owc";
152                                 nvidia,function = "owr";
153                         };
154                         pmc {
155                                 nvidia,pins = "pmc";
156                                 nvidia,function = "pwr_on";
157                         };
158                         rm {
159                                 nvidia,pins = "rm";
160                                 nvidia,function = "i2c1";
161                         };
162                         sdc {
163                                 nvidia,pins = "sdc";
164                                 nvidia,function = "twc";
165                         };
166                         sdio1 {
167                                 nvidia,pins = "sdio1";
168                                 nvidia,function = "sdio1";
169                         };
170                         slxc {
171                                 nvidia,pins = "slxc", "slxd";
172                                 nvidia,function = "spi4";
173                         };
174                         spdi {
175                                 nvidia,pins = "spdi", "spdo";
176                                 nvidia,function = "rsvd2";
177                         };
178                         spif {
179                                 nvidia,pins = "spif", "uac";
180                                 nvidia,function = "rsvd4";
181                         };
182                         spig {
183                                 nvidia,pins = "spig", "spih";
184                                 nvidia,function = "spi2_alt";
185                         };
186                         uaa {
187                                 nvidia,pins = "uaa", "uab", "uda";
188                                 nvidia,function = "ulpi";
189                         };
190                         uad {
191                                 nvidia,pins = "uad";
192                                 nvidia,function = "spdif";
193                         };
194                         uca {
195                                 nvidia,pins = "uca", "ucb";
196                                 nvidia,function = "uartc";
197                         };
198                         conf_ata {
199                                 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
200                                         "cdev1", "cdev2", "dap1", "dap2", "dtf",
201                                         "gma", "gmb", "gmc", "gmd", "gme",
202                                         "gpu", "gpu7", "gpv", "i2cp", "pta",
203                                         "rm", "sdio1", "slxk", "spdo", "uac",
204                                         "uda";
205                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
207                         };
208                         conf_ck32 {
209                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
210                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
211                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
212                         };
213                         conf_crtp {
214                                 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
215                                         "dtc", "dte", "slxa", "slxc", "slxd",
216                                         "spdi";
217                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
218                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
219                         };
220                         conf_csus {
221                                 nvidia,pins = "csus", "spia", "spib", "spid",
222                                         "spif";
223                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
224                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
225                         };
226                         conf_ddc {
227                                 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
228                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
229                                         "spic", "spig", "uaa", "uab";
230                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
231                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
232                         };
233                         conf_dta {
234                                 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
235                                         "spie", "spih", "uad", "uca", "ucb";
236                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
237                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
238                         };
239                         conf_hdint {
240                                 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
241                                         "ld3", "ld4", "ld5", "ld6", "ld7",
242                                         "ld8", "ld9", "ld10", "ld11", "ld12",
243                                         "ld13", "ld14", "ld15", "ld16", "ld17",
244                                         "ldc", "ldi", "lhs", "lsc0", "lspi",
245                                         "lvs", "pmc";
246                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
247                         };
248                         conf_lc {
249                                 nvidia,pins = "lc", "ls";
250                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
251                         };
252                         conf_lcsn {
253                                 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
254                                         "lm0", "lm1", "lpp", "lpw0", "lpw1",
255                                         "lpw2", "lsc1", "lsck", "lsda", "lsdi",
256                                         "lvp0", "lvp1", "sdb";
257                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
258                         };
259                         conf_ld17_0 {
260                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
261                                         "ld23_22";
262                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
263                         };
264                 };
265         };
266
267         i2s@70002800 {
268                 status = "okay";
269         };
270
271         serial@70006000 {
272                 status = "okay";
273         };
274
275         serial@70006200 {
276                 status = "okay";
277         };
278
279         pwm: pwm@7000a000 {
280                 status = "okay";
281         };
282
283         lvds_ddc: i2c@7000c000 {
284                 status = "okay";
285                 clock-frequency = <400000>;
286
287                 alc5632: alc5632@1e {
288                         compatible = "realtek,alc5632";
289                         reg = <0x1e>;
290                         gpio-controller;
291                         #gpio-cells = <2>;
292                 };
293         };
294
295         hdmi_ddc: i2c@7000c400 {
296                 status = "okay";
297                 clock-frequency = <100000>;
298         };
299
300         nvec@7000c500 {
301                 compatible = "nvidia,nvec";
302                 reg = <0x7000c500 0x100>;
303                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
304                 #address-cells = <1>;
305                 #size-cells = <0>;
306                 clock-frequency = <80000>;
307                 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
308                 slave-addr = <138>;
309                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
310                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
311                 clock-names = "div-clk", "fast-clk";
312                 resets = <&tegra_car 67>;
313                 reset-names = "i2c";
314         };
315
316         memory-controller@7000f400 {
317                 nvidia,use-ram-code;
318
319                 emc-tables@0 {
320                         nvidia,ram-code = <0x0>;
321                         #address-cells = <1>;
322                         #size-cells = <0>;
323                         reg = <0>;
324
325                         emc-table@166500 {
326                                 reg = <166500>;
327                                 compatible = "nvidia,tegra20-emc-table";
328                                 clock-frequency = <166500>;
329                                 nvidia,emc-registers = <0x0000000a 0x00000016
330                                         0x00000008 0x00000003 0x00000004 0x00000004
331                                         0x00000002 0x0000000c 0x00000003 0x00000003
332                                         0x00000002 0x00000001 0x00000004 0x00000005
333                                         0x00000004 0x00000009 0x0000000d 0x000004df
334                                         0x00000000 0x00000003 0x00000003 0x00000003
335                                         0x00000003 0x00000001 0x0000000a 0x000000c8
336                                         0x00000003 0x00000006 0x00000004 0x00000008
337                                         0x00000002 0x00000000 0x00000000 0x00000002
338                                         0x00000000 0x00000000 0x00000083 0xe03b0323
339                                         0x007fe010 0x00001414 0x00000000 0x00000000
340                                         0x00000000 0x00000000 0x00000000 0x00000000>;
341                         };
342
343                         emc-table@333000 {
344                                 reg = <333000>;
345                                 compatible = "nvidia,tegra20-emc-table";
346                                 clock-frequency = <333000>;
347                                 nvidia,emc-registers = <0x00000018 0x00000033
348                                         0x00000012 0x00000004 0x00000004 0x00000005
349                                         0x00000003 0x0000000c 0x00000006 0x00000006
350                                         0x00000003 0x00000001 0x00000004 0x00000005
351                                         0x00000004 0x00000009 0x0000000d 0x00000bff
352                                         0x00000000 0x00000003 0x00000003 0x00000006
353                                         0x00000006 0x00000001 0x00000011 0x000000c8
354                                         0x00000003 0x0000000e 0x00000007 0x00000008
355                                         0x00000002 0x00000000 0x00000000 0x00000002
356                                         0x00000000 0x00000000 0x00000083 0xf0440303
357                                         0x007fe010 0x00001414 0x00000000 0x00000000
358                                         0x00000000 0x00000000 0x00000000 0x00000000>;
359                         };
360                 };
361         };
362
363         i2c@7000d000 {
364                 status = "okay";
365                 clock-frequency = <400000>;
366
367                 pmic: tps6586x@34 {
368                         compatible = "ti,tps6586x";
369                         reg = <0x34>;
370                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
371
372                         #gpio-cells = <2>;
373                         gpio-controller;
374
375                         sys-supply = <&p5valw_reg>;
376                         vin-sm0-supply = <&sys_reg>;
377                         vin-sm1-supply = <&sys_reg>;
378                         vin-sm2-supply = <&sys_reg>;
379                         vinldo01-supply = <&sm2_reg>;
380                         vinldo23-supply = <&sm2_reg>;
381                         vinldo4-supply = <&sm2_reg>;
382                         vinldo678-supply = <&sm2_reg>;
383                         vinldo9-supply = <&sm2_reg>;
384
385                         regulators {
386                                 sys_reg: sys {
387                                         regulator-name = "vdd_sys";
388                                         regulator-always-on;
389                                 };
390
391                                 core_vdd_reg: sm0 {
392                                         regulator-name = "+1.2vs_sm0,vdd_core";
393                                         regulator-min-microvolt = <950000>;
394                                         regulator-max-microvolt = <1300000>;
395                                         regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
396                                         regulator-coupled-max-spread = <170000 550000>;
397                                         regulator-always-on;
398
399                                         nvidia,tegra-core-regulator;
400                                 };
401
402                                 cpu_vdd_reg: sm1 {
403                                         regulator-name = "+1.0vs_sm1,vdd_cpu";
404                                         regulator-min-microvolt = <750000>;
405                                         regulator-max-microvolt = <1100000>;
406                                         regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
407                                         regulator-coupled-max-spread = <550000 550000>;
408                                         regulator-always-on;
409
410                                         nvidia,tegra-cpu-regulator;
411                                 };
412
413                                 sm2_reg: sm2 {
414                                         regulator-name = "+3.7vs_sm2,vin_ldo*";
415                                         regulator-min-microvolt = <3700000>;
416                                         regulator-max-microvolt = <3700000>;
417                                         regulator-always-on;
418                                 };
419
420                                 /* LDO0 is not connected to anything */
421
422                                 ldo1 {
423                                         regulator-name = "+1.1vs_ldo1,avdd_pll*";
424                                         regulator-min-microvolt = <1100000>;
425                                         regulator-max-microvolt = <1100000>;
426                                         regulator-always-on;
427                                 };
428
429                                 rtc_vdd_reg: ldo2 {
430                                         regulator-name = "+1.2vs_ldo2,vdd_rtc";
431                                         regulator-min-microvolt = <950000>;
432                                         regulator-max-microvolt = <1300000>;
433                                         regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
434                                         regulator-coupled-max-spread = <170000 550000>;
435                                         regulator-always-on;
436
437                                         nvidia,tegra-rtc-regulator;
438                                 };
439
440                                 ldo3 {
441                                         regulator-name = "+3.3vs_ldo3,avdd_usb*";
442                                         regulator-min-microvolt = <3300000>;
443                                         regulator-max-microvolt = <3300000>;
444                                         regulator-always-on;
445                                 };
446
447                                 ldo4 {
448                                         regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
449                                         regulator-min-microvolt = <1800000>;
450                                         regulator-max-microvolt = <1800000>;
451                                         regulator-always-on;
452                                 };
453
454                                 ldo5 {
455                                         regulator-name = "+2.85vs_ldo5,vcore_mmc";
456                                         regulator-min-microvolt = <2850000>;
457                                         regulator-max-microvolt = <2850000>;
458                                         regulator-always-on;
459                                 };
460
461                                 ldo6 {
462                                         /*
463                                          * Research indicates this should be
464                                          * 1.8v; other boards that use this
465                                          * rail for the same purpose need it
466                                          * set to 1.8v. The schematic signal
467                                          * name is incorrect; perhaps copied
468                                          * from an incorrect NVIDIA reference.
469                                          */
470                                         regulator-name = "+2.85vs_ldo6,avdd_vdac";
471                                         regulator-min-microvolt = <1800000>;
472                                         regulator-max-microvolt = <1800000>;
473                                 };
474
475                                 hdmi_vdd_reg: ldo7 {
476                                         regulator-name = "+3.3vs_ldo7,avdd_hdmi";
477                                         regulator-min-microvolt = <3300000>;
478                                         regulator-max-microvolt = <3300000>;
479                                 };
480
481                                 hdmi_pll_reg: ldo8 {
482                                         regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
483                                         regulator-min-microvolt = <1800000>;
484                                         regulator-max-microvolt = <1800000>;
485                                 };
486
487                                 ldo9 {
488                                         regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
489                                         regulator-min-microvolt = <2850000>;
490                                         regulator-max-microvolt = <2850000>;
491                                         regulator-always-on;
492                                 };
493
494                                 ldo_rtc {
495                                         regulator-name = "+3.3vs_rtc";
496                                         regulator-min-microvolt = <3300000>;
497                                         regulator-max-microvolt = <3300000>;
498                                         regulator-always-on;
499                                 };
500                         };
501                 };
502
503                 adt7461: temperature-sensor@4c {
504                         compatible = "adi,adt7461";
505                         reg = <0x4c>;
506                         #thermal-sensor-cells = <1>;
507                 };
508         };
509
510         pmc@7000e400 {
511                 nvidia,invert-interrupt;
512                 nvidia,suspend-mode = <1>;
513                 nvidia,cpu-pwr-good-time = <2000>;
514                 nvidia,cpu-pwr-off-time = <0>;
515                 nvidia,core-pwr-good-time = <3845 3845>;
516                 nvidia,core-pwr-off-time = <0>;
517                 nvidia,sys-clock-req-active-high;
518         };
519
520         usb@c5000000 {
521                 compatible = "nvidia,tegra20-udc";
522                 status = "okay";
523                 dr_mode = "peripheral";
524         };
525
526         usb-phy@c5000000 {
527                 status = "okay";
528         };
529
530         usb@c5004000 {
531                 status = "okay";
532                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
533                         GPIO_ACTIVE_LOW>;
534         };
535
536         usb-phy@c5004000 {
537                 status = "okay";
538                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
539                         GPIO_ACTIVE_LOW>;
540         };
541
542         usb@c5008000 {
543                 status = "okay";
544         };
545
546         usb-phy@c5008000 {
547                 status = "okay";
548         };
549
550         mmc@c8000000 {
551                 status = "okay";
552                 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
553                 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
554                 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
555                 bus-width = <4>;
556         };
557
558         mmc@c8000600 {
559                 status = "okay";
560                 bus-width = <8>;
561                 non-removable;
562         };
563
564         backlight: backlight {
565                 compatible = "pwm-backlight";
566
567                 enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
568                 pwms = <&pwm 0 5000000>;
569
570                 brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
571                 default-brightness-level = <10>;
572
573                 backlight-boot-off;
574         };
575
576         clk32k_in: clock@0 {
577                 compatible = "fixed-clock";
578                 clock-frequency = <32768>;
579                 #clock-cells = <0>;
580         };
581
582         gpio-keys {
583                 compatible = "gpio-keys";
584
585                 wakeup {
586                         label = "Wakeup";
587                         gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
588                         linux,code = <KEY_WAKEUP>;
589                         wakeup-source;
590                 };
591         };
592
593         gpio-leds {
594                 compatible = "gpio-leds";
595
596                 led-0 {
597                         label = "wifi-led";
598                         gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
599                         linux,default-trigger = "rfkill0";
600                 };
601         };
602
603         panel: panel {
604                 compatible = "samsung,ltn101nt05";
605
606                 ddc-i2c-bus = <&lvds_ddc>;
607                 power-supply = <&vdd_pnl_reg>;
608                 enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
609
610                 backlight = <&backlight>;
611         };
612
613         p5valw_reg: regulator@0 {
614                 compatible = "regulator-fixed";
615                 regulator-name = "+5valw";
616                 regulator-min-microvolt = <5000000>;
617                 regulator-max-microvolt = <5000000>;
618                 regulator-always-on;
619         };
620
621         vdd_pnl_reg: regulator@1 {
622                 compatible = "regulator-fixed";
623                 regulator-name = "+3VS,vdd_pnl";
624                 regulator-min-microvolt = <3300000>;
625                 regulator-max-microvolt = <3300000>;
626                 regulator-boot-on;
627                 gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
628                 enable-active-high;
629         };
630
631         sound {
632                 compatible = "nvidia,tegra-audio-alc5632-paz00",
633                         "nvidia,tegra-audio-alc5632";
634
635                 nvidia,model = "Compal PAZ00";
636
637                 nvidia,audio-routing =
638                         "Int Spk", "SPKOUT",
639                         "Int Spk", "SPKOUTN",
640                         "Headset Mic", "MICBIAS1",
641                         "MIC1", "Headset Mic",
642                         "Headset Stereophone", "HPR",
643                         "Headset Stereophone", "HPL",
644                         "DMICDAT", "Digital Mic";
645
646                 nvidia,audio-codec = <&alc5632>;
647                 nvidia,i2s-controller = <&tegra_i2s1>;
648                 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
649                         GPIO_ACTIVE_HIGH>;
650
651                 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
652                          <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
653                          <&tegra_car TEGRA20_CLK_CDEV1>;
654                 clock-names = "pll_a", "pll_a_out0", "mclk";
655         };
656
657         cpus {
658                 cpu0: cpu@0 {
659                         cpu-supply = <&cpu_vdd_reg>;
660                         operating-points-v2 = <&cpu0_opp_table>;
661                         #cooling-cells = <2>;
662                 };
663
664                 cpu1: cpu@1 {
665                         cpu-supply = <&cpu_vdd_reg>;
666                         operating-points-v2 = <&cpu0_opp_table>;
667                         #cooling-cells = <2>;
668                 };
669         };
670
671         thermal-zones {
672                 cpu-thermal {
673                         polling-delay-passive = <500>; /* milliseconds */
674                         polling-delay = <1500>; /* milliseconds */
675
676                         thermal-sensors = <&adt7461 1>;
677
678                         trips {
679                                 trip0: cpu-alert0 {
680                                         /* start throttling at 80C */
681                                         temperature = <80000>;
682                                         hysteresis = <200>;
683                                         type = "passive";
684                                 };
685
686                                 trip1: cpu-crit {
687                                         /* shut down at 85C */
688                                         temperature = <85000>;
689                                         hysteresis = <2000>;
690                                         type = "critical";
691                                 };
692                         };
693
694                         cooling-maps {
695                                 map0 {
696                                         trip = <&trip0>;
697                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
698                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
699                                 };
700                         };
701                 };
702         };
703 };
704
705 &emc_icc_dvfs_opp_table {
706         /delete-node/ opp@760000000;
707 };