arch/arm/boot/dts/sunxi-h3-h5.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/sun8i-de2.h>
  44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
  45 #include <dt-bindings/clock/sun8i-r-ccu.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/reset/sun8i-de2.h>
  48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
  49 #include <dt-bindings/reset/sun8i-r-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         chosen {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 ranges;
  60
  61                 framebuffer-hdmi {
  62                         compatible = "allwinner,simple-framebuffer",
  63                                      "simple-framebuffer";
  64                         allwinner,pipeline = "mixer0-lcd0-hdmi";
  65                         clocks = <&display_clocks CLK_MIXER0>,
  66                                  <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
  67                         status = "disabled";
  68                 };
  69
  70                 framebuffer-tve {
  71                         compatible = "allwinner,simple-framebuffer",
  72                                      "simple-framebuffer";
  73                         allwinner,pipeline = "mixer1-lcd1-tve";
  74                         clocks = <&display_clocks CLK_MIXER1>,
  75                                  <&ccu CLK_TVE>;
  76                         status = "disabled";
  77                 };
  78         };
  79
  80         clocks {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges;
  84
  85                 osc24M: osc24M_clk {
  86                         #clock-cells = <0>;
  87                         compatible = "fixed-clock";
  88                         clock-frequency = <24000000>;
  89                         clock-accuracy = <50000>;
  90                         clock-output-names = "osc24M";
  91                 };
  92
  93                 osc32k: osc32k_clk {
  94                         #clock-cells = <0>;
  95                         compatible = "fixed-clock";
  96                         clock-frequency = <32768>;
  97                         clock-accuracy = <50000>;
  98                         clock-output-names = "ext_osc32k";
  99                 };
 100         };
 101
 102         de: display-engine {
 103                 compatible = "allwinner,sun8i-h3-display-engine";
 104                 allwinner,pipelines = <&mixer0>;
 105                 status = "disabled";
 106         };
 107
 108         soc {
 109                 compatible = "simple-bus";
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 dma-ranges;
 113                 ranges;
 114
 115                 display_clocks: clock@1000000 {
 116                         /* compatible is in per SoC .dtsi file */
 117                         reg = <0x01000000 0x10000>;
 118                         clocks = <&ccu CLK_BUS_DE>,
 119                                  <&ccu CLK_DE>;
 120                         clock-names = "bus",
 121                                       "mod";
 122                         resets = <&ccu RST_BUS_DE>;
 123                         #clock-cells = <1>;
 124                         #reset-cells = <1>;
 125                 };
 126
 127                 mixer0: mixer@1100000 {
 128                         compatible = "allwinner,sun8i-h3-de2-mixer-0";
 129                         reg = <0x01100000 0x100000>;
 130                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 131                                  <&display_clocks CLK_MIXER0>;
 132                         clock-names = "bus",
 133                                       "mod";
 134                         resets = <&display_clocks RST_MIXER0>;
 135
 136                         ports {
 137                                 #address-cells = <1>;
 138                                 #size-cells = <0>;
 139
 140                                 mixer0_out: port@1 {
 141                                         reg = <1>;
 142
 143                                         mixer0_out_tcon0: endpoint {
 144                                                 remote-endpoint = <&tcon0_in_mixer0>;
 145                                         };
 146                                 };
 147                         };
 148                 };
 149
 150                 dma: dma-controller@1c02000 {
 151                         compatible = "allwinner,sun8i-h3-dma";
 152                         reg = <0x01c02000 0x1000>;
 153                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 154                         clocks = <&ccu CLK_BUS_DMA>;
 155                         resets = <&ccu RST_BUS_DMA>;
 156                         #dma-cells = <1>;
 157                 };
 158
 159                 tcon0: lcd-controller@1c0c000 {
 160                         compatible = "allwinner,sun8i-h3-tcon-tv",
 161                                      "allwinner,sun8i-a83t-tcon-tv";
 162                         reg = <0x01c0c000 0x1000>;
 163                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 164                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 165                         clock-names = "ahb", "tcon-ch1";
 166                         resets = <&ccu RST_BUS_TCON0>;
 167                         reset-names = "lcd";
 168
 169                         ports {
 170                                 #address-cells = <1>;
 171                                 #size-cells = <0>;
 172
 173                                 tcon0_in: port@0 {
 174                                         reg = <0>;
 175
 176                                         tcon0_in_mixer0: endpoint {
 177                                                 remote-endpoint = <&mixer0_out_tcon0>;
 178                                         };
 179                                 };
 180
 181                                 tcon0_out: port@1 {
 182                                         #address-cells = <1>;
 183                                         #size-cells = <0>;
 184                                         reg = <1>;
 185
 186                                         tcon0_out_hdmi: endpoint@1 {
 187                                                 reg = <1>;
 188                                                 remote-endpoint = <&hdmi_in_tcon0>;
 189                                         };
 190                                 };
 191                         };
 192                 };
 193
 194                 mmc0: mmc@1c0f000 {
 195                         /* compatible and clocks are in per SoC .dtsi file */
 196                         reg = <0x01c0f000 0x1000>;
 197                         pinctrl-names = "default";
 198                         pinctrl-0 = <&mmc0_pins>;
 199                         resets = <&ccu RST_BUS_MMC0>;
 200                         reset-names = "ahb";
 201                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 202                         status = "disabled";
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                 };
 206
 207                 mmc1: mmc@1c10000 {
 208                         /* compatible and clocks are in per SoC .dtsi file */
 209                         reg = <0x01c10000 0x1000>;
 210                         pinctrl-names = "default";
 211                         pinctrl-0 = <&mmc1_pins>;
 212                         resets = <&ccu RST_BUS_MMC1>;
 213                         reset-names = "ahb";
 214                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 215                         status = "disabled";
 216                         #address-cells = <1>;
 217                         #size-cells = <0>;
 218                 };
 219
 220                 mmc2: mmc@1c11000 {
 221                         /* compatible and clocks are in per SoC .dtsi file */
 222                         reg = <0x01c11000 0x1000>;
 223                         resets = <&ccu RST_BUS_MMC2>;
 224                         reset-names = "ahb";
 225                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 226                         status = "disabled";
 227                         #address-cells = <1>;
 228                         #size-cells = <0>;
 229                 };
 230
 231                 sid: eeprom@1c14000 {
 232                         /* compatible is in per SoC .dtsi file */
 233                         reg = <0x1c14000 0x400>;
 234                         #address-cells = <1>;
 235                         #size-cells = <1>;
 236
 237                         ths_calibration: thermal-sensor-calibration@34 {
 238                                 reg = <0x34 4>;
 239                         };
 240                 };
 241
 242                 msgbox: mailbox@1c17000 {
 243                         compatible = "allwinner,sun8i-h3-msgbox",
 244                                      "allwinner,sun6i-a31-msgbox";
 245                         reg = <0x01c17000 0x1000>;
 246                         clocks = <&ccu CLK_BUS_MSGBOX>;
 247                         resets = <&ccu RST_BUS_MSGBOX>;
 248                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 249                         #mbox-cells = <1>;
 250                 };
 251
 252                 usb_otg: usb@1c19000 {
 253                         compatible = "allwinner,sun8i-h3-musb";
 254                         reg = <0x01c19000 0x400>;
 255                         clocks = <&ccu CLK_BUS_OTG>;
 256                         resets = <&ccu RST_BUS_OTG>;
 257                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 258                         interrupt-names = "mc";
 259                         phys = <&usbphy 0>;
 260                         phy-names = "usb";
 261                         extcon = <&usbphy 0>;
 262                         dr_mode = "otg";
 263                         status = "disabled";
 264                 };
 265
 266                 usbphy: phy@1c19400 {
 267                         compatible = "allwinner,sun8i-h3-usb-phy";
 268                         reg = <0x01c19400 0x2c>,
 269                               <0x01c1a800 0x4>,
 270                               <0x01c1b800 0x4>,
 271                               <0x01c1c800 0x4>,
 272                               <0x01c1d800 0x4>;
 273                         reg-names = "phy_ctrl",
 274                                     "pmu0",
 275                                     "pmu1",
 276                                     "pmu2",
 277                                     "pmu3";
 278                         clocks = <&ccu CLK_USB_PHY0>,
 279                                  <&ccu CLK_USB_PHY1>,
 280                                  <&ccu CLK_USB_PHY2>,
 281                                  <&ccu CLK_USB_PHY3>;
 282                         clock-names = "usb0_phy",
 283                                       "usb1_phy",
 284                                       "usb2_phy",
 285                                       "usb3_phy";
 286                         resets = <&ccu RST_USB_PHY0>,
 287                                  <&ccu RST_USB_PHY1>,
 288                                  <&ccu RST_USB_PHY2>,
 289                                  <&ccu RST_USB_PHY3>;
 290                         reset-names = "usb0_reset",
 291                                       "usb1_reset",
 292                                       "usb2_reset",
 293                                       "usb3_reset";
 294                         status = "disabled";
 295                         #phy-cells = <1>;
 296                 };
 297
 298                 ehci0: usb@1c1a000 {
 299                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 300                         reg = <0x01c1a000 0x100>;
 301                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 302                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
 303                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 304                         status = "disabled";
 305                 };
 306
 307                 ohci0: usb@1c1a400 {
 308                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 309                         reg = <0x01c1a400 0x100>;
 310                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 311                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
 312                                  <&ccu CLK_USB_OHCI0>;
 313                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 314                         status = "disabled";
 315                 };
 316
 317                 ehci1: usb@1c1b000 {
 318                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 319                         reg = <0x01c1b000 0x100>;
 320                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 321                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
 322                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 323                         phys = <&usbphy 1>;
 324                         phy-names = "usb";
 325                         status = "disabled";
 326                 };
 327
 328                 ohci1: usb@1c1b400 {
 329                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 330                         reg = <0x01c1b400 0x100>;
 331                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 332                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
 333                                  <&ccu CLK_USB_OHCI1>;
 334                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 335                         phys = <&usbphy 1>;
 336                         phy-names = "usb";
 337                         status = "disabled";
 338                 };
 339
 340                 ehci2: usb@1c1c000 {
 341                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 342                         reg = <0x01c1c000 0x100>;
 343                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 344                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
 345                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 346                         phys = <&usbphy 2>;
 347                         phy-names = "usb";
 348                         status = "disabled";
 349                 };
 350
 351                 ohci2: usb@1c1c400 {
 352                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 353                         reg = <0x01c1c400 0x100>;
 354                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
 356                                  <&ccu CLK_USB_OHCI2>;
 357                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 358                         phys = <&usbphy 2>;
 359                         phy-names = "usb";
 360                         status = "disabled";
 361                 };
 362
 363                 ehci3: usb@1c1d000 {
 364                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 365                         reg = <0x01c1d000 0x100>;
 366                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 367                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
 368                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 369                         phys = <&usbphy 3>;
 370                         phy-names = "usb";
 371                         status = "disabled";
 372                 };
 373
 374                 ohci3: usb@1c1d400 {
 375                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 376                         reg = <0x01c1d400 0x100>;
 377                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 378                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
 379                                  <&ccu CLK_USB_OHCI3>;
 380                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 381                         phys = <&usbphy 3>;
 382                         phy-names = "usb";
 383                         status = "disabled";
 384                 };
 385
 386                 ccu: clock@1c20000 {
 387                         /* compatible is in per SoC .dtsi file */
 388                         reg = <0x01c20000 0x400>;
 389                         clocks = <&osc24M>, <&rtc 0>;
 390                         clock-names = "hosc", "losc";
 391                         #clock-cells = <1>;
 392                         #reset-cells = <1>;
 393                 };
 394
 395                 pio: pinctrl@1c20800 {
 396                         /* compatible is in per SoC .dtsi file */
 397                         reg = <0x01c20800 0x400>;
 398                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 399                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 400                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 401                         clock-names = "apb", "hosc", "losc";
 402                         gpio-controller;
 403                         #gpio-cells = <3>;
 404                         interrupt-controller;
 405                         #interrupt-cells = <3>;
 406
 407                         csi_pins: csi-pins {
 408                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
 409                                        "PE6", "PE7", "PE8", "PE9", "PE10",
 410                                        "PE11";
 411                                 function = "csi";
 412                         };
 413
 414                         emac_rgmii_pins: emac-rgmii-pins {
 415                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 416                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 417                                        "PD12", "PD13", "PD15", "PD16", "PD17";
 418                                 function = "emac";
 419                                 drive-strength = <40>;
 420                         };
 421
 422                         i2c0_pins: i2c0-pins {
 423                                 pins = "PA11", "PA12";
 424                                 function = "i2c0";
 425                         };
 426
 427                         i2c1_pins: i2c1-pins {
 428                                 pins = "PA18", "PA19";
 429                                 function = "i2c1";
 430                         };
 431
 432                         i2c2_pins: i2c2-pins {
 433                                 pins = "PE12", "PE13";
 434                                 function = "i2c2";
 435                         };
 436
 437                         mmc0_pins: mmc0-pins {
 438                                 pins = "PF0", "PF1", "PF2", "PF3",
 439                                        "PF4", "PF5";
 440                                 function = "mmc0";
 441                                 drive-strength = <30>;
 442                                 bias-pull-up;
 443                         };
 444
 445                         mmc1_pins: mmc1-pins {
 446                                 pins = "PG0", "PG1", "PG2", "PG3",
 447                                        "PG4", "PG5";
 448                                 function = "mmc1";
 449                                 drive-strength = <30>;
 450                                 bias-pull-up;
 451                         };
 452
 453                         mmc2_8bit_pins: mmc2-8bit-pins {
 454                                 pins = "PC5", "PC6", "PC8",
 455                                        "PC9", "PC10", "PC11",
 456                                        "PC12", "PC13", "PC14",
 457                                        "PC15", "PC16";
 458                                 function = "mmc2";
 459                                 drive-strength = <30>;
 460                                 bias-pull-up;
 461                         };
 462
 463                         spdif_tx_pin: spdif-tx-pin {
 464                                 pins = "PA17";
 465                                 function = "spdif";
 466                         };
 467
 468                         spi0_pins: spi0-pins {
 469                                 pins = "PC0", "PC1", "PC2", "PC3";
 470                                 function = "spi0";
 471                         };
 472
 473                         spi1_pins: spi1-pins {
 474                                 pins = "PA15", "PA16", "PA14", "PA13";
 475                                 function = "spi1";
 476                         };
 477
 478                         uart0_pa_pins: uart0-pa-pins {
 479                                 pins = "PA4", "PA5";
 480                                 function = "uart0";
 481                         };
 482
 483                         uart1_pins: uart1-pins {
 484                                 pins = "PG6", "PG7";
 485                                 function = "uart1";
 486                         };
 487
 488                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 489                                 pins = "PG8", "PG9";
 490                                 function = "uart1";
 491                         };
 492
 493                         uart2_pins: uart2-pins {
 494                                 pins = "PA0", "PA1";
 495                                 function = "uart2";
 496                         };
 497
 498                         uart2_rts_cts_pins: uart2-rts-cts-pins {
 499                                 pins = "PA2", "PA3";
 500                                 function = "uart2";
 501                         };
 502
 503                         uart3_pins: uart3-pins {
 504                                 pins = "PA13", "PA14";
 505                                 function = "uart3";
 506                         };
 507
 508                         uart3_rts_cts_pins: uart3-rts-cts-pins {
 509                                 pins = "PA15", "PA16";
 510                                 function = "uart3";
 511                         };
 512                 };
 513
 514                 timer@1c20c00 {
 515                         compatible = "allwinner,sun8i-a23-timer";
 516                         reg = <0x01c20c00 0xa0>;
 517                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 518                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 519                         clocks = <&osc24M>;
 520                 };
 521
 522                 emac: ethernet@1c30000 {
 523                         compatible = "allwinner,sun8i-h3-emac";
 524                         syscon = <&syscon>;
 525                         reg = <0x01c30000 0x10000>;
 526                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 527                         interrupt-names = "macirq";
 528                         resets = <&ccu RST_BUS_EMAC>;
 529                         reset-names = "stmmaceth";
 530                         clocks = <&ccu CLK_BUS_EMAC>;
 531                         clock-names = "stmmaceth";
 532                         status = "disabled";
 533
 534                         mdio: mdio {
 535                                 #address-cells = <1>;
 536                                 #size-cells = <0>;
 537                                 compatible = "snps,dwmac-mdio";
 538                         };
 539
 540                         mdio-mux {
 541                                 compatible = "allwinner,sun8i-h3-mdio-mux";
 542                                 #address-cells = <1>;
 543                                 #size-cells = <0>;
 544
 545                                 mdio-parent-bus = <&mdio>;
 546                                 /* Only one MDIO is usable at the time */
 547                                 internal_mdio: mdio@1 {
 548                                         compatible = "allwinner,sun8i-h3-mdio-internal";
 549                                         reg = <1>;
 550                                         #address-cells = <1>;
 551                                         #size-cells = <0>;
 552
 553                                         int_mii_phy: ethernet-phy@1 {
 554                                                 compatible = "ethernet-phy-ieee802.3-c22";
 555                                                 reg = <1>;
 556                                                 clocks = <&ccu CLK_BUS_EPHY>;
 557                                                 resets = <&ccu RST_BUS_EPHY>;
 558                                         };
 559                                 };
 560
 561                                 external_mdio: mdio@2 {
 562                                         reg = <2>;
 563                                         #address-cells = <1>;
 564                                         #size-cells = <0>;
 565                                 };
 566                         };
 567                 };
 568
 569                 mbus: dram-controller@1c62000 {
 570                         compatible = "allwinner,sun8i-h3-mbus";
 571                         reg = <0x01c62000 0x1000>;
 572                         clocks = <&ccu CLK_MBUS>;
 573                         #address-cells = <1>;
 574                         #size-cells = <1>;
 575                         dma-ranges = <0x00000000 0x40000000 0xc0000000>;
 576                         #interconnect-cells = <1>;
 577                 };
 578
 579                 spi0: spi@1c68000 {
 580                         compatible = "allwinner,sun8i-h3-spi";
 581                         reg = <0x01c68000 0x1000>;
 582                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 583                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 584                         clock-names = "ahb", "mod";
 585                         dmas = <&dma 23>, <&dma 23>;
 586                         dma-names = "rx", "tx";
 587                         pinctrl-names = "default";
 588                         pinctrl-0 = <&spi0_pins>;
 589                         resets = <&ccu RST_BUS_SPI0>;
 590                         status = "disabled";
 591                         #address-cells = <1>;
 592                         #size-cells = <0>;
 593                 };
 594
 595                 spi1: spi@1c69000 {
 596                         compatible = "allwinner,sun8i-h3-spi";
 597                         reg = <0x01c69000 0x1000>;
 598                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 599                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 600                         clock-names = "ahb", "mod";
 601                         dmas = <&dma 24>, <&dma 24>;
 602                         dma-names = "rx", "tx";
 603                         pinctrl-names = "default";
 604                         pinctrl-0 = <&spi1_pins>;
 605                         resets = <&ccu RST_BUS_SPI1>;
 606                         status = "disabled";
 607                         #address-cells = <1>;
 608                         #size-cells = <0>;
 609                 };
 610
 611                 wdt0: watchdog@1c20ca0 {
 612                         compatible = "allwinner,sun6i-a31-wdt";
 613                         reg = <0x01c20ca0 0x20>;
 614                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 615                         clocks = <&osc24M>;
 616                 };
 617
 618                 spdif: spdif@1c21000 {
 619                         #sound-dai-cells = <0>;
 620                         compatible = "allwinner,sun8i-h3-spdif";
 621                         reg = <0x01c21000 0x400>;
 622                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 623                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 624                         resets = <&ccu RST_BUS_SPDIF>;
 625                         clock-names = "apb", "spdif";
 626                         dmas = <&dma 2>;
 627                         dma-names = "tx";
 628                         status = "disabled";
 629                 };
 630
 631                 pwm: pwm@1c21400 {
 632                         compatible = "allwinner,sun8i-h3-pwm";
 633                         reg = <0x01c21400 0x8>;
 634                         clocks = <&osc24M>;
 635                         #pwm-cells = <3>;
 636                         status = "disabled";
 637                 };
 638
 639                 i2s0: i2s@1c22000 {
 640                         #sound-dai-cells = <0>;
 641                         compatible = "allwinner,sun8i-h3-i2s";
 642                         reg = <0x01c22000 0x400>;
 643                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 644                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 645                         clock-names = "apb", "mod";
 646                         dmas = <&dma 3>, <&dma 3>;
 647                         resets = <&ccu RST_BUS_I2S0>;
 648                         dma-names = "rx", "tx";
 649                         status = "disabled";
 650                 };
 651
 652                 i2s1: i2s@1c22400 {
 653                         #sound-dai-cells = <0>;
 654                         compatible = "allwinner,sun8i-h3-i2s";
 655                         reg = <0x01c22400 0x400>;
 656                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 657                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 658                         clock-names = "apb", "mod";
 659                         dmas = <&dma 4>, <&dma 4>;
 660                         resets = <&ccu RST_BUS_I2S1>;
 661                         dma-names = "rx", "tx";
 662                         status = "disabled";
 663                 };
 664
 665                 i2s2: i2s@1c22800 {
 666                         #sound-dai-cells = <0>;
 667                         compatible = "allwinner,sun8i-h3-i2s";
 668                         reg = <0x01c22800 0x400>;
 669                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 670                         clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
 671                         clock-names = "apb", "mod";
 672                         dmas = <&dma 27>;
 673                         resets = <&ccu RST_BUS_I2S2>;
 674                         dma-names = "tx";
 675                         status = "disabled";
 676                 };
 677
 678                 codec: codec@1c22c00 {
 679                         #sound-dai-cells = <0>;
 680                         compatible = "allwinner,sun8i-h3-codec";
 681                         reg = <0x01c22c00 0x400>;
 682                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 683                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 684                         clock-names = "apb", "codec";
 685                         resets = <&ccu RST_BUS_CODEC>;
 686                         dmas = <&dma 15>, <&dma 15>;
 687                         dma-names = "rx", "tx";
 688                         allwinner,codec-analog-controls = <&codec_analog>;
 689                         status = "disabled";
 690                 };
 691
 692                 uart0: serial@1c28000 {
 693                         compatible = "snps,dw-apb-uart";
 694                         reg = <0x01c28000 0x400>;
 695                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 696                         reg-shift = <2>;
 697                         reg-io-width = <4>;
 698                         clocks = <&ccu CLK_BUS_UART0>;
 699                         resets = <&ccu RST_BUS_UART0>;
 700                         dmas = <&dma 6>, <&dma 6>;
 701                         dma-names = "rx", "tx";
 702                         status = "disabled";
 703                 };
 704
 705                 uart1: serial@1c28400 {
 706                         compatible = "snps,dw-apb-uart";
 707                         reg = <0x01c28400 0x400>;
 708                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 709                         reg-shift = <2>;
 710                         reg-io-width = <4>;
 711                         clocks = <&ccu CLK_BUS_UART1>;
 712                         resets = <&ccu RST_BUS_UART1>;
 713                         dmas = <&dma 7>, <&dma 7>;
 714                         dma-names = "rx", "tx";
 715                         status = "disabled";
 716                 };
 717
 718                 uart2: serial@1c28800 {
 719                         compatible = "snps,dw-apb-uart";
 720                         reg = <0x01c28800 0x400>;
 721                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 722                         reg-shift = <2>;
 723                         reg-io-width = <4>;
 724                         clocks = <&ccu CLK_BUS_UART2>;
 725                         resets = <&ccu RST_BUS_UART2>;
 726                         dmas = <&dma 8>, <&dma 8>;
 727                         dma-names = "rx", "tx";
 728                         status = "disabled";
 729                 };
 730
 731                 uart3: serial@1c28c00 {
 732                         compatible = "snps,dw-apb-uart";
 733                         reg = <0x01c28c00 0x400>;
 734                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 735                         reg-shift = <2>;
 736                         reg-io-width = <4>;
 737                         clocks = <&ccu CLK_BUS_UART3>;
 738                         resets = <&ccu RST_BUS_UART3>;
 739                         dmas = <&dma 9>, <&dma 9>;
 740                         dma-names = "rx", "tx";
 741                         status = "disabled";
 742                 };
 743
 744                 i2c0: i2c@1c2ac00 {
 745                         compatible = "allwinner,sun6i-a31-i2c";
 746                         reg = <0x01c2ac00 0x400>;
 747                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 748                         clocks = <&ccu CLK_BUS_I2C0>;
 749                         resets = <&ccu RST_BUS_I2C0>;
 750                         pinctrl-names = "default";
 751                         pinctrl-0 = <&i2c0_pins>;
 752                         status = "disabled";
 753                         #address-cells = <1>;
 754                         #size-cells = <0>;
 755                 };
 756
 757                 i2c1: i2c@1c2b000 {
 758                         compatible = "allwinner,sun6i-a31-i2c";
 759                         reg = <0x01c2b000 0x400>;
 760                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 761                         clocks = <&ccu CLK_BUS_I2C1>;
 762                         resets = <&ccu RST_BUS_I2C1>;
 763                         pinctrl-names = "default";
 764                         pinctrl-0 = <&i2c1_pins>;
 765                         status = "disabled";
 766                         #address-cells = <1>;
 767                         #size-cells = <0>;
 768                 };
 769
 770                 i2c2: i2c@1c2b400 {
 771                         compatible = "allwinner,sun6i-a31-i2c";
 772                         reg = <0x01c2b400 0x400>;
 773                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 774                         clocks = <&ccu CLK_BUS_I2C2>;
 775                         resets = <&ccu RST_BUS_I2C2>;
 776                         pinctrl-names = "default";
 777                         pinctrl-0 = <&i2c2_pins>;
 778                         status = "disabled";
 779                         #address-cells = <1>;
 780                         #size-cells = <0>;
 781                 };
 782
 783                 gic: interrupt-controller@1c81000 {
 784                         compatible = "arm,gic-400";
 785                         reg = <0x01c81000 0x1000>,
 786                               <0x01c82000 0x2000>,
 787                               <0x01c84000 0x2000>,
 788                               <0x01c86000 0x2000>;
 789                         interrupt-controller;
 790                         #interrupt-cells = <3>;
 791                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 792                 };
 793
 794                 csi: camera@1cb0000 {
 795                         compatible = "allwinner,sun8i-h3-csi";
 796                         reg = <0x01cb0000 0x1000>;
 797                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 798                         clocks = <&ccu CLK_BUS_CSI>,
 799                                  <&ccu CLK_CSI_SCLK>,
 800                                  <&ccu CLK_DRAM_CSI>;
 801                         clock-names = "bus", "mod", "ram";
 802                         resets = <&ccu RST_BUS_CSI>;
 803                         pinctrl-names = "default";
 804                         pinctrl-0 = <&csi_pins>;
 805                         status = "disabled";
 806                 };
 807
 808                 hdmi: hdmi@1ee0000 {
 809                         compatible = "allwinner,sun8i-h3-dw-hdmi",
 810                                      "allwinner,sun8i-a83t-dw-hdmi";
 811                         reg = <0x01ee0000 0x10000>;
 812                         reg-io-width = <1>;
 813                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 814                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
 815                                  <&ccu CLK_HDMI>;
 816                         clock-names = "iahb", "isfr", "tmds";
 817                         resets = <&ccu RST_BUS_HDMI1>;
 818                         reset-names = "ctrl";
 819                         phys = <&hdmi_phy>;
 820                         phy-names = "phy";
 821                         status = "disabled";
 822
 823                         ports {
 824                                 #address-cells = <1>;
 825                                 #size-cells = <0>;
 826
 827                                 hdmi_in: port@0 {
 828                                         reg = <0>;
 829
 830                                         hdmi_in_tcon0: endpoint {
 831                                                 remote-endpoint = <&tcon0_out_hdmi>;
 832                                         };
 833                                 };
 834
 835                                 hdmi_out: port@1 {
 836                                         reg = <1>;
 837                                 };
 838                         };
 839                 };
 840
 841                 hdmi_phy: hdmi-phy@1ef0000 {
 842                         compatible = "allwinner,sun8i-h3-hdmi-phy";
 843                         reg = <0x01ef0000 0x10000>;
 844                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
 845                                  <&ccu CLK_PLL_VIDEO>;
 846                         clock-names = "bus", "mod", "pll-0";
 847                         resets = <&ccu RST_BUS_HDMI0>;
 848                         reset-names = "phy";
 849                         #phy-cells = <0>;
 850                 };
 851
 852                 rtc: rtc@1f00000 {
 853                         /* compatible is in per SoC .dtsi file */
 854                         reg = <0x01f00000 0x400>;
 855                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 856                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 857                         clock-output-names = "osc32k", "osc32k-out", "iosc";
 858                         clocks = <&osc32k>;
 859                         #clock-cells = <1>;
 860                 };
 861
 862                 r_ccu: clock@1f01400 {
 863                         compatible = "allwinner,sun8i-h3-r-ccu";
 864                         reg = <0x01f01400 0x100>;
 865                         clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
 866                                  <&ccu CLK_PLL_PERIPH0>;
 867                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 868                         #clock-cells = <1>;
 869                         #reset-cells = <1>;
 870                 };
 871
 872                 codec_analog: codec-analog@1f015c0 {
 873                         compatible = "allwinner,sun8i-h3-codec-analog";
 874                         reg = <0x01f015c0 0x4>;
 875                 };
 876
 877                 ir: ir@1f02000 {
 878                         compatible = "allwinner,sun6i-a31-ir";
 879                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
 880                         clock-names = "apb", "ir";
 881                         resets = <&r_ccu RST_APB0_IR>;
 882                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 883                         reg = <0x01f02000 0x400>;
 884                         status = "disabled";
 885                 };
 886
 887                 r_i2c: i2c@1f02400 {
 888                         compatible = "allwinner,sun6i-a31-i2c";
 889                         reg = <0x01f02400 0x400>;
 890                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 891                         pinctrl-names = "default";
 892                         pinctrl-0 = <&r_i2c_pins>;
 893                         clocks = <&r_ccu CLK_APB0_I2C>;
 894                         resets = <&r_ccu RST_APB0_I2C>;
 895                         status = "disabled";
 896                         #address-cells = <1>;
 897                         #size-cells = <0>;
 898                 };
 899
 900                 r_pio: pinctrl@1f02c00 {
 901                         compatible = "allwinner,sun8i-h3-r-pinctrl";
 902                         reg = <0x01f02c00 0x400>;
 903                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 904                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
 905                         clock-names = "apb", "hosc", "losc";
 906                         gpio-controller;
 907                         #gpio-cells = <3>;
 908                         interrupt-controller;
 909                         #interrupt-cells = <3>;
 910
 911                         r_ir_rx_pin: r-ir-rx-pin {
 912                                 pins = "PL11";
 913                                 function = "s_cir_rx";
 914                         };
 915
 916                         r_i2c_pins: r-i2c-pins {
 917                                 pins = "PL0", "PL1";
 918                                 function = "s_i2c";
 919                         };
 920
 921                         r_pwm_pin: r-pwm-pin {
 922                                 pins = "PL10";
 923                                 function = "s_pwm";
 924                         };
 925                 };
 926
 927                 r_pwm: pwm@1f03800 {
 928                         compatible = "allwinner,sun8i-h3-pwm";
 929                         reg = <0x01f03800 0x8>;
 930                         pinctrl-names = "default";
 931                         pinctrl-0 = <&r_pwm_pin>;
 932                         clocks = <&osc24M>;
 933                         #pwm-cells = <3>;
 934                         status = "disabled";
 935                 };
 936         };
 937 };