arch/arm/boot/dts/sun8i-v3s.dtsi

   1 /*
   2  * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
  45 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
  46 #include <dt-bindings/clock/sun8i-de2.h>
  47
  48 / {
  49         #address-cells = <1>;
  50         #size-cells = <1>;
  51         interrupt-parent = <&gic>;
  52
  53         chosen {
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 ranges;
  57
  58                 framebuffer-lcd {
  59                         compatible = "allwinner,simple-framebuffer",
  60                                      "simple-framebuffer";
  61                         allwinner,pipeline = "mixer0-lcd0";
  62                         clocks = <&display_clocks CLK_MIXER0>,
  63                                  <&ccu CLK_TCON0>;
  64                         status = "disabled";
  65                 };
  66         };
  67
  68         cpus {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71
  72                 cpu@0 {
  73                         compatible = "arm,cortex-a7";
  74                         device_type = "cpu";
  75                         reg = <0>;
  76                         clocks = <&ccu CLK_CPU>;
  77                 };
  78         };
  79
  80         de: display-engine {
  81                 compatible = "allwinner,sun8i-v3s-display-engine";
  82                 allwinner,pipelines = <&mixer0>;
  83                 status = "disabled";
  84         };
  85
  86         timer {
  87                 compatible = "arm,armv7-timer";
  88                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  89                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  92         };
  93
  94         clocks {
  95                 #address-cells = <1>;
  96                 #size-cells = <1>;
  97                 ranges;
  98
  99                 osc24M: osc24M_clk {
 100                         #clock-cells = <0>;
 101                         compatible = "fixed-clock";
 102                         clock-frequency = <24000000>;
 103                         clock-accuracy = <50000>;
 104                         clock-output-names = "osc24M";
 105                 };
 106
 107                 osc32k: osc32k_clk {
 108                         #clock-cells = <0>;
 109                         compatible = "fixed-clock";
 110                         clock-frequency = <32768>;
 111                         clock-accuracy = <50000>;
 112                         clock-output-names = "ext-osc32k";
 113                 };
 114         };
 115
 116         soc {
 117                 compatible = "simple-bus";
 118                 #address-cells = <1>;
 119                 #size-cells = <1>;
 120                 ranges;
 121
 122                 display_clocks: clock@1000000 {
 123                         compatible = "allwinner,sun8i-v3s-de2-clk";
 124                         reg = <0x01000000 0x10000>;
 125                         clocks = <&ccu CLK_BUS_DE>,
 126                                  <&ccu CLK_DE>;
 127                         clock-names = "bus",
 128                                       "mod";
 129                         resets = <&ccu RST_BUS_DE>;
 130                         #clock-cells = <1>;
 131                         #reset-cells = <1>;
 132                 };
 133
 134                 mixer0: mixer@1100000 {
 135                         compatible = "allwinner,sun8i-v3s-de2-mixer";
 136                         reg = <0x01100000 0x100000>;
 137                         clocks = <&display_clocks 0>,
 138                                  <&display_clocks 6>;
 139                         clock-names = "bus",
 140                                       "mod";
 141                         resets = <&display_clocks 0>;
 142
 143                         ports {
 144                                 #address-cells = <1>;
 145                                 #size-cells = <0>;
 146
 147                                 mixer0_out: port@1 {
 148                                         reg = <1>;
 149
 150                                         mixer0_out_tcon0: endpoint {
 151                                                 remote-endpoint = <&tcon0_in_mixer0>;
 152                                         };
 153                                 };
 154                         };
 155                 };
 156
 157                 syscon: system-control@1c00000 {
 158                         compatible = "allwinner,sun8i-v3s-system-control",
 159                                      "allwinner,sun8i-h3-system-control";
 160                         reg = <0x01c00000 0x1000>;
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                         ranges;
 164                 };
 165
 166                 tcon0: lcd-controller@1c0c000 {
 167                         compatible = "allwinner,sun8i-v3s-tcon";
 168                         reg = <0x01c0c000 0x1000>;
 169                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 170                         clocks = <&ccu CLK_BUS_TCON0>,
 171                                  <&ccu CLK_TCON0>;
 172                         clock-names = "ahb",
 173                                       "tcon-ch0";
 174                         clock-output-names = "tcon-pixel-clock";
 175                         #clock-cells = <0>;
 176                         resets = <&ccu RST_BUS_TCON0>;
 177                         reset-names = "lcd";
 178                         status = "disabled";
 179
 180                         ports {
 181                                 #address-cells = <1>;
 182                                 #size-cells = <0>;
 183
 184                                 tcon0_in: port@0 {
 185                                         reg = <0>;
 186
 187                                         tcon0_in_mixer0: endpoint {
 188                                                 remote-endpoint = <&mixer0_out_tcon0>;
 189                                         };
 190                                 };
 191
 192                                 tcon0_out: port@1 {
 193                                         #address-cells = <1>;
 194                                         #size-cells = <0>;
 195                                         reg = <1>;
 196                                 };
 197                         };
 198                 };
 199
 200
 201                 mmc0: mmc@1c0f000 {
 202                         compatible = "allwinner,sun7i-a20-mmc";
 203                         reg = <0x01c0f000 0x1000>;
 204                         clocks = <&ccu CLK_BUS_MMC0>,
 205                                  <&ccu CLK_MMC0>,
 206                                  <&ccu CLK_MMC0_OUTPUT>,
 207                                  <&ccu CLK_MMC0_SAMPLE>;
 208                         clock-names = "ahb",
 209                                       "mmc",
 210                                       "output",
 211                                       "sample";
 212                         resets = <&ccu RST_BUS_MMC0>;
 213                         reset-names = "ahb";
 214                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 215                         pinctrl-names = "default";
 216                         pinctrl-0 = <&mmc0_pins>;
 217                         status = "disabled";
 218                         #address-cells = <1>;
 219                         #size-cells = <0>;
 220                 };
 221
 222                 mmc1: mmc@1c10000 {
 223                         compatible = "allwinner,sun7i-a20-mmc";
 224                         reg = <0x01c10000 0x1000>;
 225                         clocks = <&ccu CLK_BUS_MMC1>,
 226                                  <&ccu CLK_MMC1>,
 227                                  <&ccu CLK_MMC1_OUTPUT>,
 228                                  <&ccu CLK_MMC1_SAMPLE>;
 229                         clock-names = "ahb",
 230                                       "mmc",
 231                                       "output",
 232                                       "sample";
 233                         resets = <&ccu RST_BUS_MMC1>;
 234                         reset-names = "ahb";
 235                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 236                         pinctrl-names = "default";
 237                         pinctrl-0 = <&mmc1_pins>;
 238                         status = "disabled";
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                 };
 242
 243                 mmc2: mmc@1c11000 {
 244                         compatible = "allwinner,sun7i-a20-mmc";
 245                         reg = <0x01c11000 0x1000>;
 246                         clocks = <&ccu CLK_BUS_MMC2>,
 247                                  <&ccu CLK_MMC2>,
 248                                  <&ccu CLK_MMC2_OUTPUT>,
 249                                  <&ccu CLK_MMC2_SAMPLE>;
 250                         clock-names = "ahb",
 251                                       "mmc",
 252                                       "output",
 253                                       "sample";
 254                         resets = <&ccu RST_BUS_MMC2>;
 255                         reset-names = "ahb";
 256                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 257                         status = "disabled";
 258                         #address-cells = <1>;
 259                         #size-cells = <0>;
 260                 };
 261
 262                 crypto@1c15000 {
 263                         compatible = "allwinner,sun8i-v3s-crypto",
 264                                      "allwinner,sun8i-a33-crypto";
 265                         reg = <0x01c15000 0x1000>;
 266                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 267                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
 268                         clock-names = "ahb", "mod";
 269                         resets = <&ccu RST_BUS_CE>;
 270                         reset-names = "ahb";
 271                 };
 272
 273                 usb_otg: usb@1c19000 {
 274                         compatible = "allwinner,sun8i-h3-musb";
 275                         reg = <0x01c19000 0x0400>;
 276                         clocks = <&ccu CLK_BUS_OTG>;
 277                         resets = <&ccu RST_BUS_OTG>;
 278                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 279                         interrupt-names = "mc";
 280                         phys = <&usbphy 0>;
 281                         phy-names = "usb";
 282                         extcon = <&usbphy 0>;
 283                         status = "disabled";
 284                 };
 285
 286                 usbphy: phy@1c19400 {
 287                         compatible = "allwinner,sun8i-v3s-usb-phy";
 288                         reg = <0x01c19400 0x2c>,
 289                               <0x01c1a800 0x4>;
 290                         reg-names = "phy_ctrl",
 291                                     "pmu0";
 292                         clocks = <&ccu CLK_USB_PHY0>;
 293                         clock-names = "usb0_phy";
 294                         resets = <&ccu RST_USB_PHY0>;
 295                         reset-names = "usb0_reset";
 296                         status = "disabled";
 297                         #phy-cells = <1>;
 298                 };
 299
 300                 ccu: clock@1c20000 {
 301                         compatible = "allwinner,sun8i-v3s-ccu";
 302                         reg = <0x01c20000 0x400>;
 303                         clocks = <&osc24M>, <&rtc 0>;
 304                         clock-names = "hosc", "losc";
 305                         #clock-cells = <1>;
 306                         #reset-cells = <1>;
 307                 };
 308
 309                 rtc: rtc@1c20400 {
 310                         #clock-cells = <1>;
 311                         compatible = "allwinner,sun8i-v3-rtc";
 312                         reg = <0x01c20400 0x54>;
 313                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 314                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 315                         clocks = <&osc32k>;
 316                         clock-output-names = "osc32k", "osc32k-out";
 317                 };
 318
 319                 pio: pinctrl@1c20800 {
 320                         compatible = "allwinner,sun8i-v3s-pinctrl";
 321                         reg = <0x01c20800 0x400>;
 322                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 323                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 325                         clock-names = "apb", "hosc", "losc";
 326                         gpio-controller;
 327                         #gpio-cells = <3>;
 328                         interrupt-controller;
 329                         #interrupt-cells = <3>;
 330
 331                         /omit-if-no-ref/
 332                         csi1_8bit_pins: csi1-8bit-pins {
 333                                 pins = "PE0", "PE2", "PE3", "PE8", "PE9",
 334                                        "PE10", "PE11", "PE12", "PE13", "PE14",
 335                                        "PE15";
 336                                 function = "csi";
 337                         };
 338
 339                         /omit-if-no-ref/
 340                         csi1_mclk_pin: csi1-mclk-pin {
 341                                 pins = "PE1";
 342                                 function = "csi";
 343                         };
 344
 345                         i2c0_pins: i2c0-pins {
 346                                 pins = "PB6", "PB7";
 347                                 function = "i2c0";
 348                         };
 349
 350                         /omit-if-no-ref/
 351                         i2c1_pb_pins: i2c1-pb-pins {
 352                                 pins = "PB8", "PB9";
 353                                 function = "i2c1";
 354                         };
 355
 356                         /omit-if-no-ref/
 357                         i2c1_pe_pins: i2c1-pe-pins {
 358                                 pins = "PE21", "PE22";
 359                                 function = "i2c1";
 360                         };
 361
 362                         uart0_pb_pins: uart0-pb-pins {
 363                                 pins = "PB8", "PB9";
 364                                 function = "uart0";
 365                         };
 366
 367                         uart2_pins: uart2-pins {
 368                                 pins = "PB0", "PB1";
 369                                 function = "uart2";
 370                         };
 371
 372                         mmc0_pins: mmc0-pins {
 373                                 pins = "PF0", "PF1", "PF2", "PF3",
 374                                        "PF4", "PF5";
 375                                 function = "mmc0";
 376                                 drive-strength = <30>;
 377                                 bias-pull-up;
 378                         };
 379
 380                         mmc1_pins: mmc1-pins {
 381                                 pins = "PG0", "PG1", "PG2", "PG3",
 382                                        "PG4", "PG5";
 383                                 function = "mmc1";
 384                                 drive-strength = <30>;
 385                                 bias-pull-up;
 386                         };
 387
 388                         spi0_pins: spi0-pins {
 389                                 pins = "PC0", "PC1", "PC2", "PC3";
 390                                 function = "spi0";
 391                         };
 392                 };
 393
 394                 timer@1c20c00 {
 395                         compatible = "allwinner,sun8i-v3s-timer";
 396                         reg = <0x01c20c00 0xa0>;
 397                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 398                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 399                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 400                         clocks = <&osc24M>;
 401                 };
 402
 403                 wdt0: watchdog@1c20ca0 {
 404                         compatible = "allwinner,sun6i-a31-wdt";
 405                         reg = <0x01c20ca0 0x20>;
 406                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&osc24M>;
 408                 };
 409
 410                 lradc: lradc@1c22800 {
 411                         compatible = "allwinner,sun4i-a10-lradc-keys";
 412                         reg = <0x01c22800 0x400>;
 413                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 414                         status = "disabled";
 415                 };
 416
 417                 uart0: serial@1c28000 {
 418                         compatible = "snps,dw-apb-uart";
 419                         reg = <0x01c28000 0x400>;
 420                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 421                         reg-shift = <2>;
 422                         reg-io-width = <4>;
 423                         clocks = <&ccu CLK_BUS_UART0>;
 424                         resets = <&ccu RST_BUS_UART0>;
 425                         status = "disabled";
 426                 };
 427
 428                 uart1: serial@1c28400 {
 429                         compatible = "snps,dw-apb-uart";
 430                         reg = <0x01c28400 0x400>;
 431                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 432                         reg-shift = <2>;
 433                         reg-io-width = <4>;
 434                         clocks = <&ccu CLK_BUS_UART1>;
 435                         resets = <&ccu RST_BUS_UART1>;
 436                         status = "disabled";
 437                 };
 438
 439                 uart2: serial@1c28800 {
 440                         compatible = "snps,dw-apb-uart";
 441                         reg = <0x01c28800 0x400>;
 442                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 443                         reg-shift = <2>;
 444                         reg-io-width = <4>;
 445                         clocks = <&ccu CLK_BUS_UART2>;
 446                         resets = <&ccu RST_BUS_UART2>;
 447                         pinctrl-0 = <&uart2_pins>;
 448                         pinctrl-names = "default";
 449                         status = "disabled";
 450                 };
 451
 452                 i2c0: i2c@1c2ac00 {
 453                         compatible = "allwinner,sun6i-a31-i2c";
 454                         reg = <0x01c2ac00 0x400>;
 455                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&ccu CLK_BUS_I2C0>;
 457                         resets = <&ccu RST_BUS_I2C0>;
 458                         pinctrl-names = "default";
 459                         pinctrl-0 = <&i2c0_pins>;
 460                         status = "disabled";
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                 };
 464
 465                 i2c1: i2c@1c2b000 {
 466                         compatible = "allwinner,sun6i-a31-i2c";
 467                         reg = <0x01c2b000 0x400>;
 468                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 469                         clocks = <&ccu CLK_BUS_I2C1>;
 470                         resets = <&ccu RST_BUS_I2C1>;
 471                         status = "disabled";
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                 };
 475
 476                 emac: ethernet@1c30000 {
 477                         compatible = "allwinner,sun8i-v3s-emac";
 478                         syscon = <&syscon>;
 479                         reg = <0x01c30000 0x10000>;
 480                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 481                         interrupt-names = "macirq";
 482                         resets = <&ccu RST_BUS_EMAC>;
 483                         reset-names = "stmmaceth";
 484                         clocks = <&ccu CLK_BUS_EMAC>;
 485                         clock-names = "stmmaceth";
 486                         phy-handle = <&int_mii_phy>;
 487                         phy-mode = "mii";
 488                         status = "disabled";
 489
 490                         mdio: mdio {
 491                                 #address-cells = <1>;
 492                                 #size-cells = <0>;
 493                                 compatible = "snps,dwmac-mdio";
 494                         };
 495
 496                         mdio_mux: mdio-mux {
 497                                 compatible = "allwinner,sun8i-h3-mdio-mux";
 498                                 #address-cells = <1>;
 499                                 #size-cells = <0>;
 500
 501                                 mdio-parent-bus = <&mdio>;
 502                                 /* Only one MDIO is usable at the time */
 503                                 internal_mdio: mdio@1 {
 504                                         compatible = "allwinner,sun8i-h3-mdio-internal";
 505                                         reg = <1>;
 506                                         #address-cells = <1>;
 507                                         #size-cells = <0>;
 508
 509                                         int_mii_phy: ethernet-phy@1 {
 510                                                 compatible = "ethernet-phy-ieee802.3-c22";
 511                                                 reg = <1>;
 512                                                 clocks = <&ccu CLK_BUS_EPHY>;
 513                                                 resets = <&ccu RST_BUS_EPHY>;
 514                                         };
 515                                 };
 516                         };
 517                 };
 518
 519                 spi0: spi@1c68000 {
 520                         compatible = "allwinner,sun8i-h3-spi";
 521                         reg = <0x01c68000 0x1000>;
 522                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 523                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 524                         clock-names = "ahb", "mod";
 525                         pinctrl-names = "default";
 526                         pinctrl-0 = <&spi0_pins>;
 527                         resets = <&ccu RST_BUS_SPI0>;
 528                         status = "disabled";
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                 };
 532
 533                 csi1: camera@1cb4000 {
 534                         compatible = "allwinner,sun8i-v3s-csi";
 535                         reg = <0x01cb4000 0x3000>;
 536                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 537                         clocks = <&ccu CLK_BUS_CSI>,
 538                                  <&ccu CLK_CSI1_SCLK>,
 539                                  <&ccu CLK_DRAM_CSI>;
 540                         clock-names = "bus", "mod", "ram";
 541                         resets = <&ccu RST_BUS_CSI>;
 542                         status = "disabled";
 543                 };
 544
 545                 gic: interrupt-controller@1c81000 {
 546                         compatible = "arm,gic-400";
 547                         reg = <0x01c81000 0x1000>,
 548                               <0x01c82000 0x2000>,
 549                               <0x01c84000 0x2000>,
 550                               <0x01c86000 0x2000>;
 551                         interrupt-controller;
 552                         #interrupt-cells = <3>;
 553                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 554                 };
 555         };
 556 };