arch/arm/boot/dts/stm32h743.dtsi

   1 /*
   2  * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "armv7-m.dtsi"
  44 #include <dt-bindings/clock/stm32h7-clks.h>
  45 #include <dt-bindings/mfd/stm32h7-rcc.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47
  48 / {
  49         #address-cells = <1>;
  50         #size-cells = <1>;
  51
  52         clocks {
  53                 clk_hse: clk-hse {
  54                         #clock-cells = <0>;
  55                         compatible = "fixed-clock";
  56                         clock-frequency = <0>;
  57                 };
  58
  59                 clk_lse: clk-lse {
  60                         #clock-cells = <0>;
  61                         compatible = "fixed-clock";
  62                         clock-frequency = <32768>;
  63                 };
  64
  65                 clk_i2s: i2s_ckin {
  66                         #clock-cells = <0>;
  67                         compatible = "fixed-clock";
  68                         clock-frequency = <0>;
  69                 };
  70         };
  71
  72         soc {
  73                 timer5: timer@40000c00 {
  74                         compatible = "st,stm32-timer";
  75                         reg = <0x40000c00 0x400>;
  76                         interrupts = <50>;
  77                         clocks = <&rcc TIM5_CK>;
  78                 };
  79
  80                 lptimer1: timer@40002400 {
  81                         #address-cells = <1>;
  82                         #size-cells = <0>;
  83                         compatible = "st,stm32-lptimer";
  84                         reg = <0x40002400 0x400>;
  85                         clocks = <&rcc LPTIM1_CK>;
  86                         clock-names = "mux";
  87                         status = "disabled";
  88
  89                         pwm {
  90                                 compatible = "st,stm32-pwm-lp";
  91                                 #pwm-cells = <3>;
  92                                 status = "disabled";
  93                         };
  94
  95                         trigger@0 {
  96                                 compatible = "st,stm32-lptimer-trigger";
  97                                 reg = <0>;
  98                                 status = "disabled";
  99                         };
 100
 101                         counter {
 102                                 compatible = "st,stm32-lptimer-counter";
 103                                 status = "disabled";
 104                         };
 105                 };
 106
 107                 spi2: spi@40003800 {
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110                         compatible = "st,stm32h7-spi";
 111                         reg = <0x40003800 0x400>;
 112                         interrupts = <36>;
 113                         resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
 114                         clocks = <&rcc SPI2_CK>;
 115                         status = "disabled";
 116
 117                 };
 118
 119                 spi3: spi@40003c00 {
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         compatible = "st,stm32h7-spi";
 123                         reg = <0x40003c00 0x400>;
 124                         interrupts = <51>;
 125                         resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
 126                         clocks = <&rcc SPI3_CK>;
 127                         status = "disabled";
 128                 };
 129
 130                 usart2: serial@40004400 {
 131                         compatible = "st,stm32h7-uart";
 132                         reg = <0x40004400 0x400>;
 133                         interrupts = <38>;
 134                         status = "disabled";
 135                         clocks = <&rcc USART2_CK>;
 136                 };
 137
 138                 i2c1: i2c@40005400 {
 139                         compatible = "st,stm32f7-i2c";
 140                         #address-cells = <1>;
 141                         #size-cells = <0>;
 142                         reg = <0x40005400 0x400>;
 143                         interrupts = <31>,
 144                                      <32>;
 145                         resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
 146                         clocks = <&rcc I2C1_CK>;
 147                         status = "disabled";
 148                 };
 149
 150                 i2c2: i2c@40005800 {
 151                         compatible = "st,stm32f7-i2c";
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154                         reg = <0x40005800 0x400>;
 155                         interrupts = <33>,
 156                                      <34>;
 157                         resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
 158                         clocks = <&rcc I2C2_CK>;
 159                         status = "disabled";
 160                 };
 161
 162                 i2c3: i2c@40005C00 {
 163                         compatible = "st,stm32f7-i2c";
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                         reg = <0x40005C00 0x400>;
 167                         interrupts = <72>,
 168                                      <73>;
 169                         resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
 170                         clocks = <&rcc I2C3_CK>;
 171                         status = "disabled";
 172                 };
 173
 174                 dac: dac@40007400 {
 175                         compatible = "st,stm32h7-dac-core";
 176                         reg = <0x40007400 0x400>;
 177                         clocks = <&rcc DAC12_CK>;
 178                         clock-names = "pclk";
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         status = "disabled";
 182
 183                         dac1: dac@1 {
 184                                 compatible = "st,stm32-dac";
 185                                 #io-channel-cells = <1>;
 186                                 reg = <1>;
 187                                 status = "disabled";
 188                         };
 189
 190                         dac2: dac@2 {
 191                                 compatible = "st,stm32-dac";
 192                                 #io-channel-cells = <1>;
 193                                 reg = <2>;
 194                                 status = "disabled";
 195                         };
 196                 };
 197
 198                 usart1: serial@40011000 {
 199                         compatible = "st,stm32h7-uart";
 200                         reg = <0x40011000 0x400>;
 201                         interrupts = <37>;
 202                         status = "disabled";
 203                         clocks = <&rcc USART1_CK>;
 204                 };
 205
 206                 spi1: spi@40013000 {
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         compatible = "st,stm32h7-spi";
 210                         reg = <0x40013000 0x400>;
 211                         interrupts = <35>;
 212                         resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
 213                         clocks = <&rcc SPI1_CK>;
 214                         status = "disabled";
 215                 };
 216
 217                 spi4: spi@40013400 {
 218                         #address-cells = <1>;
 219                         #size-cells = <0>;
 220                         compatible = "st,stm32h7-spi";
 221                         reg = <0x40013400 0x400>;
 222                         interrupts = <84>;
 223                         resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
 224                         clocks = <&rcc SPI4_CK>;
 225                         status = "disabled";
 226                 };
 227
 228                 spi5: spi@40015000 {
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                         compatible = "st,stm32h7-spi";
 232                         reg = <0x40015000 0x400>;
 233                         interrupts = <85>;
 234                         resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
 235                         clocks = <&rcc SPI5_CK>;
 236                         status = "disabled";
 237                 };
 238
 239                 dma1: dma-controller@40020000 {
 240                         compatible = "st,stm32-dma";
 241                         reg = <0x40020000 0x400>;
 242                         interrupts = <11>,
 243                                      <12>,
 244                                      <13>,
 245                                      <14>,
 246                                      <15>,
 247                                      <16>,
 248                                      <17>,
 249                                      <47>;
 250                         clocks = <&rcc DMA1_CK>;
 251                         #dma-cells = <4>;
 252                         st,mem2mem;
 253                         dma-requests = <8>;
 254                         status = "disabled";
 255                 };
 256
 257                 dma2: dma-controller@40020400 {
 258                         compatible = "st,stm32-dma";
 259                         reg = <0x40020400 0x400>;
 260                         interrupts = <56>,
 261                                      <57>,
 262                                      <58>,
 263                                      <59>,
 264                                      <60>,
 265                                      <68>,
 266                                      <69>,
 267                                      <70>;
 268                         clocks = <&rcc DMA2_CK>;
 269                         #dma-cells = <4>;
 270                         st,mem2mem;
 271                         dma-requests = <8>;
 272                         status = "disabled";
 273                 };
 274
 275                 dmamux1: dma-router@40020800 {
 276                         compatible = "st,stm32h7-dmamux";
 277                         reg = <0x40020800 0x40>;
 278                         #dma-cells = <3>;
 279                         dma-channels = <16>;
 280                         dma-requests = <128>;
 281                         dma-masters = <&dma1 &dma2>;
 282                         clocks = <&rcc DMA1_CK>;
 283                 };
 284
 285                 adc_12: adc@40022000 {
 286                         compatible = "st,stm32h7-adc-core";
 287                         reg = <0x40022000 0x400>;
 288                         interrupts = <18>;
 289                         clocks = <&rcc ADC12_CK>;
 290                         clock-names = "bus";
 291                         interrupt-controller;
 292                         #interrupt-cells = <1>;
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                         status = "disabled";
 296
 297                         adc1: adc@0 {
 298                                 compatible = "st,stm32h7-adc";
 299                                 #io-channel-cells = <1>;
 300                                 reg = <0x0>;
 301                                 interrupt-parent = <&adc_12>;
 302                                 interrupts = <0>;
 303                                 status = "disabled";
 304                         };
 305
 306                         adc2: adc@100 {
 307                                 compatible = "st,stm32h7-adc";
 308                                 #io-channel-cells = <1>;
 309                                 reg = <0x100>;
 310                                 interrupt-parent = <&adc_12>;
 311                                 interrupts = <1>;
 312                                 status = "disabled";
 313                         };
 314                 };
 315
 316                 usbotg_hs: usb@40040000 {
 317                         compatible = "st,stm32f7-hsotg";
 318                         reg = <0x40040000 0x40000>;
 319                         interrupts = <77>;
 320                         clocks = <&rcc USB1OTG_CK>;
 321                         clock-names = "otg";
 322                         g-rx-fifo-size = <256>;
 323                         g-np-tx-fifo-size = <32>;
 324                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 325                         status = "disabled";
 326                 };
 327
 328                 usbotg_fs: usb@40080000 {
 329                         compatible = "st,stm32f4x9-fsotg";
 330                         reg = <0x40080000 0x40000>;
 331                         interrupts = <101>;
 332                         clocks = <&rcc USB2OTG_CK>;
 333                         clock-names = "otg";
 334                         status = "disabled";
 335                 };
 336
 337                 ltdc: display-controller@50001000 {
 338                         compatible = "st,stm32-ltdc";
 339                         reg = <0x50001000 0x200>;
 340                         interrupts = <88>, <89>;
 341                         resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
 342                         clocks = <&rcc LTDC_CK>;
 343                         clock-names = "lcd";
 344                         status = "disabled";
 345                 };
 346
 347                 mdma1: dma-controller@52000000 {
 348                         compatible = "st,stm32h7-mdma";
 349                         reg = <0x52000000 0x1000>;
 350                         interrupts = <122>;
 351                         clocks = <&rcc MDMA_CK>;
 352                         #dma-cells = <5>;
 353                         dma-channels = <16>;
 354                         dma-requests = <32>;
 355                 };
 356
 357                 sdmmc1: sdmmc@52007000 {
 358                         compatible = "arm,pl18x", "arm,primecell";
 359                         arm,primecell-periphid = <0x10153180>;
 360                         reg = <0x52007000 0x1000>;
 361                         interrupts = <49>;
 362                         interrupt-names = "cmd_irq";
 363                         clocks = <&rcc SDMMC1_CK>;
 364                         clock-names = "apb_pclk";
 365                         resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
 366                         cap-sd-highspeed;
 367                         cap-mmc-highspeed;
 368                         max-frequency = <120000000>;
 369                 };
 370
 371                 exti: interrupt-controller@58000000 {
 372                         compatible = "st,stm32h7-exti";
 373                         interrupt-controller;
 374                         #interrupt-cells = <2>;
 375                         reg = <0x58000000 0x400>;
 376                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
 377                 };
 378
 379                 syscfg: syscon@58000400 {
 380                         compatible = "st,stm32-syscfg", "syscon";
 381                         reg = <0x58000400 0x400>;
 382                 };
 383
 384                 spi6: spi@58001400 {
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                         compatible = "st,stm32h7-spi";
 388                         reg = <0x58001400 0x400>;
 389                         interrupts = <86>;
 390                         resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
 391                         clocks = <&rcc SPI6_CK>;
 392                         status = "disabled";
 393                 };
 394
 395                 i2c4: i2c@58001C00 {
 396                         compatible = "st,stm32f7-i2c";
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         reg = <0x58001C00 0x400>;
 400                         interrupts = <95>,
 401                                      <96>;
 402                         resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
 403                         clocks = <&rcc I2C4_CK>;
 404                         status = "disabled";
 405                 };
 406
 407                 lptimer2: timer@58002400 {
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         compatible = "st,stm32-lptimer";
 411                         reg = <0x58002400 0x400>;
 412                         clocks = <&rcc LPTIM2_CK>;
 413                         clock-names = "mux";
 414                         status = "disabled";
 415
 416                         pwm {
 417                                 compatible = "st,stm32-pwm-lp";
 418                                 #pwm-cells = <3>;
 419                                 status = "disabled";
 420                         };
 421
 422                         trigger@1 {
 423                                 compatible = "st,stm32-lptimer-trigger";
 424                                 reg = <1>;
 425                                 status = "disabled";
 426                         };
 427
 428                         counter {
 429                                 compatible = "st,stm32-lptimer-counter";
 430                                 status = "disabled";
 431                         };
 432                 };
 433
 434                 lptimer3: timer@58002800 {
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         compatible = "st,stm32-lptimer";
 438                         reg = <0x58002800 0x400>;
 439                         clocks = <&rcc LPTIM3_CK>;
 440                         clock-names = "mux";
 441                         status = "disabled";
 442
 443                         pwm {
 444                                 compatible = "st,stm32-pwm-lp";
 445                                 #pwm-cells = <3>;
 446                                 status = "disabled";
 447                         };
 448
 449                         trigger@2 {
 450                                 compatible = "st,stm32-lptimer-trigger";
 451                                 reg = <2>;
 452                                 status = "disabled";
 453                         };
 454                 };
 455
 456                 lptimer4: timer@58002c00 {
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459                         compatible = "st,stm32-lptimer";
 460                         reg = <0x58002c00 0x400>;
 461                         clocks = <&rcc LPTIM4_CK>;
 462                         clock-names = "mux";
 463                         status = "disabled";
 464
 465                         pwm {
 466                                 compatible = "st,stm32-pwm-lp";
 467                                 #pwm-cells = <3>;
 468                                 status = "disabled";
 469                         };
 470                 };
 471
 472                 lptimer5: timer@58003000 {
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                         compatible = "st,stm32-lptimer";
 476                         reg = <0x58003000 0x400>;
 477                         clocks = <&rcc LPTIM5_CK>;
 478                         clock-names = "mux";
 479                         status = "disabled";
 480
 481                         pwm {
 482                                 compatible = "st,stm32-pwm-lp";
 483                                 #pwm-cells = <3>;
 484                                 status = "disabled";
 485                         };
 486                 };
 487
 488                 vrefbuf: regulator@58003c00 {
 489                         compatible = "st,stm32-vrefbuf";
 490                         reg = <0x58003C00 0x8>;
 491                         clocks = <&rcc VREF_CK>;
 492                         regulator-min-microvolt = <1500000>;
 493                         regulator-max-microvolt = <2500000>;
 494                         status = "disabled";
 495                 };
 496
 497                 rtc: rtc@58004000 {
 498                         compatible = "st,stm32h7-rtc";
 499                         reg = <0x58004000 0x400>;
 500                         clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
 501                         clock-names = "pclk", "rtc_ck";
 502                         assigned-clocks = <&rcc RTC_CK>;
 503                         assigned-clock-parents = <&rcc LSE_CK>;
 504                         interrupt-parent = <&exti>;
 505                         interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 506                         st,syscfg = <&pwrcfg 0x00 0x100>;
 507                         status = "disabled";
 508                 };
 509
 510                 rcc: reset-clock-controller@58024400 {
 511                         compatible = "st,stm32h743-rcc", "st,stm32-rcc";
 512                         reg = <0x58024400 0x400>;
 513                         #clock-cells = <1>;
 514                         #reset-cells = <1>;
 515                         clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
 516                         st,syscfg = <&pwrcfg>;
 517                 };
 518
 519                 pwrcfg: power-config@58024800 {
 520                         compatible = "st,stm32-power-config", "syscon";
 521                         reg = <0x58024800 0x400>;
 522                 };
 523
 524                 adc_3: adc@58026000 {
 525                         compatible = "st,stm32h7-adc-core";
 526                         reg = <0x58026000 0x400>;
 527                         interrupts = <127>;
 528                         clocks = <&rcc ADC3_CK>;
 529                         clock-names = "bus";
 530                         interrupt-controller;
 531                         #interrupt-cells = <1>;
 532                         #address-cells = <1>;
 533                         #size-cells = <0>;
 534                         status = "disabled";
 535
 536                         adc3: adc@0 {
 537                                 compatible = "st,stm32h7-adc";
 538                                 #io-channel-cells = <1>;
 539                                 reg = <0x0>;
 540                                 interrupt-parent = <&adc_3>;
 541                                 interrupts = <0>;
 542                                 status = "disabled";
 543                         };
 544                 };
 545
 546                 mac: ethernet@40028000 {
 547                         compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
 548                         reg = <0x40028000 0x8000>;
 549                         reg-names = "stmmaceth";
 550                         interrupts = <61>;
 551                         interrupt-names = "macirq";
 552                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 553                         clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
 554                         st,syscon = <&syscfg 0x4>;
 555                         snps,pbl = <8>;
 556                         status = "disabled";
 557                 };
 558         };
 559 };
 560
 561 &systick {
 562         clock-frequency = <250000000>;
 563         status = "okay";
 564 };