arch/arm/boot/dts/stm32h743.dtsi

   1 /*
   2  * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "armv7-m.dtsi"
  44 #include <dt-bindings/clock/stm32h7-clks.h>
  45 #include <dt-bindings/mfd/stm32h7-rcc.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47
  48 / {
  49         #address-cells = <1>;
  50         #size-cells = <1>;
  51
  52         clocks {
  53                 clk_hse: clk-hse {
  54                         #clock-cells = <0>;
  55                         compatible = "fixed-clock";
  56                         clock-frequency = <0>;
  57                 };
  58
  59                 clk_lse: clk-lse {
  60                         #clock-cells = <0>;
  61                         compatible = "fixed-clock";
  62                         clock-frequency = <32768>;
  63                 };
  64
  65                 clk_i2s: i2s_ckin {
  66                         #clock-cells = <0>;
  67                         compatible = "fixed-clock";
  68                         clock-frequency = <0>;
  69                 };
  70         };
  71
  72         soc {
  73                 timer5: timer@40000c00 {
  74                         compatible = "st,stm32-timer";
  75                         reg = <0x40000c00 0x400>;
  76                         interrupts = <50>;
  77                         clocks = <&rcc TIM5_CK>;
  78                 };
  79
  80                 lptimer1: timer@40002400 {
  81                         #address-cells = <1>;
  82                         #size-cells = <0>;
  83                         compatible = "st,stm32-lptimer";
  84                         reg = <0x40002400 0x400>;
  85                         clocks = <&rcc LPTIM1_CK>;
  86                         clock-names = "mux";
  87                         status = "disabled";
  88
  89                         pwm {
  90                                 compatible = "st,stm32-pwm-lp";
  91                                 #pwm-cells = <3>;
  92                                 status = "disabled";
  93                         };
  94
  95                         trigger@0 {
  96                                 compatible = "st,stm32-lptimer-trigger";
  97                                 reg = <0>;
  98                                 status = "disabled";
  99                         };
 100
 101                         counter {
 102                                 compatible = "st,stm32-lptimer-counter";
 103                                 status = "disabled";
 104                         };
 105                 };
 106
 107                 spi2: spi@40003800 {
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110                         compatible = "st,stm32h7-spi";
 111                         reg = <0x40003800 0x400>;
 112                         interrupts = <36>;
 113                         resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
 114                         clocks = <&rcc SPI2_CK>;
 115                         status = "disabled";
 116
 117                 };
 118
 119                 spi3: spi@40003c00 {
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         compatible = "st,stm32h7-spi";
 123                         reg = <0x40003c00 0x400>;
 124                         interrupts = <51>;
 125                         resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
 126                         clocks = <&rcc SPI3_CK>;
 127                         status = "disabled";
 128                 };
 129
 130                 usart2: serial@40004400 {
 131                         compatible = "st,stm32h7-uart";
 132                         reg = <0x40004400 0x400>;
 133                         interrupts = <38>;
 134                         status = "disabled";
 135                         clocks = <&rcc USART2_CK>;
 136                 };
 137
 138                 usart3: serial@40004800 {
 139                         compatible = "st,stm32h7-uart";
 140                         reg = <0x40004800 0x400>;
 141                         interrupts = <39>;
 142                         status = "disabled";
 143                         clocks = <&rcc USART3_CK>;
 144                 };
 145
 146                 uart4: serial@40004c00 {
 147                         compatible = "st,stm32h7-uart";
 148                         reg = <0x40004c00 0x400>;
 149                         interrupts = <52>;
 150                         status = "disabled";
 151                         clocks = <&rcc UART4_CK>;
 152                 };
 153
 154                 i2c1: i2c@40005400 {
 155                         compatible = "st,stm32f7-i2c";
 156                         #address-cells = <1>;
 157                         #size-cells = <0>;
 158                         reg = <0x40005400 0x400>;
 159                         interrupts = <31>,
 160                                      <32>;
 161                         resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
 162                         clocks = <&rcc I2C1_CK>;
 163                         status = "disabled";
 164                 };
 165
 166                 i2c2: i2c@40005800 {
 167                         compatible = "st,stm32f7-i2c";
 168                         #address-cells = <1>;
 169                         #size-cells = <0>;
 170                         reg = <0x40005800 0x400>;
 171                         interrupts = <33>,
 172                                      <34>;
 173                         resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
 174                         clocks = <&rcc I2C2_CK>;
 175                         status = "disabled";
 176                 };
 177
 178                 i2c3: i2c@40005c00 {
 179                         compatible = "st,stm32f7-i2c";
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         reg = <0x40005C00 0x400>;
 183                         interrupts = <72>,
 184                                      <73>;
 185                         resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
 186                         clocks = <&rcc I2C3_CK>;
 187                         status = "disabled";
 188                 };
 189
 190                 dac: dac@40007400 {
 191                         compatible = "st,stm32h7-dac-core";
 192                         reg = <0x40007400 0x400>;
 193                         clocks = <&rcc DAC12_CK>;
 194                         clock-names = "pclk";
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         status = "disabled";
 198
 199                         dac1: dac@1 {
 200                                 compatible = "st,stm32-dac";
 201                                 #io-channel-cells = <1>;
 202                                 reg = <1>;
 203                                 status = "disabled";
 204                         };
 205
 206                         dac2: dac@2 {
 207                                 compatible = "st,stm32-dac";
 208                                 #io-channel-cells = <1>;
 209                                 reg = <2>;
 210                                 status = "disabled";
 211                         };
 212                 };
 213
 214                 usart1: serial@40011000 {
 215                         compatible = "st,stm32h7-uart";
 216                         reg = <0x40011000 0x400>;
 217                         interrupts = <37>;
 218                         status = "disabled";
 219                         clocks = <&rcc USART1_CK>;
 220                 };
 221
 222                 spi1: spi@40013000 {
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         compatible = "st,stm32h7-spi";
 226                         reg = <0x40013000 0x400>;
 227                         interrupts = <35>;
 228                         resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
 229                         clocks = <&rcc SPI1_CK>;
 230                         status = "disabled";
 231                 };
 232
 233                 spi4: spi@40013400 {
 234                         #address-cells = <1>;
 235                         #size-cells = <0>;
 236                         compatible = "st,stm32h7-spi";
 237                         reg = <0x40013400 0x400>;
 238                         interrupts = <84>;
 239                         resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
 240                         clocks = <&rcc SPI4_CK>;
 241                         status = "disabled";
 242                 };
 243
 244                 spi5: spi@40015000 {
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         compatible = "st,stm32h7-spi";
 248                         reg = <0x40015000 0x400>;
 249                         interrupts = <85>;
 250                         resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
 251                         clocks = <&rcc SPI5_CK>;
 252                         status = "disabled";
 253                 };
 254
 255                 dma1: dma-controller@40020000 {
 256                         compatible = "st,stm32-dma";
 257                         reg = <0x40020000 0x400>;
 258                         interrupts = <11>,
 259                                      <12>,
 260                                      <13>,
 261                                      <14>,
 262                                      <15>,
 263                                      <16>,
 264                                      <17>,
 265                                      <47>;
 266                         clocks = <&rcc DMA1_CK>;
 267                         #dma-cells = <4>;
 268                         st,mem2mem;
 269                         dma-requests = <8>;
 270                         status = "disabled";
 271                 };
 272
 273                 dma2: dma-controller@40020400 {
 274                         compatible = "st,stm32-dma";
 275                         reg = <0x40020400 0x400>;
 276                         interrupts = <56>,
 277                                      <57>,
 278                                      <58>,
 279                                      <59>,
 280                                      <60>,
 281                                      <68>,
 282                                      <69>,
 283                                      <70>;
 284                         clocks = <&rcc DMA2_CK>;
 285                         #dma-cells = <4>;
 286                         st,mem2mem;
 287                         dma-requests = <8>;
 288                         status = "disabled";
 289                 };
 290
 291                 dmamux1: dma-router@40020800 {
 292                         compatible = "st,stm32h7-dmamux";
 293                         reg = <0x40020800 0x40>;
 294                         #dma-cells = <3>;
 295                         dma-channels = <16>;
 296                         dma-requests = <128>;
 297                         dma-masters = <&dma1 &dma2>;
 298                         clocks = <&rcc DMA1_CK>;
 299                 };
 300
 301                 adc_12: adc@40022000 {
 302                         compatible = "st,stm32h7-adc-core";
 303                         reg = <0x40022000 0x400>;
 304                         interrupts = <18>;
 305                         clocks = <&rcc ADC12_CK>;
 306                         clock-names = "bus";
 307                         interrupt-controller;
 308                         #interrupt-cells = <1>;
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                         status = "disabled";
 312
 313                         adc1: adc@0 {
 314                                 compatible = "st,stm32h7-adc";
 315                                 #io-channel-cells = <1>;
 316                                 reg = <0x0>;
 317                                 interrupt-parent = <&adc_12>;
 318                                 interrupts = <0>;
 319                                 status = "disabled";
 320                         };
 321
 322                         adc2: adc@100 {
 323                                 compatible = "st,stm32h7-adc";
 324                                 #io-channel-cells = <1>;
 325                                 reg = <0x100>;
 326                                 interrupt-parent = <&adc_12>;
 327                                 interrupts = <1>;
 328                                 status = "disabled";
 329                         };
 330                 };
 331
 332                 usbotg_hs: usb@40040000 {
 333                         compatible = "st,stm32f7-hsotg";
 334                         reg = <0x40040000 0x40000>;
 335                         interrupts = <77>;
 336                         clocks = <&rcc USB1OTG_CK>;
 337                         clock-names = "otg";
 338                         g-rx-fifo-size = <256>;
 339                         g-np-tx-fifo-size = <32>;
 340                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 341                         status = "disabled";
 342                 };
 343
 344                 usbotg_fs: usb@40080000 {
 345                         compatible = "st,stm32f4x9-fsotg";
 346                         reg = <0x40080000 0x40000>;
 347                         interrupts = <101>;
 348                         clocks = <&rcc USB2OTG_CK>;
 349                         clock-names = "otg";
 350                         status = "disabled";
 351                 };
 352
 353                 ltdc: display-controller@50001000 {
 354                         compatible = "st,stm32-ltdc";
 355                         reg = <0x50001000 0x200>;
 356                         interrupts = <88>, <89>;
 357                         resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
 358                         clocks = <&rcc LTDC_CK>;
 359                         clock-names = "lcd";
 360                         status = "disabled";
 361                 };
 362
 363                 mdma1: dma-controller@52000000 {
 364                         compatible = "st,stm32h7-mdma";
 365                         reg = <0x52000000 0x1000>;
 366                         interrupts = <122>;
 367                         clocks = <&rcc MDMA_CK>;
 368                         #dma-cells = <5>;
 369                         dma-channels = <16>;
 370                         dma-requests = <32>;
 371                 };
 372
 373                 sdmmc1: mmc@52007000 {
 374                         compatible = "arm,pl18x", "arm,primecell";
 375                         arm,primecell-periphid = <0x10153180>;
 376                         reg = <0x52007000 0x1000>;
 377                         interrupts = <49>;
 378                         interrupt-names = "cmd_irq";
 379                         clocks = <&rcc SDMMC1_CK>;
 380                         clock-names = "apb_pclk";
 381                         resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
 382                         cap-sd-highspeed;
 383                         cap-mmc-highspeed;
 384                         max-frequency = <120000000>;
 385                 };
 386
 387                 sdmmc2: mmc@48022400 {
 388                         compatible = "arm,pl18x", "arm,primecell";
 389                         arm,primecell-periphid = <0x10153180>;
 390                         reg = <0x48022400 0x400>;
 391                         interrupts = <124>;
 392                         interrupt-names = "cmd_irq";
 393                         clocks = <&rcc SDMMC2_CK>;
 394                         clock-names = "apb_pclk";
 395                         resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
 396                         cap-sd-highspeed;
 397                         cap-mmc-highspeed;
 398                         max-frequency = <120000000>;
 399                         status = "disabled";
 400                 };
 401
 402                 exti: interrupt-controller@58000000 {
 403                         compatible = "st,stm32h7-exti";
 404                         interrupt-controller;
 405                         #interrupt-cells = <2>;
 406                         reg = <0x58000000 0x400>;
 407                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
 408                 };
 409
 410                 syscfg: syscon@58000400 {
 411                         compatible = "st,stm32-syscfg", "syscon";
 412                         reg = <0x58000400 0x400>;
 413                 };
 414
 415                 spi6: spi@58001400 {
 416                         #address-cells = <1>;
 417                         #size-cells = <0>;
 418                         compatible = "st,stm32h7-spi";
 419                         reg = <0x58001400 0x400>;
 420                         interrupts = <86>;
 421                         resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
 422                         clocks = <&rcc SPI6_CK>;
 423                         status = "disabled";
 424                 };
 425
 426                 i2c4: i2c@58001c00 {
 427                         compatible = "st,stm32f7-i2c";
 428                         #address-cells = <1>;
 429                         #size-cells = <0>;
 430                         reg = <0x58001C00 0x400>;
 431                         interrupts = <95>,
 432                                      <96>;
 433                         resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
 434                         clocks = <&rcc I2C4_CK>;
 435                         status = "disabled";
 436                 };
 437
 438                 lptimer2: timer@58002400 {
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         compatible = "st,stm32-lptimer";
 442                         reg = <0x58002400 0x400>;
 443                         clocks = <&rcc LPTIM2_CK>;
 444                         clock-names = "mux";
 445                         status = "disabled";
 446
 447                         pwm {
 448                                 compatible = "st,stm32-pwm-lp";
 449                                 #pwm-cells = <3>;
 450                                 status = "disabled";
 451                         };
 452
 453                         trigger@1 {
 454                                 compatible = "st,stm32-lptimer-trigger";
 455                                 reg = <1>;
 456                                 status = "disabled";
 457                         };
 458
 459                         counter {
 460                                 compatible = "st,stm32-lptimer-counter";
 461                                 status = "disabled";
 462                         };
 463                 };
 464
 465                 lptimer3: timer@58002800 {
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                         compatible = "st,stm32-lptimer";
 469                         reg = <0x58002800 0x400>;
 470                         clocks = <&rcc LPTIM3_CK>;
 471                         clock-names = "mux";
 472                         status = "disabled";
 473
 474                         pwm {
 475                                 compatible = "st,stm32-pwm-lp";
 476                                 #pwm-cells = <3>;
 477                                 status = "disabled";
 478                         };
 479
 480                         trigger@2 {
 481                                 compatible = "st,stm32-lptimer-trigger";
 482                                 reg = <2>;
 483                                 status = "disabled";
 484                         };
 485                 };
 486
 487                 lptimer4: timer@58002c00 {
 488                         compatible = "st,stm32-lptimer";
 489                         reg = <0x58002c00 0x400>;
 490                         clocks = <&rcc LPTIM4_CK>;
 491                         clock-names = "mux";
 492                         status = "disabled";
 493
 494                         pwm {
 495                                 compatible = "st,stm32-pwm-lp";
 496                                 #pwm-cells = <3>;
 497                                 status = "disabled";
 498                         };
 499                 };
 500
 501                 lptimer5: timer@58003000 {
 502                         compatible = "st,stm32-lptimer";
 503                         reg = <0x58003000 0x400>;
 504                         clocks = <&rcc LPTIM5_CK>;
 505                         clock-names = "mux";
 506                         status = "disabled";
 507
 508                         pwm {
 509                                 compatible = "st,stm32-pwm-lp";
 510                                 #pwm-cells = <3>;
 511                                 status = "disabled";
 512                         };
 513                 };
 514
 515                 vrefbuf: regulator@58003c00 {
 516                         compatible = "st,stm32-vrefbuf";
 517                         reg = <0x58003C00 0x8>;
 518                         clocks = <&rcc VREF_CK>;
 519                         regulator-min-microvolt = <1500000>;
 520                         regulator-max-microvolt = <2500000>;
 521                         status = "disabled";
 522                 };
 523
 524                 rtc: rtc@58004000 {
 525                         compatible = "st,stm32h7-rtc";
 526                         reg = <0x58004000 0x400>;
 527                         clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
 528                         clock-names = "pclk", "rtc_ck";
 529                         assigned-clocks = <&rcc RTC_CK>;
 530                         assigned-clock-parents = <&rcc LSE_CK>;
 531                         interrupt-parent = <&exti>;
 532                         interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 533                         st,syscfg = <&pwrcfg 0x00 0x100>;
 534                         status = "disabled";
 535                 };
 536
 537                 rcc: reset-clock-controller@58024400 {
 538                         compatible = "st,stm32h743-rcc", "st,stm32-rcc";
 539                         reg = <0x58024400 0x400>;
 540                         #clock-cells = <1>;
 541                         #reset-cells = <1>;
 542                         clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
 543                         st,syscfg = <&pwrcfg>;
 544                 };
 545
 546                 pwrcfg: power-config@58024800 {
 547                         compatible = "st,stm32-power-config", "syscon";
 548                         reg = <0x58024800 0x400>;
 549                 };
 550
 551                 adc_3: adc@58026000 {
 552                         compatible = "st,stm32h7-adc-core";
 553                         reg = <0x58026000 0x400>;
 554                         interrupts = <127>;
 555                         clocks = <&rcc ADC3_CK>;
 556                         clock-names = "bus";
 557                         interrupt-controller;
 558                         #interrupt-cells = <1>;
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561                         status = "disabled";
 562
 563                         adc3: adc@0 {
 564                                 compatible = "st,stm32h7-adc";
 565                                 #io-channel-cells = <1>;
 566                                 reg = <0x0>;
 567                                 interrupt-parent = <&adc_3>;
 568                                 interrupts = <0>;
 569                                 status = "disabled";
 570                         };
 571                 };
 572
 573                 mac: ethernet@40028000 {
 574                         compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
 575                         reg = <0x40028000 0x8000>;
 576                         reg-names = "stmmaceth";
 577                         interrupts = <61>;
 578                         interrupt-names = "macirq";
 579                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 580                         clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
 581                         st,syscon = <&syscfg 0x4>;
 582                         snps,pbl = <8>;
 583                         status = "disabled";
 584                 };
 585
 586                 pinctrl: pin-controller@58020000 {
 587                         #address-cells = <1>;
 588                         #size-cells = <1>;
 589                         compatible = "st,stm32h743-pinctrl";
 590                         ranges = <0 0x58020000 0x3000>;
 591                         interrupt-parent = <&exti>;
 592                         st,syscfg = <&syscfg 0x8>;
 593                         pins-are-numbered;
 594
 595                         gpioa: gpio@58020000 {
 596                                 gpio-controller;
 597                                 #gpio-cells = <2>;
 598                                 reg = <0x0 0x400>;
 599                                 clocks = <&rcc GPIOA_CK>;
 600                                 st,bank-name = "GPIOA";
 601                                 interrupt-controller;
 602                                 #interrupt-cells = <2>;
 603                                 ngpios = <16>;
 604                                 gpio-ranges = <&pinctrl 0 0 16>;
 605                         };
 606
 607                         gpiob: gpio@58020400 {
 608                                 gpio-controller;
 609                                 #gpio-cells = <2>;
 610                                 reg = <0x400 0x400>;
 611                                 clocks = <&rcc GPIOB_CK>;
 612                                 st,bank-name = "GPIOB";
 613                                 interrupt-controller;
 614                                 #interrupt-cells = <2>;
 615                                 ngpios = <16>;
 616                                 gpio-ranges = <&pinctrl 0 16 16>;
 617                         };
 618
 619                         gpioc: gpio@58020800 {
 620                                 gpio-controller;
 621                                 #gpio-cells = <2>;
 622                                 reg = <0x800 0x400>;
 623                                 clocks = <&rcc GPIOC_CK>;
 624                                 st,bank-name = "GPIOC";
 625                                 interrupt-controller;
 626                                 #interrupt-cells = <2>;
 627                                 ngpios = <16>;
 628                                 gpio-ranges = <&pinctrl 0 32 16>;
 629                         };
 630
 631                         gpiod: gpio@58020c00 {
 632                                 gpio-controller;
 633                                 #gpio-cells = <2>;
 634                                 reg = <0xc00 0x400>;
 635                                 clocks = <&rcc GPIOD_CK>;
 636                                 st,bank-name = "GPIOD";
 637                                 interrupt-controller;
 638                                 #interrupt-cells = <2>;
 639                                 ngpios = <16>;
 640                                 gpio-ranges = <&pinctrl 0 48 16>;
 641                         };
 642
 643                         gpioe: gpio@58021000 {
 644                                 gpio-controller;
 645                                 #gpio-cells = <2>;
 646                                 reg = <0x1000 0x400>;
 647                                 clocks = <&rcc GPIOE_CK>;
 648                                 st,bank-name = "GPIOE";
 649                                 interrupt-controller;
 650                                 #interrupt-cells = <2>;
 651                                 ngpios = <16>;
 652                                 gpio-ranges = <&pinctrl 0 64 16>;
 653                         };
 654
 655                         gpiof: gpio@58021400 {
 656                                 gpio-controller;
 657                                 #gpio-cells = <2>;
 658                                 reg = <0x1400 0x400>;
 659                                 clocks = <&rcc GPIOF_CK>;
 660                                 st,bank-name = "GPIOF";
 661                                 interrupt-controller;
 662                                 #interrupt-cells = <2>;
 663                                 ngpios = <16>;
 664                                 gpio-ranges = <&pinctrl 0 80 16>;
 665                         };
 666
 667                         gpiog: gpio@58021800 {
 668                                 gpio-controller;
 669                                 #gpio-cells = <2>;
 670                                 reg = <0x1800 0x400>;
 671                                 clocks = <&rcc GPIOG_CK>;
 672                                 st,bank-name = "GPIOG";
 673                                 interrupt-controller;
 674                                 #interrupt-cells = <2>;
 675                                 ngpios = <16>;
 676                                 gpio-ranges = <&pinctrl 0 96 16>;
 677                         };
 678
 679                         gpioh: gpio@58021c00 {
 680                                 gpio-controller;
 681                                 #gpio-cells = <2>;
 682                                 reg = <0x1c00 0x400>;
 683                                 clocks = <&rcc GPIOH_CK>;
 684                                 st,bank-name = "GPIOH";
 685                                 interrupt-controller;
 686                                 #interrupt-cells = <2>;
 687                                 ngpios = <16>;
 688                                 gpio-ranges = <&pinctrl 0 112 16>;
 689                         };
 690
 691                         gpioi: gpio@58022000 {
 692                                 gpio-controller;
 693                                 #gpio-cells = <2>;
 694                                 reg = <0x2000 0x400>;
 695                                 clocks = <&rcc GPIOI_CK>;
 696                                 st,bank-name = "GPIOI";
 697                                 interrupt-controller;
 698                                 #interrupt-cells = <2>;
 699                                 ngpios = <16>;
 700                                 gpio-ranges = <&pinctrl 0 128 16>;
 701                         };
 702
 703                         gpioj: gpio@58022400 {
 704                                 gpio-controller;
 705                                 #gpio-cells = <2>;
 706                                 reg = <0x2400 0x400>;
 707                                 clocks = <&rcc GPIOJ_CK>;
 708                                 st,bank-name = "GPIOJ";
 709                                 interrupt-controller;
 710                                 #interrupt-cells = <2>;
 711                                 ngpios = <16>;
 712                                 gpio-ranges = <&pinctrl 0 144 16>;
 713                         };
 714
 715                         gpiok: gpio@58022800 {
 716                                 gpio-controller;
 717                                 #gpio-cells = <2>;
 718                                 reg = <0x2800 0x400>;
 719                                 clocks = <&rcc GPIOK_CK>;
 720                                 st,bank-name = "GPIOK";
 721                                 interrupt-controller;
 722                                 #interrupt-cells = <2>;
 723                                 ngpios = <8>;
 724                                 gpio-ranges = <&pinctrl 0 160 8>;
 725                         };
 726                 };
 727         };
 728 };
 729
 730 &systick {
 731         clock-frequency = <250000000>;
 732         status = "okay";
 733 };