arch/arm/boot/dts/rv1108.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/rv1108-cru.h>
   7 #include <dt-bindings/pinctrl/rockchip.h>
   8 #include <dt-bindings/thermal/thermal.h>
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12
  13         compatible = "rockchip,rv1108";
  14
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 i2c0 = &i2c0;
  19                 i2c1 = &i2c1;
  20                 i2c2 = &i2c2;
  21                 i2c3 = &i2c3;
  22                 serial0 = &uart0;
  23                 serial1 = &uart1;
  24                 serial2 = &uart2;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu0: cpu@f00 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34                         reg = <0xf00>;
  35                         clock-latency = <40000>;
  36                         clocks = <&cru ARMCLK>;
  37                         #cooling-cells = <2>; /* min followed by max */
  38                         dynamic-power-coefficient = <75>;
  39                         operating-points-v2 = <&cpu_opp_table>;
  40                 };
  41         };
  42
  43         cpu_opp_table: opp_table {
  44                 compatible = "operating-points-v2";
  45
  46                 opp-408000000 {
  47                         opp-hz = /bits/ 64 <408000000>;
  48                         opp-microvolt = <975000>;
  49                         clock-latency-ns = <40000>;
  50                 };
  51                 opp-600000000 {
  52                         opp-hz = /bits/ 64 <600000000>;
  53                         opp-microvolt = <975000>;
  54                         clock-latency-ns = <40000>;
  55                 };
  56                 opp-816000000 {
  57                         opp-hz = /bits/ 64 <816000000>;
  58                         opp-microvolt = <1025000>;
  59                         clock-latency-ns = <40000>;
  60                 };
  61                 opp-1008000000 {
  62                         opp-hz = /bits/ 64 <1008000000>;
  63                         opp-microvolt = <1150000>;
  64                         clock-latency-ns = <40000>;
  65                 };
  66         };
  67
  68         arm-pmu {
  69                 compatible = "arm,cortex-a7-pmu";
  70                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  71         };
  72
  73         timer {
  74                 compatible = "arm,armv7-timer";
  75                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
  76                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  77                 arm,cpu-registers-not-fw-configured;
  78                 clock-frequency = <24000000>;
  79         };
  80
  81         xin24m: oscillator {
  82                 compatible = "fixed-clock";
  83                 clock-frequency = <24000000>;
  84                 clock-output-names = "xin24m";
  85                 #clock-cells = <0>;
  86         };
  87
  88         amba: bus {
  89                 compatible = "simple-bus";
  90                 #address-cells = <1>;
  91                 #size-cells = <1>;
  92                 ranges;
  93
  94                 pdma: pdma@102a0000 {
  95                         compatible = "arm,pl330", "arm,primecell";
  96                         reg = <0x102a0000 0x4000>;
  97                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  98                         #dma-cells = <1>;
  99                         arm,pl330-broken-no-flushp;
 100                         arm,pl330-periph-burst;
 101                         clocks = <&cru ACLK_DMAC>;
 102                         clock-names = "apb_pclk";
 103                 };
 104         };
 105
 106         bus_intmem: sram@10080000 {
 107                 compatible = "mmio-sram";
 108                 reg = <0x10080000 0x2000>;
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 ranges = <0 0x10080000 0x2000>;
 112         };
 113
 114         uart2: serial@10210000 {
 115                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
 116                 reg = <0x10210000 0x100>;
 117                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 118                 reg-shift = <2>;
 119                 reg-io-width = <4>;
 120                 clock-frequency = <24000000>;
 121                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 122                 clock-names = "baudclk", "apb_pclk";
 123                 dmas = <&pdma 6>, <&pdma 7>;
 124                 pinctrl-names = "default";
 125                 pinctrl-0 = <&uart2m0_xfer>;
 126                 status = "disabled";
 127         };
 128
 129         uart1: serial@10220000 {
 130                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
 131                 reg = <0x10220000 0x100>;
 132                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 133                 reg-shift = <2>;
 134                 reg-io-width = <4>;
 135                 clock-frequency = <24000000>;
 136                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 137                 clock-names = "baudclk", "apb_pclk";
 138                 dmas = <&pdma 4>, <&pdma 5>;
 139                 pinctrl-names = "default";
 140                 pinctrl-0 = <&uart1_xfer>;
 141                 status = "disabled";
 142         };
 143
 144         uart0: serial@10230000 {
 145                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
 146                 reg = <0x10230000 0x100>;
 147                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 148                 reg-shift = <2>;
 149                 reg-io-width = <4>;
 150                 clock-frequency = <24000000>;
 151                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 152                 clock-names = "baudclk", "apb_pclk";
 153                 dmas = <&pdma 2>, <&pdma 3>;
 154                 pinctrl-names = "default";
 155                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 156                 status = "disabled";
 157         };
 158
 159         i2c1: i2c@10240000 {
 160                 compatible = "rockchip,rv1108-i2c";
 161                 reg = <0x10240000 0x1000>;
 162                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 166                 clock-names = "i2c", "pclk";
 167                 pinctrl-names = "default";
 168                 pinctrl-0 = <&i2c1_xfer>;
 169                 rockchip,grf = <&grf>;
 170                 status = "disabled";
 171         };
 172
 173         i2c2: i2c@10250000 {
 174                 compatible = "rockchip,rv1108-i2c";
 175                 reg = <0x10250000 0x1000>;
 176                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 177                 #address-cells = <1>;
 178                 #size-cells = <0>;
 179                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 180                 clock-names = "i2c", "pclk";
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&i2c2m1_xfer>;
 183                 rockchip,grf = <&grf>;
 184                 status = "disabled";
 185         };
 186
 187         i2c3: i2c@10260000 {
 188                 compatible = "rockchip,rv1108-i2c";
 189                 reg = <0x10260000 0x1000>;
 190                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 191                 #address-cells = <1>;
 192                 #size-cells = <0>;
 193                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 194                 clock-names = "i2c", "pclk";
 195                 pinctrl-names = "default";
 196                 pinctrl-0 = <&i2c3_xfer>;
 197                 rockchip,grf = <&grf>;
 198                 status = "disabled";
 199         };
 200
 201         spi: spi@10270000 {
 202                 compatible = "rockchip,rv1108-spi";
 203                 reg = <0x10270000 0x1000>;
 204                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 205                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 206                 clock-names = "spiclk", "apb_pclk";
 207                 dmas = <&pdma 8>, <&pdma 9>;
 208                 dma-names = "tx", "rx";
 209                 #address-cells = <1>;
 210                 #size-cells = <0>;
 211                 status = "disabled";
 212         };
 213
 214         pwm4: pwm@10280000 {
 215                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 216                 reg = <0x10280000 0x10>;
 217                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 219                 clock-names = "pwm", "pclk";
 220                 pinctrl-names = "default";
 221                 pinctrl-0 = <&pwm4_pin>;
 222                 #pwm-cells = <3>;
 223                 status = "disabled";
 224         };
 225
 226         pwm5: pwm@10280010 {
 227                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 228                 reg = <0x10280010 0x10>;
 229                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 230                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 231                 clock-names = "pwm", "pclk";
 232                 pinctrl-names = "default";
 233                 pinctrl-0 = <&pwm5_pin>;
 234                 #pwm-cells = <3>;
 235                 status = "disabled";
 236         };
 237
 238         pwm6: pwm@10280020 {
 239                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 240                 reg = <0x10280020 0x10>;
 241                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 242                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 243                 clock-names = "pwm", "pclk";
 244                 pinctrl-names = "default";
 245                 pinctrl-0 = <&pwm6_pin>;
 246                 #pwm-cells = <3>;
 247                 status = "disabled";
 248         };
 249
 250         pwm7: pwm@10280030 {
 251                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 252                 reg = <0x10280030 0x10>;
 253                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 254                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 255                 clock-names = "pwm", "pclk";
 256                 pinctrl-names = "default";
 257                 pinctrl-0 = <&pwm7_pin>;
 258                 #pwm-cells = <3>;
 259                 status = "disabled";
 260         };
 261
 262         grf: syscon@10300000 {
 263                 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
 264                 reg = <0x10300000 0x1000>;
 265                 #address-cells = <1>;
 266                 #size-cells = <1>;
 267
 268                 io_domains: io-domains {
 269                         compatible = "rockchip,rv1108-io-voltage-domain";
 270                         status = "disabled";
 271                 };
 272
 273                 u2phy: usb2phy@100 {
 274                         compatible = "rockchip,rv1108-usb2phy";
 275                         reg = <0x100 0x0c>;
 276                         clocks = <&cru SCLK_USBPHY>;
 277                         clock-names = "phyclk";
 278                         #clock-cells = <0>;
 279                         clock-output-names = "usbphy";
 280                         rockchip,usbgrf = <&usbgrf>;
 281                         status = "disabled";
 282
 283                         u2phy_otg: otg-port {
 284                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 285                                 interrupt-names = "otg-mux";
 286                                 #phy-cells = <0>;
 287                                 status = "disabled";
 288                         };
 289
 290                         u2phy_host: host-port {
 291                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 292                                 interrupt-names = "linestate";
 293                                 #phy-cells = <0>;
 294                                 status = "disabled";
 295                         };
 296                 };
 297         };
 298
 299         timer: timer@10350000 {
 300                 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
 301                 reg = <0x10350000 0x20>;
 302                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 303                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 304                 clock-names = "timer", "pclk";
 305         };
 306
 307         watchdog: watchdog@10360000 {
 308                 compatible = "rockchip,rv1108-wdt", "snps,dw-wdt";
 309                 reg = <0x10360000 0x100>;
 310                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 311                 clocks = <&cru PCLK_WDT>;
 312                 status = "disabled";
 313         };
 314
 315         thermal-zones {
 316                 soc_thermal: soc-thermal {
 317                         polling-delay-passive = <20>;
 318                         polling-delay = <1000>;
 319                         sustainable-power = <50>;
 320                         thermal-sensors = <&tsadc 0>;
 321
 322                         trips {
 323                                 threshold: trip-point0 {
 324                                         temperature = <70000>;
 325                                         hysteresis = <2000>;
 326                                         type = "passive";
 327                                 };
 328                                 target: trip-point1 {
 329                                         temperature = <85000>;
 330                                         hysteresis = <2000>;
 331                                         type = "passive";
 332                                 };
 333                                 soc_crit: soc-crit {
 334                                         temperature = <95000>;
 335                                         hysteresis = <2000>;
 336                                         type = "critical";
 337                                 };
 338                         };
 339
 340                         cooling-maps {
 341                                 map0 {
 342                                         trip = <&target>;
 343                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 344                                         contribution = <4096>;
 345                                 };
 346                         };
 347                 };
 348         };
 349
 350         tsadc: tsadc@10370000 {
 351                 compatible = "rockchip,rv1108-tsadc";
 352                 reg = <0x10370000 0x100>;
 353                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 354                 assigned-clocks = <&cru SCLK_TSADC>;
 355                 assigned-clock-rates = <750000>;
 356                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 357                 clock-names = "tsadc", "apb_pclk";
 358                 pinctrl-names = "init", "default", "sleep";
 359                 pinctrl-0 = <&otp_pin>;
 360                 pinctrl-1 = <&otp_out>;
 361                 pinctrl-2 = <&otp_pin>;
 362                 resets = <&cru SRST_TSADC>;
 363                 reset-names = "tsadc-apb";
 364                 rockchip,hw-tshut-temp = <120000>;
 365                 #thermal-sensor-cells = <1>;
 366                 status = "disabled";
 367         };
 368
 369         adc: adc@1038c000 {
 370                 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
 371                 reg = <0x1038c000 0x100>;
 372                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 373                 #io-channel-cells = <1>;
 374                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 375                 clock-names = "saradc", "apb_pclk";
 376                 status = "disabled";
 377         };
 378
 379         i2c0: i2c@20000000 {
 380                 compatible = "rockchip,rv1108-i2c";
 381                 reg = <0x20000000 0x1000>;
 382                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385                 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
 386                 clock-names = "i2c", "pclk";
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&i2c0_xfer>;
 389                 rockchip,grf = <&grf>;
 390                 status = "disabled";
 391         };
 392
 393         pwm0: pwm@20040000 {
 394                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 395                 reg = <0x20040000 0x10>;
 396                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 397                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
 398                 clock-names = "pwm", "pclk";
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&pwm0_pin>;
 401                 #pwm-cells = <3>;
 402                 status = "disabled";
 403         };
 404
 405         pwm1: pwm@20040010 {
 406                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 407                 reg = <0x20040010 0x10>;
 408                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 409                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
 410                 clock-names = "pwm", "pclk";
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&pwm1_pin>;
 413                 #pwm-cells = <3>;
 414                 status = "disabled";
 415         };
 416
 417         pwm2: pwm@20040020 {
 418                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 419                 reg = <0x20040020 0x10>;
 420                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 421                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
 422                 clock-names = "pwm", "pclk";
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&pwm2_pin>;
 425                 #pwm-cells = <3>;
 426                 status = "disabled";
 427         };
 428
 429         pwm3: pwm@20040030 {
 430                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 431                 reg = <0x20040030 0x10>;
 432                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 433                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
 434                 clock-names = "pwm", "pclk";
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&pwm3_pin>;
 437                 #pwm-cells = <3>;
 438                 status = "disabled";
 439         };
 440
 441         pmugrf: syscon@20060000 {
 442                 compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd";
 443                 reg = <0x20060000 0x1000>;
 444
 445                 pmu_io_domains: io-domains {
 446                         compatible = "rockchip,rv1108-pmu-io-voltage-domain";
 447                         status = "disabled";
 448                 };
 449         };
 450
 451         usbgrf: syscon@202a0000 {
 452                 compatible = "rockchip,rv1108-usbgrf", "syscon";
 453                 reg = <0x202a0000 0x1000>;
 454         };
 455
 456         cru: clock-controller@20200000 {
 457                 compatible = "rockchip,rv1108-cru";
 458                 reg = <0x20200000 0x1000>;
 459                 rockchip,grf = <&grf>;
 460                 #clock-cells = <1>;
 461                 #reset-cells = <1>;
 462         };
 463
 464         nfc: nand-controller@30100000 {
 465                 compatible = "rockchip,rv1108-nfc";
 466                 reg = <0x30100000  0x1000>;
 467                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 468                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
 469                 clock-names = "ahb", "nfc";
 470                 assigned-clocks = <&cru SCLK_NANDC>;
 471                 assigned-clock-rates = <150000000>;
 472                 status = "disabled";
 473         };
 474
 475         emmc: mmc@30110000 {
 476                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 477                 reg = <0x30110000 0x4000>;
 478                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 479                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 480                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 481                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 482                 fifo-depth = <0x100>;
 483                 max-frequency = <150000000>;
 484                 status = "disabled";
 485         };
 486
 487         sdio: mmc@30120000 {
 488                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 489                 reg = <0x30120000 0x4000>;
 490                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 491                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 492                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 493                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 494                 fifo-depth = <0x100>;
 495                 max-frequency = <150000000>;
 496                 status = "disabled";
 497         };
 498
 499         sdmmc: mmc@30130000 {
 500                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 501                 reg = <0x30130000 0x4000>;
 502                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 504                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 505                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 506                 fifo-depth = <0x100>;
 507                 max-frequency = <100000000>;
 508                 pinctrl-names = "default";
 509                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
 510                 status = "disabled";
 511         };
 512
 513         usb_host_ehci: usb@30140000 {
 514                 compatible = "generic-ehci";
 515                 reg = <0x30140000 0x20000>;
 516                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 518                 phys = <&u2phy_host>;
 519                 phy-names = "usb";
 520                 status = "disabled";
 521         };
 522
 523         usb_host_ohci: usb@30160000 {
 524                 compatible = "generic-ohci";
 525                 reg = <0x30160000 0x20000>;
 526                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 527                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 528                 phys = <&u2phy_host>;
 529                 phy-names = "usb";
 530                 status = "disabled";
 531         };
 532
 533         usb_otg: usb@30180000 {
 534                 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
 535                              "snps,dwc2";
 536                 reg = <0x30180000 0x40000>;
 537                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 538                 clocks = <&cru HCLK_OTG>;
 539                 clock-names = "otg";
 540                 dr_mode = "otg";
 541                 g-np-tx-fifo-size = <16>;
 542                 g-rx-fifo-size = <280>;
 543                 g-tx-fifo-size = <256 128 128 64 32 16>;
 544                 phys = <&u2phy_otg>;
 545                 phy-names = "usb2-phy";
 546                 status = "disabled";
 547         };
 548
 549         sfc: spi@301c0000 {
 550                 compatible = "rockchip,sfc";
 551                 reg = <0x301c0000 0x4000>;
 552                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 553                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
 554                 clock-names = "clk_sfc", "hclk_sfc";
 555                 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
 556                 pinctrl-names = "default";
 557                 status = "disabled";
 558         };
 559
 560         gmac: eth@30200000 {
 561                 compatible = "rockchip,rv1108-gmac";
 562                 reg = <0x30200000 0x10000>;
 563                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 564                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 565                 interrupt-names = "macirq", "eth_wake_irq";
 566                 clocks = <&cru SCLK_MAC>,
 567                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
 568                         <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
 569                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 570                 clock-names = "stmmaceth",
 571                         "mac_clk_rx", "mac_clk_tx",
 572                         "clk_mac_ref", "clk_mac_refout",
 573                         "aclk_mac", "pclk_mac";
 574                 /* rv1108 only supports an rmii interface */
 575                 phy-mode = "rmii";
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&rmii_pins>;
 578                 rockchip,grf = <&grf>;
 579                 status = "disabled";
 580         };
 581
 582         gic: interrupt-controller@32010000 {
 583                 compatible = "arm,gic-400";
 584                 interrupt-controller;
 585                 #interrupt-cells = <3>;
 586                 #address-cells = <0>;
 587
 588                 reg = <0x32011000 0x1000>,
 589                       <0x32012000 0x2000>,
 590                       <0x32014000 0x2000>,
 591                       <0x32016000 0x2000>;
 592                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 593         };
 594
 595         pinctrl: pinctrl {
 596                 compatible = "rockchip,rv1108-pinctrl";
 597                 rockchip,grf = <&grf>;
 598                 rockchip,pmu = <&pmugrf>;
 599                 #address-cells = <1>;
 600                 #size-cells = <1>;
 601                 ranges;
 602
 603                 gpio0: gpio0@20030000 {
 604                         compatible = "rockchip,gpio-bank";
 605                         reg = <0x20030000 0x100>;
 606                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 607                         clocks = <&cru PCLK_GPIO0_PMU>;
 608
 609                         gpio-controller;
 610                         #gpio-cells = <2>;
 611
 612                         interrupt-controller;
 613                         #interrupt-cells = <2>;
 614                 };
 615
 616                 gpio1: gpio1@10310000 {
 617                         compatible = "rockchip,gpio-bank";
 618                         reg = <0x10310000 0x100>;
 619                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 620                         clocks = <&cru PCLK_GPIO1>;
 621
 622                         gpio-controller;
 623                         #gpio-cells = <2>;
 624
 625                         interrupt-controller;
 626                         #interrupt-cells = <2>;
 627                 };
 628
 629                 gpio2: gpio2@10320000 {
 630                         compatible = "rockchip,gpio-bank";
 631                         reg = <0x10320000 0x100>;
 632                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 633                         clocks = <&cru PCLK_GPIO2>;
 634
 635                         gpio-controller;
 636                         #gpio-cells = <2>;
 637
 638                         interrupt-controller;
 639                         #interrupt-cells = <2>;
 640                 };
 641
 642                 gpio3: gpio3@10330000 {
 643                         compatible = "rockchip,gpio-bank";
 644                         reg = <0x10330000 0x100>;
 645                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 646                         clocks = <&cru PCLK_GPIO3>;
 647
 648                         gpio-controller;
 649                         #gpio-cells = <2>;
 650
 651                         interrupt-controller;
 652                         #interrupt-cells = <2>;
 653                 };
 654
 655                 pcfg_pull_up: pcfg-pull-up {
 656                         bias-pull-up;
 657                 };
 658
 659                 pcfg_pull_down: pcfg-pull-down {
 660                         bias-pull-down;
 661                 };
 662
 663                 pcfg_pull_none: pcfg-pull-none {
 664                         bias-disable;
 665                 };
 666
 667                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 668                         drive-strength = <8>;
 669                 };
 670
 671                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 672                         drive-strength = <12>;
 673                 };
 674
 675                 pcfg_pull_none_smt: pcfg-pull-none-smt {
 676                         bias-disable;
 677                         input-schmitt-enable;
 678                 };
 679
 680                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 681                         bias-pull-up;
 682                         drive-strength = <8>;
 683                 };
 684
 685                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
 686                         drive-strength = <4>;
 687                 };
 688
 689                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
 690                         bias-pull-up;
 691                         drive-strength = <4>;
 692                 };
 693
 694                 pcfg_output_high: pcfg-output-high {
 695                         output-high;
 696                 };
 697
 698                 pcfg_output_low: pcfg-output-low {
 699                         output-low;
 700                 };
 701
 702                 pcfg_input_high: pcfg-input-high {
 703                         bias-pull-up;
 704                         input-enable;
 705                 };
 706
 707                 emmc {
 708                         emmc_bus8: emmc-bus8 {
 709                                 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
 710                                                 <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
 711                                                 <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
 712                                                 <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
 713                                                 <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
 714                                                 <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
 715                                                 <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
 716                                                 <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
 717                         };
 718
 719                         emmc_clk: emmc-clk {
 720                                 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
 721                         };
 722
 723                         emmc_cmd: emmc-cmd {
 724                                 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
 725                         };
 726                 };
 727
 728                 sfc {
 729                         sfc_bus4: sfc-bus4 {
 730                                 rockchip,pins =
 731                                         <2 RK_PA0 3 &pcfg_pull_none>,
 732                                         <2 RK_PA1 3 &pcfg_pull_none>,
 733                                         <2 RK_PA2 3 &pcfg_pull_none>,
 734                                         <2 RK_PA3 3 &pcfg_pull_none>;
 735                         };
 736
 737                         sfc_bus2: sfc-bus2 {
 738                                 rockchip,pins =
 739                                         <2 RK_PA0 3 &pcfg_pull_none>,
 740                                         <2 RK_PA1 3 &pcfg_pull_none>;
 741                         };
 742
 743                         sfc_cs0: sfc-cs0 {
 744                                 rockchip,pins =
 745                                         <2 RK_PB4 3 &pcfg_pull_none>;
 746                         };
 747
 748                         sfc_clk: sfc-clk {
 749                                 rockchip,pins =
 750                                         <2 RK_PB7 2 &pcfg_pull_none>;
 751                         };
 752                 };
 753
 754                 gmac {
 755                         rmii_pins: rmii-pins {
 756                                 rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
 757                                                 <1 RK_PC3 2 &pcfg_pull_none>,
 758                                                 <1 RK_PC4 2 &pcfg_pull_none>,
 759                                                 <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
 760                                                 <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
 761                                                 <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
 762                                                 <1 RK_PB5 3 &pcfg_pull_none>,
 763                                                 <1 RK_PB6 3 &pcfg_pull_none>,
 764                                                 <1 RK_PB7 3 &pcfg_pull_none>,
 765                                                 <1 RK_PC2 3 &pcfg_pull_none>;
 766                         };
 767                 };
 768
 769                 i2c0 {
 770                         i2c0_xfer: i2c0-xfer {
 771                                 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
 772                                                 <0 RK_PB2 1 &pcfg_pull_none_smt>;
 773                         };
 774                 };
 775
 776                 i2c1 {
 777                         i2c1_xfer: i2c1-xfer {
 778                                 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
 779                                                 <2 RK_PD4 1 &pcfg_pull_up>;
 780                         };
 781                 };
 782
 783                 i2c2m1 {
 784                         i2c2m1_xfer: i2c2m1-xfer {
 785                                 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
 786                                                 <0 RK_PC6 3 &pcfg_pull_none>;
 787                         };
 788
 789                         i2c2m1_pins: i2c2m1-pins {
 790                                 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
 791                                                 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
 792                         };
 793                 };
 794
 795                 i2c2m05v {
 796                         i2c2m05v_xfer: i2c2m05v-xfer {
 797                                 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
 798                                                 <1 RK_PD4 2 &pcfg_pull_none>;
 799                         };
 800
 801                         i2c2m05v_pins: i2c2m05v-pins {
 802                                 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
 803                                                 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
 804                         };
 805                 };
 806
 807                 i2c3 {
 808                         i2c3_xfer: i2c3-xfer {
 809                                 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
 810                                                 <0 RK_PC4 2 &pcfg_pull_none>;
 811                         };
 812                 };
 813
 814                 pwm0 {
 815                         pwm0_pin: pwm0-pin {
 816                                 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
 817                         };
 818                 };
 819
 820                 pwm1 {
 821                         pwm1_pin: pwm1-pin {
 822                                 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
 823                         };
 824                 };
 825
 826                 pwm2 {
 827                         pwm2_pin: pwm2-pin {
 828                                 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
 829                         };
 830                 };
 831
 832                 pwm3 {
 833                         pwm3_pin: pwm3-pin {
 834                                 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
 835                         };
 836                 };
 837
 838                 pwm4 {
 839                         pwm4_pin: pwm4-pin {
 840                                 rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
 841                         };
 842                 };
 843
 844                 pwm5 {
 845                         pwm5_pin: pwm5-pin {
 846                                 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
 847                         };
 848                 };
 849
 850                 pwm6 {
 851                         pwm6_pin: pwm6-pin {
 852                                 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
 853                         };
 854                 };
 855
 856                 pwm7 {
 857                         pwm7_pin: pwm7-pin {
 858                                 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
 859                         };
 860                 };
 861
 862                 sdmmc {
 863                         sdmmc_clk: sdmmc-clk {
 864                                 rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
 865                         };
 866
 867                         sdmmc_cmd: sdmmc-cmd {
 868                                 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
 869                         };
 870
 871                         sdmmc_cd: sdmmc-cd {
 872                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
 873                         };
 874
 875                         sdmmc_bus1: sdmmc-bus1 {
 876                                 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
 877                         };
 878
 879                         sdmmc_bus4: sdmmc-bus4 {
 880                                 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
 881                                                 <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
 882                                                 <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
 883                                                 <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
 884                         };
 885                 };
 886
 887                 spim0 {
 888                         spim0_clk: spim0-clk {
 889                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
 890                         };
 891
 892                         spim0_cs0: spim0-cs0 {
 893                                 rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
 894                         };
 895
 896                         spim0_tx: spim0-tx {
 897                                 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
 898                         };
 899
 900                         spim0_rx: spim0-rx {
 901                                 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
 902                         };
 903                 };
 904
 905                 spim1 {
 906                         spim1_clk: spim1-clk {
 907                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
 908                         };
 909
 910                         spim1_cs0: spim1-cs0 {
 911                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
 912                         };
 913
 914                         spim1_rx: spim1-rx {
 915                                 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
 916                         };
 917
 918                         spim1_tx: spim1-tx {
 919                                 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
 920                         };
 921                 };
 922
 923                 tsadc {
 924                         otp_out: otp-out {
 925                                 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
 926                         };
 927
 928                         otp_pin: otp-pin {
 929                                 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
 930                         };
 931                 };
 932
 933                 uart0 {
 934                         uart0_xfer: uart0-xfer {
 935                                 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
 936                                                 <3 RK_PA5 1 &pcfg_pull_none>;
 937                         };
 938
 939                         uart0_cts: uart0-cts {
 940                                 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
 941                         };
 942
 943                         uart0_rts: uart0-rts {
 944                                 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
 945                         };
 946
 947                         uart0_rts_pin: uart0-rts-pin {
 948                                 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 949                         };
 950                 };
 951
 952                 uart1 {
 953                         uart1_xfer: uart1-xfer {
 954                                 rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
 955                                                 <1 RK_PD2 1 &pcfg_pull_none>;
 956                         };
 957
 958                         uart1_cts: uart1-cts {
 959                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
 960                         };
 961
 962                         uart1_rts: uart1-rts {
 963                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
 964                         };
 965                 };
 966
 967                 uart2m0 {
 968                         uart2m0_xfer: uart2m0-xfer {
 969                                 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
 970                                                 <2 RK_PD1 1 &pcfg_pull_none>;
 971                         };
 972                 };
 973
 974                 uart2m1 {
 975                         uart2m1_xfer: uart2m1-xfer {
 976                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
 977                                                 <3 RK_PC2 2 &pcfg_pull_none>;
 978                         };
 979                 };
 980
 981                 uart2_5v {
 982                         uart2_5v_cts: uart2_5v-cts {
 983                                 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
 984                         };
 985
 986                         uart2_5v_rts: uart2_5v-rts {
 987                                 rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;
 988                         };
 989                 };
 990         };
 991 };