arch/arm/boot/dts/r8a7779.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the R-Car H1 (R8A77790) SoC
   4  *
   5  * Copyright (C) 2013 Renesas Solutions Corp.
   6  * Copyright (C) 2013 Simon Horman
   7  */
   8
   9 #include <dt-bindings/clock/r8a7779-clock.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/power/r8a7779-sysc.h>
  13
  14 / {
  15         compatible = "renesas,r8a7779";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a9";
  27                         reg = <0>;
  28                         clock-frequency = <1000000000>;
  29                         clocks = <&cpg_clocks R8A7779_CLK_Z>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <1>;
  35                         clock-frequency = <1000000000>;
  36                         clocks = <&cpg_clocks R8A7779_CLK_Z>;
  37                         power-domains = <&sysc R8A7779_PD_ARM1>;
  38                 };
  39                 cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         reg = <2>;
  43                         clock-frequency = <1000000000>;
  44                         clocks = <&cpg_clocks R8A7779_CLK_Z>;
  45                         power-domains = <&sysc R8A7779_PD_ARM2>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a9";
  50                         reg = <3>;
  51                         clock-frequency = <1000000000>;
  52                         clocks = <&cpg_clocks R8A7779_CLK_Z>;
  53                         power-domains = <&sysc R8A7779_PD_ARM3>;
  54                 };
  55         };
  56
  57         aliases {
  58                 spi0 = &hspi0;
  59                 spi1 = &hspi1;
  60                 spi2 = &hspi2;
  61         };
  62
  63         gic: interrupt-controller@f0001000 {
  64                 compatible = "arm,cortex-a9-gic";
  65                 #interrupt-cells = <3>;
  66                 interrupt-controller;
  67                 reg = <0xf0001000 0x1000>,
  68                       <0xf0000100 0x100>;
  69         };
  70
  71         timer@f0000200 {
  72                 compatible = "arm,cortex-a9-global-timer";
  73                 reg = <0xf0000200 0x100>;
  74                 interrupts = <GIC_PPI 11
  75                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
  76                 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
  77         };
  78
  79         timer@f0000600 {
  80                 compatible = "arm,cortex-a9-twd-timer";
  81                 reg = <0xf0000600 0x20>;
  82                 interrupts = <GIC_PPI 13
  83                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
  84                 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
  85         };
  86
  87         gpio0: gpio@ffc40000 {
  88                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
  89                 reg = <0xffc40000 0x2c>;
  90                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
  91                 #gpio-cells = <2>;
  92                 gpio-controller;
  93                 gpio-ranges = <&pfc 0 0 32>;
  94                 #interrupt-cells = <2>;
  95                 interrupt-controller;
  96         };
  97
  98         gpio1: gpio@ffc41000 {
  99                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
 100                 reg = <0xffc41000 0x2c>;
 101                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 102                 #gpio-cells = <2>;
 103                 gpio-controller;
 104                 gpio-ranges = <&pfc 0 32 32>;
 105                 #interrupt-cells = <2>;
 106                 interrupt-controller;
 107         };
 108
 109         gpio2: gpio@ffc42000 {
 110                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
 111                 reg = <0xffc42000 0x2c>;
 112                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 113                 #gpio-cells = <2>;
 114                 gpio-controller;
 115                 gpio-ranges = <&pfc 0 64 32>;
 116                 #interrupt-cells = <2>;
 117                 interrupt-controller;
 118         };
 119
 120         gpio3: gpio@ffc43000 {
 121                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
 122                 reg = <0xffc43000 0x2c>;
 123                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 124                 #gpio-cells = <2>;
 125                 gpio-controller;
 126                 gpio-ranges = <&pfc 0 96 32>;
 127                 #interrupt-cells = <2>;
 128                 interrupt-controller;
 129         };
 130
 131         gpio4: gpio@ffc44000 {
 132                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
 133                 reg = <0xffc44000 0x2c>;
 134                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 135                 #gpio-cells = <2>;
 136                 gpio-controller;
 137                 gpio-ranges = <&pfc 0 128 32>;
 138                 #interrupt-cells = <2>;
 139                 interrupt-controller;
 140         };
 141
 142         gpio5: gpio@ffc45000 {
 143                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
 144                 reg = <0xffc45000 0x2c>;
 145                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 146                 #gpio-cells = <2>;
 147                 gpio-controller;
 148                 gpio-ranges = <&pfc 0 160 32>;
 149                 #interrupt-cells = <2>;
 150                 interrupt-controller;
 151         };
 152
 153         gpio6: gpio@ffc46000 {
 154                 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
 155                 reg = <0xffc46000 0x2c>;
 156                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 157                 #gpio-cells = <2>;
 158                 gpio-controller;
 159                 gpio-ranges = <&pfc 0 192 9>;
 160                 #interrupt-cells = <2>;
 161                 interrupt-controller;
 162         };
 163
 164         irqpin0: interrupt-controller@fe78001c {
 165                 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
 166                 #interrupt-cells = <2>;
 167                 status = "disabled";
 168                 interrupt-controller;
 169                 reg = <0xfe78001c 4>,
 170                         <0xfe780010 4>,
 171                         <0xfe780024 4>,
 172                         <0xfe780044 4>,
 173                         <0xfe780064 4>,
 174                         <0xfe780000 4>;
 175                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 179                 sense-bitfield-width = <2>;
 180         };
 181
 182         i2c0: i2c@ffc70000 {
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 186                 reg = <0xffc70000 0x1000>;
 187                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 189                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 190                 status = "disabled";
 191         };
 192
 193         i2c1: i2c@ffc71000 {
 194                 #address-cells = <1>;
 195                 #size-cells = <0>;
 196                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 197                 reg = <0xffc71000 0x1000>;
 198                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 200                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 201                 i2c-scl-internal-delay-ns = <5>;
 202                 status = "disabled";
 203         };
 204
 205         i2c2: i2c@ffc72000 {
 206                 #address-cells = <1>;
 207                 #size-cells = <0>;
 208                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 209                 reg = <0xffc72000 0x1000>;
 210                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 211                 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 212                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 213                 i2c-scl-internal-delay-ns = <5>;
 214                 status = "disabled";
 215         };
 216
 217         i2c3: i2c@ffc73000 {
 218                 #address-cells = <1>;
 219                 #size-cells = <0>;
 220                 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
 221                 reg = <0xffc73000 0x1000>;
 222                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 223                 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 224                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 225                 i2c-scl-internal-delay-ns = <5>;
 226                 status = "disabled";
 227         };
 228
 229         scif0: serial@ffe40000 {
 230                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 231                              "renesas,scif";
 232                 reg = <0xffe40000 0x100>;
 233                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
 235                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 236                 clock-names = "fck", "brg_int", "scif_clk";
 237                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 238                 status = "disabled";
 239         };
 240
 241         scif1: serial@ffe41000 {
 242                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 243                              "renesas,scif";
 244                 reg = <0xffe41000 0x100>;
 245                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
 247                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 248                 clock-names = "fck", "brg_int", "scif_clk";
 249                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 250                 status = "disabled";
 251         };
 252
 253         scif2: serial@ffe42000 {
 254                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 255                              "renesas,scif";
 256                 reg = <0xffe42000 0x100>;
 257                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
 259                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 260                 clock-names = "fck", "brg_int", "scif_clk";
 261                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 262                 status = "disabled";
 263         };
 264
 265         scif3: serial@ffe43000 {
 266                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 267                              "renesas,scif";
 268                 reg = <0xffe43000 0x100>;
 269                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
 271                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 272                 clock-names = "fck", "brg_int", "scif_clk";
 273                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 274                 status = "disabled";
 275         };
 276
 277         scif4: serial@ffe44000 {
 278                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 279                              "renesas,scif";
 280                 reg = <0xffe44000 0x100>;
 281                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 282                 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
 283                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 284                 clock-names = "fck", "brg_int", "scif_clk";
 285                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 286                 status = "disabled";
 287         };
 288
 289         scif5: serial@ffe45000 {
 290                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 291                              "renesas,scif";
 292                 reg = <0xffe45000 0x100>;
 293                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 294                 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
 295                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 296                 clock-names = "fck", "brg_int", "scif_clk";
 297                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 298                 status = "disabled";
 299         };
 300
 301         hscif0: serial@ffe48000 {
 302                 compatible = "renesas,hscif-r8a7779",
 303                              "renesas,rcar-gen1-hscif", "renesas,hscif";
 304                 reg = <0xffe48000 96>;
 305                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>,
 307                          <&cpg_clocks R8A7779_CLK_S>,
 308                          <&scif_clk>;
 309                 clock-names = "fck", "brg_int", "scif_clk";
 310                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 311                 status = "disabled";
 312         };
 313
 314         hscif1: serial@ffe49000 {
 315                 compatible = "renesas,hscif-r8a7779",
 316                              "renesas,rcar-gen1-hscif", "renesas,hscif";
 317                 reg = <0xffe49000 96>;
 318                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>,
 320                          <&cpg_clocks R8A7779_CLK_S>,
 321                          <&scif_clk>;
 322                 clock-names = "fck", "brg_int", "scif_clk";
 323                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 324                 status = "disabled";
 325         };
 326
 327         pfc: pinctrl@fffc0000 {
 328                 compatible = "renesas,pfc-r8a7779";
 329                 reg = <0xfffc0000 0x23c>;
 330         };
 331
 332         thermal@ffc48000 {
 333                 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
 334                 reg = <0xffc48000 0x38>;
 335         };
 336
 337         tmu0: timer@ffd80000 {
 338                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 339                 reg = <0xffd80000 0x30>;
 340                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 341                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 342                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
 344                 clock-names = "fck";
 345                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 346
 347                 #renesas,channels = <3>;
 348
 349                 status = "disabled";
 350         };
 351
 352         tmu1: timer@ffd81000 {
 353                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 354                 reg = <0xffd81000 0x30>;
 355                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 356                              <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 357                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 358                 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
 359                 clock-names = "fck";
 360                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 361
 362                 #renesas,channels = <3>;
 363
 364                 status = "disabled";
 365         };
 366
 367         tmu2: timer@ffd82000 {
 368                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 369                 reg = <0xffd82000 0x30>;
 370                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 371                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 372                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 373                 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
 374                 clock-names = "fck";
 375                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 376
 377                 #renesas,channels = <3>;
 378
 379                 status = "disabled";
 380         };
 381
 382         sata: sata@fc600000 {
 383                 compatible = "renesas,sata-r8a7779";
 384                 reg = <0xfc600000 0x200000>;
 385                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 386                 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 387                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 388                 status = "disabled";
 389         };
 390
 391         sdhi0: mmc@ffe4c000 {
 392                 compatible = "renesas,sdhi-r8a7779",
 393                              "renesas,rcar-gen1-sdhi";
 394                 reg = <0xffe4c000 0x100>;
 395                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 397                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 398                 status = "disabled";
 399         };
 400
 401         sdhi1: mmc@ffe4d000 {
 402                 compatible = "renesas,sdhi-r8a7779",
 403                              "renesas,rcar-gen1-sdhi";
 404                 reg = <0xffe4d000 0x100>;
 405                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 407                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 408                 status = "disabled";
 409         };
 410
 411         sdhi2: mmc@ffe4e000 {
 412                 compatible = "renesas,sdhi-r8a7779",
 413                              "renesas,rcar-gen1-sdhi";
 414                 reg = <0xffe4e000 0x100>;
 415                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 417                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 418                 status = "disabled";
 419         };
 420
 421         sdhi3: mmc@ffe4f000 {
 422                 compatible = "renesas,sdhi-r8a7779",
 423                              "renesas,rcar-gen1-sdhi";
 424                 reg = <0xffe4f000 0x100>;
 425                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 427                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 428                 status = "disabled";
 429         };
 430
 431         hspi0: spi@fffc7000 {
 432                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 433                 reg = <0xfffc7000 0x18>;
 434                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 435                 #address-cells = <1>;
 436                 #size-cells = <0>;
 437                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 438                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 439                 status = "disabled";
 440         };
 441
 442         hspi1: spi@fffc8000 {
 443                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 444                 reg = <0xfffc8000 0x18>;
 445                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 446                 #address-cells = <1>;
 447                 #size-cells = <0>;
 448                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 449                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 450                 status = "disabled";
 451         };
 452
 453         hspi2: spi@fffc6000 {
 454                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 455                 reg = <0xfffc6000 0x18>;
 456                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 460                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 461                 status = "disabled";
 462         };
 463
 464         du: display@fff80000 {
 465                 compatible = "renesas,du-r8a7779";
 466                 reg = <0xfff80000 0x40000>;
 467                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 468                 clocks = <&mstp1_clks R8A7779_CLK_DU>;
 469                 clock-names = "du.0";
 470                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 471                 status = "disabled";
 472
 473                 ports {
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476
 477                         port@0 {
 478                                 reg = <0>;
 479                                 du_out_rgb0: endpoint {
 480                                 };
 481                         };
 482                         port@1 {
 483                                 reg = <1>;
 484                                 du_out_rgb1: endpoint {
 485                                 };
 486                         };
 487                 };
 488         };
 489
 490         clocks {
 491                 #address-cells = <1>;
 492                 #size-cells = <1>;
 493                 ranges;
 494
 495                 /* External root clock */
 496                 extal_clk: extal {
 497                         compatible = "fixed-clock";
 498                         #clock-cells = <0>;
 499                         /* This value must be overriden by the board. */
 500                         clock-frequency = <0>;
 501                 };
 502
 503                 /* External SCIF clock */
 504                 scif_clk: scif {
 505                         compatible = "fixed-clock";
 506                         #clock-cells = <0>;
 507                         /* This value must be overridden by the board. */
 508                         clock-frequency = <0>;
 509                 };
 510
 511                 /* Special CPG clocks */
 512                 cpg_clocks: clocks@ffc80000 {
 513                         compatible = "renesas,r8a7779-cpg-clocks";
 514                         reg = <0xffc80000 0x30>;
 515                         clocks = <&extal_clk>;
 516                         #clock-cells = <1>;
 517                         clock-output-names = "plla", "z", "zs", "s",
 518                                              "s1", "p", "b", "out";
 519                         #power-domain-cells = <0>;
 520                 };
 521
 522                 /* Fixed factor clocks */
 523                 i_clk: i {
 524                         compatible = "fixed-factor-clock";
 525                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 526                         #clock-cells = <0>;
 527                         clock-div = <2>;
 528                         clock-mult = <1>;
 529                 };
 530                 s3_clk: s3 {
 531                         compatible = "fixed-factor-clock";
 532                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 533                         #clock-cells = <0>;
 534                         clock-div = <8>;
 535                         clock-mult = <1>;
 536                 };
 537                 s4_clk: s4 {
 538                         compatible = "fixed-factor-clock";
 539                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 540                         #clock-cells = <0>;
 541                         clock-div = <16>;
 542                         clock-mult = <1>;
 543                 };
 544                 g_clk: g {
 545                         compatible = "fixed-factor-clock";
 546                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 547                         #clock-cells = <0>;
 548                         clock-div = <24>;
 549                         clock-mult = <1>;
 550                 };
 551
 552                 /* Gate clocks */
 553                 mstp0_clks: clocks@ffc80030 {
 554                         compatible = "renesas,r8a7779-mstp-clocks",
 555                                      "renesas,cpg-mstp-clocks";
 556                         reg = <0xffc80030 4>;
 557                         clocks = <&cpg_clocks R8A7779_CLK_S>,
 558                                  <&cpg_clocks R8A7779_CLK_P>,
 559                                  <&cpg_clocks R8A7779_CLK_P>,
 560                                  <&cpg_clocks R8A7779_CLK_P>,
 561                                  <&cpg_clocks R8A7779_CLK_S>,
 562                                  <&cpg_clocks R8A7779_CLK_S>,
 563                                  <&cpg_clocks R8A7779_CLK_P>,
 564                                  <&cpg_clocks R8A7779_CLK_P>,
 565                                  <&cpg_clocks R8A7779_CLK_P>,
 566                                  <&cpg_clocks R8A7779_CLK_P>,
 567                                  <&cpg_clocks R8A7779_CLK_P>,
 568                                  <&cpg_clocks R8A7779_CLK_P>,
 569                                  <&cpg_clocks R8A7779_CLK_P>,
 570                                  <&cpg_clocks R8A7779_CLK_P>,
 571                                  <&cpg_clocks R8A7779_CLK_P>,
 572                                  <&cpg_clocks R8A7779_CLK_P>;
 573                         #clock-cells = <1>;
 574                         clock-indices = <
 575                                 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
 576                                 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
 577                                 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
 578                                 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
 579                                 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
 580                                 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
 581                                 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
 582                                 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
 583                         >;
 584                         clock-output-names =
 585                                 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
 586                                 "hscif0", "scif5", "scif4", "scif3", "scif2",
 587                                 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
 588                                 "i2c0";
 589                 };
 590                 mstp1_clks: clocks@ffc80034 {
 591                         compatible = "renesas,r8a7779-mstp-clocks",
 592                                      "renesas,cpg-mstp-clocks";
 593                         reg = <0xffc80034 4>, <0xffc80044 4>;
 594                         clocks = <&cpg_clocks R8A7779_CLK_P>,
 595                                  <&cpg_clocks R8A7779_CLK_P>,
 596                                  <&cpg_clocks R8A7779_CLK_S>,
 597                                  <&cpg_clocks R8A7779_CLK_S>,
 598                                  <&cpg_clocks R8A7779_CLK_S>,
 599                                  <&cpg_clocks R8A7779_CLK_S>,
 600                                  <&cpg_clocks R8A7779_CLK_P>,
 601                                  <&cpg_clocks R8A7779_CLK_P>,
 602                                  <&cpg_clocks R8A7779_CLK_P>,
 603                                  <&cpg_clocks R8A7779_CLK_S>;
 604                         #clock-cells = <1>;
 605                         clock-indices = <
 606                                 R8A7779_CLK_USB01 R8A7779_CLK_USB2
 607                                 R8A7779_CLK_DU R8A7779_CLK_VIN2
 608                                 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
 609                                 R8A7779_CLK_ETHER R8A7779_CLK_SATA
 610                                 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
 611                         >;
 612                         clock-output-names =
 613                                 "usb01", "usb2",
 614                                 "du", "vin2",
 615                                 "vin1", "vin0",
 616                                 "ether", "sata",
 617                                 "pcie", "vin3";
 618                 };
 619                 mstp3_clks: clocks@ffc8003c {
 620                         compatible = "renesas,r8a7779-mstp-clocks",
 621                                      "renesas,cpg-mstp-clocks";
 622                         reg = <0xffc8003c 4>;
 623                         clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
 624                                  <&s4_clk>, <&s4_clk>;
 625                         #clock-cells = <1>;
 626                         clock-indices = <
 627                                 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
 628                                 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
 629                                 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
 630                         >;
 631                         clock-output-names =
 632                                 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
 633                                 "mmc1", "mmc0";
 634                 };
 635         };
 636
 637         prr: chipid@ff000044 {
 638                 compatible = "renesas,prr";
 639                 reg = <0xff000044 4>;
 640         };
 641
 642         rst: reset-controller@ffcc0000 {
 643                 compatible = "renesas,r8a7779-reset-wdt";
 644                 reg = <0xffcc0000 0x48>;
 645         };
 646
 647         sysc: system-controller@ffd85000 {
 648                 compatible = "renesas,r8a7779-sysc";
 649                 reg = <0xffd85000 0x0200>;
 650                 #power-domain-cells = <1>;
 651         };
 652 };