arch/arm/boot/dts/r8a7778.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the R-Car M1A (R8A77781) SoC
   4  *
   5  * Copyright (C) 2013  Renesas Solutions Corp.
   6  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   7  *
   8  * based on r8a7779
   9  *
  10  * Copyright (C) 2013 Renesas Solutions Corp.
  11  * Copyright (C) 2013 Simon Horman
  12  */
  13
  14 #include <dt-bindings/clock/r8a7778-clock.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17
  18 / {
  19         compatible = "renesas,r8a7778";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a9";
  31                         reg = <0>;
  32                         clock-frequency = <800000000>;
  33                         clocks = <&z_clk>;
  34                 };
  35         };
  36
  37         aliases {
  38                 spi0 = &hspi0;
  39                 spi1 = &hspi1;
  40                 spi2 = &hspi2;
  41         };
  42
  43         bsc: bus@1c000000 {
  44                 compatible = "simple-bus";
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 ranges = <0 0 0x1c000000>;
  48         };
  49
  50         ether: ethernet@fde00000 {
  51                 compatible = "renesas,ether-r8a7778",
  52                              "renesas,rcar-gen1-ether";
  53                 reg = <0xfde00000 0x400>;
  54                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  55                 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
  56                 power-domains = <&cpg_clocks>;
  57                 phy-mode = "rmii";
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60                 status = "disabled";
  61         };
  62
  63         gic: interrupt-controller@fe438000 {
  64                 compatible = "arm,pl390";
  65                 #interrupt-cells = <3>;
  66                 interrupt-controller;
  67                 reg = <0xfe438000 0x1000>,
  68                       <0xfe430000 0x100>;
  69         };
  70
  71         /* irqpin: IRQ0 - IRQ3 */
  72         irqpin: interrupt-controller@fe78001c {
  73                 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
  74                 #interrupt-cells = <2>;
  75                 interrupt-controller;
  76                 status = "disabled"; /* default off */
  77                 reg =   <0xfe78001c 4>,
  78                         <0xfe780010 4>,
  79                         <0xfe780024 4>,
  80                         <0xfe780044 4>,
  81                         <0xfe780064 4>,
  82                         <0xfe780000 4>;
  83                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
  86                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  87                 sense-bitfield-width = <2>;
  88         };
  89
  90         gpio0: gpio@ffc40000 {
  91                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
  92                 reg = <0xffc40000 0x2c>;
  93                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  94                 #gpio-cells = <2>;
  95                 gpio-controller;
  96                 gpio-ranges = <&pfc 0 0 32>;
  97                 #interrupt-cells = <2>;
  98                 interrupt-controller;
  99         };
 100
 101         gpio1: gpio@ffc41000 {
 102                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 103                 reg = <0xffc41000 0x2c>;
 104                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 105                 #gpio-cells = <2>;
 106                 gpio-controller;
 107                 gpio-ranges = <&pfc 0 32 32>;
 108                 #interrupt-cells = <2>;
 109                 interrupt-controller;
 110         };
 111
 112         gpio2: gpio@ffc42000 {
 113                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 114                 reg = <0xffc42000 0x2c>;
 115                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 116                 #gpio-cells = <2>;
 117                 gpio-controller;
 118                 gpio-ranges = <&pfc 0 64 32>;
 119                 #interrupt-cells = <2>;
 120                 interrupt-controller;
 121         };
 122
 123         gpio3: gpio@ffc43000 {
 124                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 125                 reg = <0xffc43000 0x2c>;
 126                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 127                 #gpio-cells = <2>;
 128                 gpio-controller;
 129                 gpio-ranges = <&pfc 0 96 32>;
 130                 #interrupt-cells = <2>;
 131                 interrupt-controller;
 132         };
 133
 134         gpio4: gpio@ffc44000 {
 135                 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
 136                 reg = <0xffc44000 0x2c>;
 137                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 138                 #gpio-cells = <2>;
 139                 gpio-controller;
 140                 gpio-ranges = <&pfc 0 128 27>;
 141                 #interrupt-cells = <2>;
 142                 interrupt-controller;
 143         };
 144
 145         pfc: pinctrl@fffc0000 {
 146                 compatible = "renesas,pfc-r8a7778";
 147                 reg = <0xfffc0000 0x118>;
 148         };
 149
 150         i2c0: i2c@ffc70000 {
 151                 #address-cells = <1>;
 152                 #size-cells = <0>;
 153                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 154                 reg = <0xffc70000 0x1000>;
 155                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
 157                 power-domains = <&cpg_clocks>;
 158                 status = "disabled";
 159         };
 160
 161         i2c1: i2c@ffc71000 {
 162                 #address-cells = <1>;
 163                 #size-cells = <0>;
 164                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 165                 reg = <0xffc71000 0x1000>;
 166                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 167                 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
 168                 power-domains = <&cpg_clocks>;
 169                 i2c-scl-internal-delay-ns = <5>;
 170                 status = "disabled";
 171         };
 172
 173         i2c2: i2c@ffc72000 {
 174                 #address-cells = <1>;
 175                 #size-cells = <0>;
 176                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 177                 reg = <0xffc72000 0x1000>;
 178                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 179                 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
 180                 power-domains = <&cpg_clocks>;
 181                 i2c-scl-internal-delay-ns = <5>;
 182                 status = "disabled";
 183         };
 184
 185         i2c3: i2c@ffc73000 {
 186                 #address-cells = <1>;
 187                 #size-cells = <0>;
 188                 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
 189                 reg = <0xffc73000 0x1000>;
 190                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 191                 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
 192                 power-domains = <&cpg_clocks>;
 193                 i2c-scl-internal-delay-ns = <5>;
 194                 status = "disabled";
 195         };
 196
 197         tmu0: timer@ffd80000 {
 198                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 199                 reg = <0xffd80000 0x30>;
 200                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 201                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 202                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
 204                 clock-names = "fck";
 205                 power-domains = <&cpg_clocks>;
 206
 207                 #renesas,channels = <3>;
 208
 209                 status = "disabled";
 210         };
 211
 212         tmu1: timer@ffd81000 {
 213                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 214                 reg = <0xffd81000 0x30>;
 215                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
 219                 clock-names = "fck";
 220                 power-domains = <&cpg_clocks>;
 221
 222                 #renesas,channels = <3>;
 223
 224                 status = "disabled";
 225         };
 226
 227         tmu2: timer@ffd82000 {
 228                 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 229                 reg = <0xffd82000 0x30>;
 230                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 231                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 232                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
 234                 clock-names = "fck";
 235                 power-domains = <&cpg_clocks>;
 236
 237                 #renesas,channels = <3>;
 238
 239                 status = "disabled";
 240         };
 241
 242         rcar_sound: sound@ffd90000 {
 243                 /*
 244                  * #sound-dai-cells is required
 245                  *
 246                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
 247                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
 248                  */
 249                 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
 250                 reg =   <0xffd90000 0x1000>,    /* SRU */
 251                         <0xffd91000 0x240>,     /* SSI */
 252                         <0xfffe0000 0x24>;      /* ADG */
 253                 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
 254                         <&mstp3_clks R8A7778_CLK_SSI7>,
 255                         <&mstp3_clks R8A7778_CLK_SSI6>,
 256                         <&mstp3_clks R8A7778_CLK_SSI5>,
 257                         <&mstp3_clks R8A7778_CLK_SSI4>,
 258                         <&mstp0_clks R8A7778_CLK_SSI3>,
 259                         <&mstp0_clks R8A7778_CLK_SSI2>,
 260                         <&mstp0_clks R8A7778_CLK_SSI1>,
 261                         <&mstp0_clks R8A7778_CLK_SSI0>,
 262                         <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
 263                         <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
 264                         <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
 265                         <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
 266                         <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
 267                         <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
 268                         <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
 269                         <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
 270                         <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
 271                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
 272                         <&cpg_clocks R8A7778_CLK_S1>;
 273                 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
 274                         "ssi.3", "ssi.2", "ssi.1", "ssi.0",
 275                         "src.8", "src.7", "src.6", "src.5", "src.4",
 276                         "src.3", "src.2", "src.1", "src.0",
 277                         "clk_a", "clk_b", "clk_c", "clk_i";
 278
 279                 status = "disabled";
 280
 281                 rcar_sound,src {
 282                         src3: src-3 { };
 283                         src4: src-4 { };
 284                         src5: src-5 { };
 285                         src6: src-6 { };
 286                         src7: src-7 { };
 287                         src8: src-8 { };
 288                         src9: src-9 { };
 289                 };
 290
 291                 rcar_sound,ssi {
 292                         ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 293                         ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
 294                         ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 295                         ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 296                         ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 297                         ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 298                         ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 299                 };
 300         };
 301
 302         scif0: serial@ffe40000 {
 303                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 304                              "renesas,scif";
 305                 reg = <0xffe40000 0x100>;
 306                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 307                 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
 308                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 309                 clock-names = "fck", "brg_int", "scif_clk";
 310                 power-domains = <&cpg_clocks>;
 311                 status = "disabled";
 312         };
 313
 314         scif1: serial@ffe41000 {
 315                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 316                              "renesas,scif";
 317                 reg = <0xffe41000 0x100>;
 318                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
 320                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 321                 clock-names = "fck", "brg_int", "scif_clk";
 322                 power-domains = <&cpg_clocks>;
 323                 status = "disabled";
 324         };
 325
 326         scif2: serial@ffe42000 {
 327                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 328                              "renesas,scif";
 329                 reg = <0xffe42000 0x100>;
 330                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 331                 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
 332                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 333                 clock-names = "fck", "brg_int", "scif_clk";
 334                 power-domains = <&cpg_clocks>;
 335                 status = "disabled";
 336         };
 337
 338         scif3: serial@ffe43000 {
 339                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 340                              "renesas,scif";
 341                 reg = <0xffe43000 0x100>;
 342                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
 344                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 345                 clock-names = "fck", "brg_int", "scif_clk";
 346                 power-domains = <&cpg_clocks>;
 347                 status = "disabled";
 348         };
 349
 350         scif4: serial@ffe44000 {
 351                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 352                              "renesas,scif";
 353                 reg = <0xffe44000 0x100>;
 354                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 355                 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
 356                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 357                 clock-names = "fck", "brg_int", "scif_clk";
 358                 power-domains = <&cpg_clocks>;
 359                 status = "disabled";
 360         };
 361
 362         scif5: serial@ffe45000 {
 363                 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
 364                              "renesas,scif";
 365                 reg = <0xffe45000 0x100>;
 366                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
 368                          <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
 369                 clock-names = "fck", "brg_int", "scif_clk";
 370                 power-domains = <&cpg_clocks>;
 371                 status = "disabled";
 372         };
 373
 374         hscif0: serial@ffe48000 {
 375                 compatible = "renesas,hscif-r8a7778",
 376                              "renesas,rcar-gen1-hscif", "renesas,hscif";
 377                 reg = <0xffe48000 96>;
 378                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 379                 clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
 380                          <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
 381                 clock-names = "fck", "brg_int", "scif_clk";
 382                 power-domains = <&cpg_clocks>;
 383                 status = "disabled";
 384         };
 385
 386         hscif1: serial@ffe49000 {
 387                 compatible = "renesas,hscif-r8a7778",
 388                              "renesas,rcar-gen1-hscif", "renesas,hscif";
 389                 reg = <0xffe49000 96>;
 390                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 391                 clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
 392                          <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
 393                 clock-names = "fck", "brg_int", "scif_clk";
 394                 power-domains = <&cpg_clocks>;
 395                 status = "disabled";
 396         };
 397
 398         mmcif: mmc@ffe4e000 {
 399                 compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
 400                 reg = <0xffe4e000 0x100>;
 401                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
 403                 power-domains = <&cpg_clocks>;
 404                 status = "disabled";
 405         };
 406
 407         sdhi0: mmc@ffe4c000 {
 408                 compatible = "renesas,sdhi-r8a7778",
 409                              "renesas,rcar-gen1-sdhi";
 410                 reg = <0xffe4c000 0x100>;
 411                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 412                 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
 413                 power-domains = <&cpg_clocks>;
 414                 status = "disabled";
 415         };
 416
 417         sdhi1: mmc@ffe4d000 {
 418                 compatible = "renesas,sdhi-r8a7778",
 419                              "renesas,rcar-gen1-sdhi";
 420                 reg = <0xffe4d000 0x100>;
 421                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 422                 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
 423                 power-domains = <&cpg_clocks>;
 424                 status = "disabled";
 425         };
 426
 427         sdhi2: mmc@ffe4f000 {
 428                 compatible = "renesas,sdhi-r8a7778",
 429                              "renesas,rcar-gen1-sdhi";
 430                 reg = <0xffe4f000 0x100>;
 431                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 432                 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
 433                 power-domains = <&cpg_clocks>;
 434                 status = "disabled";
 435         };
 436
 437         hspi0: spi@fffc7000 {
 438                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 439                 reg = <0xfffc7000 0x18>;
 440                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 441                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 442                 power-domains = <&cpg_clocks>;
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 status = "disabled";
 446         };
 447
 448         hspi1: spi@fffc8000 {
 449                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 450                 reg = <0xfffc8000 0x18>;
 451                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 452                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 453                 power-domains = <&cpg_clocks>;
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 status = "disabled";
 457         };
 458
 459         hspi2: spi@fffc6000 {
 460                 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 461                 reg = <0xfffc6000 0x18>;
 462                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 463                 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 464                 power-domains = <&cpg_clocks>;
 465                 #address-cells = <1>;
 466                 #size-cells = <0>;
 467                 status = "disabled";
 468         };
 469
 470         clocks {
 471                 #address-cells = <1>;
 472                 #size-cells = <1>;
 473                 ranges;
 474
 475                 /* External input clock */
 476                 extal_clk: extal {
 477                         compatible = "fixed-clock";
 478                         #clock-cells = <0>;
 479                         clock-frequency = <0>;
 480                 };
 481
 482                 /* External SCIF clock */
 483                 scif_clk: scif {
 484                         compatible = "fixed-clock";
 485                         #clock-cells = <0>;
 486                         /* This value must be overridden by the board. */
 487                         clock-frequency = <0>;
 488                 };
 489
 490                 /* Special CPG clocks */
 491                 cpg_clocks: cpg_clocks@ffc80000 {
 492                         compatible = "renesas,r8a7778-cpg-clocks";
 493                         reg = <0xffc80000 0x80>;
 494                         #clock-cells = <1>;
 495                         clocks = <&extal_clk>;
 496                         clock-output-names = "plla", "pllb", "b",
 497                                              "out", "p", "s", "s1";
 498                         #power-domain-cells = <0>;
 499                 };
 500
 501                 /* Audio clocks; frequencies are set by boards if applicable. */
 502                 audio_clk_a: audio_clk_a {
 503                         compatible = "fixed-clock";
 504                         #clock-cells = <0>;
 505                         clock-frequency = <0>;
 506                 };
 507                 audio_clk_b: audio_clk_b {
 508                         compatible = "fixed-clock";
 509                         #clock-cells = <0>;
 510                         clock-frequency = <0>;
 511                 };
 512                 audio_clk_c: audio_clk_c {
 513                         compatible = "fixed-clock";
 514                         #clock-cells = <0>;
 515                         clock-frequency = <0>;
 516                 };
 517
 518                 /* Fixed ratio clocks */
 519                 g_clk: g {
 520                         compatible = "fixed-factor-clock";
 521                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 522                         #clock-cells = <0>;
 523                         clock-div = <12>;
 524                         clock-mult = <1>;
 525                 };
 526                 i_clk: i {
 527                         compatible = "fixed-factor-clock";
 528                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 529                         #clock-cells = <0>;
 530                         clock-div = <1>;
 531                         clock-mult = <1>;
 532                 };
 533                 s3_clk: s3 {
 534                         compatible = "fixed-factor-clock";
 535                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 536                         #clock-cells = <0>;
 537                         clock-div = <4>;
 538                         clock-mult = <1>;
 539                 };
 540                 s4_clk: s4 {
 541                         compatible = "fixed-factor-clock";
 542                         clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 543                         #clock-cells = <0>;
 544                         clock-div = <8>;
 545                         clock-mult = <1>;
 546                 };
 547                 z_clk: z {
 548                         compatible = "fixed-factor-clock";
 549                         clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
 550                         #clock-cells = <0>;
 551                         clock-div = <1>;
 552                         clock-mult = <1>;
 553                 };
 554
 555                 /* Gate clocks */
 556                 mstp0_clks: mstp0_clks@ffc80030 {
 557                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 558                         reg = <0xffc80030 4>;
 559                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 560                                  <&cpg_clocks R8A7778_CLK_P>,
 561                                  <&cpg_clocks R8A7778_CLK_P>,
 562                                  <&cpg_clocks R8A7778_CLK_P>,
 563                                  <&cpg_clocks R8A7778_CLK_P>,
 564                                  <&cpg_clocks R8A7778_CLK_P>,
 565                                  <&cpg_clocks R8A7778_CLK_P>,
 566                                  <&cpg_clocks R8A7778_CLK_P>,
 567                                  <&cpg_clocks R8A7778_CLK_P>,
 568                                  <&cpg_clocks R8A7778_CLK_P>,
 569                                  <&cpg_clocks R8A7778_CLK_S>,
 570                                  <&cpg_clocks R8A7778_CLK_S>,
 571                                  <&cpg_clocks R8A7778_CLK_P>,
 572                                  <&cpg_clocks R8A7778_CLK_P>,
 573                                  <&cpg_clocks R8A7778_CLK_P>,
 574                                  <&cpg_clocks R8A7778_CLK_P>,
 575                                  <&cpg_clocks R8A7778_CLK_P>,
 576                                  <&cpg_clocks R8A7778_CLK_P>,
 577                                  <&cpg_clocks R8A7778_CLK_P>,
 578                                  <&cpg_clocks R8A7778_CLK_P>,
 579                                  <&cpg_clocks R8A7778_CLK_S>;
 580                         #clock-cells = <1>;
 581                         clock-indices = <
 582                                 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
 583                                 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
 584                                 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
 585                                 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
 586                                 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
 587                                 R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
 588                                 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
 589                                 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
 590                                 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
 591                                 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
 592                                 R8A7778_CLK_HSPI
 593                         >;
 594                         clock-output-names =
 595                                 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
 596                                 "scif1", "scif2", "scif3", "scif4", "scif5",
 597                                 "hscif0", "hscif1",
 598                                 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
 599                                 "ssi2", "ssi3", "sru", "hspi";
 600                 };
 601                 mstp1_clks: mstp1_clks@ffc80034 {
 602                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 603                         reg = <0xffc80034 4>, <0xffc80044 4>;
 604                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 605                                  <&cpg_clocks R8A7778_CLK_S>,
 606                                  <&cpg_clocks R8A7778_CLK_S>,
 607                                  <&cpg_clocks R8A7778_CLK_P>;
 608                         #clock-cells = <1>;
 609                         clock-indices = <
 610                                 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
 611                                 R8A7778_CLK_VIN1 R8A7778_CLK_USB
 612                         >;
 613                         clock-output-names =
 614                                 "ether", "vin0", "vin1", "usb";
 615                 };
 616                 mstp3_clks: mstp3_clks@ffc8003c {
 617                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 618                         reg = <0xffc8003c 4>;
 619                         clocks = <&s4_clk>,
 620                                  <&cpg_clocks R8A7778_CLK_P>,
 621                                  <&cpg_clocks R8A7778_CLK_P>,
 622                                  <&cpg_clocks R8A7778_CLK_P>,
 623                                  <&cpg_clocks R8A7778_CLK_P>,
 624                                  <&cpg_clocks R8A7778_CLK_P>,
 625                                  <&cpg_clocks R8A7778_CLK_P>,
 626                                  <&cpg_clocks R8A7778_CLK_P>,
 627                                  <&cpg_clocks R8A7778_CLK_P>;
 628                         #clock-cells = <1>;
 629                         clock-indices = <
 630                                 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
 631                                 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
 632                                 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
 633                                 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
 634                                 R8A7778_CLK_SSI8
 635                         >;
 636                         clock-output-names =
 637                                 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
 638                                 "ssi5", "ssi6", "ssi7", "ssi8";
 639                 };
 640                 mstp5_clks: mstp5_clks@ffc80054 {
 641                         compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
 642                         reg = <0xffc80054 4>;
 643                         clocks = <&cpg_clocks R8A7778_CLK_P>,
 644                                  <&cpg_clocks R8A7778_CLK_P>,
 645                                  <&cpg_clocks R8A7778_CLK_P>,
 646                                  <&cpg_clocks R8A7778_CLK_P>,
 647                                  <&cpg_clocks R8A7778_CLK_P>,
 648                                  <&cpg_clocks R8A7778_CLK_P>,
 649                                  <&cpg_clocks R8A7778_CLK_P>,
 650                                  <&cpg_clocks R8A7778_CLK_P>,
 651                                  <&cpg_clocks R8A7778_CLK_P>;
 652                         #clock-cells = <1>;
 653                         clock-indices = <
 654                                 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
 655                                 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
 656                                 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
 657                                 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
 658                                 R8A7778_CLK_SRU_SRC8
 659                         >;
 660                         clock-output-names =
 661                                 "sru-src0", "sru-src1", "sru-src2",
 662                                 "sru-src3", "sru-src4", "sru-src5",
 663                                 "sru-src6", "sru-src7", "sru-src8";
 664                 };
 665         };
 666
 667         rst: reset-controller@ffcc0000 {
 668                 compatible = "renesas,r8a7778-reset-wdt";
 669                 reg = <0xffcc0000 0x40>;
 670         };
 671 };