arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the iWave-RZ/G1H Qseven board development
   4  * platform with camera daughter board
   5  *
   6  * Copyright (C) 2020 Renesas Electronics Corp.
   7  */
   8
   9 /dts-v1/;
  10 #include "r8a7742-iwg21d-q7.dts"
  11
  12 / {
  13         model = "iWave Systems RZ/G1H Qseven development platform with camera add-on";
  14         compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
  15
  16         aliases {
  17                 serial0 = &scif0;
  18                 serial1 = &scif1;
  19                 serial3 = &scifb1;
  20                 serial5 = &hscif0;
  21                 ethernet1 = &ether;
  22         };
  23
  24         mclk_cam1: mclk-cam1 {
  25                 compatible = "fixed-clock";
  26                 #clock-cells = <0>;
  27                 clock-frequency = <26000000>;
  28         };
  29
  30         mclk_cam2: mclk-cam2 {
  31                 compatible = "fixed-clock";
  32                 #clock-cells = <0>;
  33                 clock-frequency = <26000000>;
  34         };
  35
  36         mclk_cam3: mclk-cam3 {
  37                 compatible = "fixed-clock";
  38                 #clock-cells = <0>;
  39                 clock-frequency = <26000000>;
  40         };
  41
  42         mclk_cam4: mclk-cam4 {
  43                 compatible = "fixed-clock";
  44                 #clock-cells = <0>;
  45                 clock-frequency = <26000000>;
  46         };
  47 };
  48
  49 &avb {
  50         /* Pins shared with VIN0, keep status disabled */
  51         status = "disabled";
  52 };
  53
  54 &can0 {
  55         pinctrl-0 = <&can0_pins>;
  56         pinctrl-names = "default";
  57         status = "okay";
  58 };
  59
  60 &ether {
  61         pinctrl-0 = <&ether_pins>;
  62         pinctrl-names = "default";
  63
  64         phy-handle = <&phy1>;
  65         renesas,ether-link-active-low;
  66         status = "okay";
  67
  68         phy1: ethernet-phy@1 {
  69                 reg = <1>;
  70                 micrel,led-mode = <1>;
  71         };
  72 };
  73
  74 &gpio0 {
  75         /* Disable hogging GP0_18 to output LOW */
  76         /delete-node/ qspi_en;
  77
  78         /* Hog GP0_18 to output HIGH to enable VIN2 */
  79         vin2_en {
  80                 gpio-hog;
  81                 gpios = <18 GPIO_ACTIVE_HIGH>;
  82                 output-high;
  83                 line-name = "VIN2_EN";
  84         };
  85 };
  86
  87 &hscif0 {
  88         pinctrl-0 = <&hscif0_pins>;
  89         pinctrl-names = "default";
  90         uart-has-rtscts;
  91         status = "okay";
  92 };
  93
  94 &i2c0 {
  95         ov5640@3c {
  96                 compatible = "ovti,ov5640";
  97                 reg = <0x3c>;
  98                 clocks = <&mclk_cam1>;
  99                 clock-names = "xclk";
 100
 101                 port {
 102                         ov5640_0: endpoint {
 103                                 bus-width = <8>;
 104                                 data-shift = <2>;
 105                                 bus-type = <6>;
 106                                 pclk-sample = <1>;
 107                                 remote-endpoint = <&vin0ep>;
 108                         };
 109                 };
 110         };
 111 };
 112
 113 &i2c1 {
 114         pinctrl-0 = <&i2c1_pins>;
 115         pinctrl-names = "default";
 116
 117         status = "okay";
 118         clock-frequency = <400000>;
 119
 120         ov5640@3c {
 121                 compatible = "ovti,ov5640";
 122                 reg = <0x3c>;
 123                 clocks = <&mclk_cam2>;
 124                 clock-names = "xclk";
 125
 126                 port {
 127                         ov5640_1: endpoint {
 128                                 bus-width = <8>;
 129                                 data-shift = <2>;
 130                                 bus-type = <6>;
 131                                 pclk-sample = <1>;
 132                                 remote-endpoint = <&vin1ep>;
 133                         };
 134                 };
 135         };
 136 };
 137
 138 &i2c2 {
 139         ov5640@3c {
 140                 compatible = "ovti,ov5640";
 141                 reg = <0x3c>;
 142                 clocks = <&mclk_cam3>;
 143                 clock-names = "xclk";
 144
 145                 port {
 146                         ov5640_2: endpoint {
 147                                 bus-width = <8>;
 148                                 data-shift = <2>;
 149                                 bus-type = <6>;
 150                                 pclk-sample = <1>;
 151                                 remote-endpoint = <&vin2ep>;
 152                         };
 153                 };
 154         };
 155 };
 156
 157 &i2c3 {
 158         pinctrl-0 = <&i2c3_pins>;
 159         pinctrl-names = "default";
 160
 161         status = "okay";
 162         clock-frequency = <400000>;
 163
 164         ov5640@3c {
 165                 compatible = "ovti,ov5640";
 166                 reg = <0x3c>;
 167                 clocks = <&mclk_cam4>;
 168                 clock-names = "xclk";
 169
 170                 port {
 171                         ov5640_3: endpoint {
 172                                 bus-width = <8>;
 173                                 data-shift = <2>;
 174                                 bus-type = <6>;
 175                                 pclk-sample = <1>;
 176                                 remote-endpoint = <&vin3ep>;
 177                         };
 178                 };
 179         };
 180 };
 181
 182 &pfc {
 183         can0_pins: can0 {
 184                 groups = "can0_data_d";
 185                 function = "can0";
 186         };
 187
 188         ether_pins: ether {
 189                 groups = "eth_mdio", "eth_rmii";
 190                 function = "eth";
 191         };
 192
 193         hscif0_pins: hscif0 {
 194                 groups = "hscif0_data", "hscif0_ctrl";
 195                 function = "hscif0";
 196         };
 197
 198         i2c1_pins: i2c1 {
 199                 groups = "i2c1_c";
 200                 function = "i2c1";
 201         };
 202
 203         i2c3_pins: i2c3 {
 204                 groups = "i2c3";
 205                 function = "i2c3";
 206         };
 207
 208         scif0_pins: scif0 {
 209                 groups = "scif0_data";
 210                 function = "scif0";
 211         };
 212
 213         scif1_pins: scif1 {
 214                 groups = "scif1_data";
 215                 function = "scif1";
 216         };
 217
 218         scifb1_pins: scifb1 {
 219                 groups = "scifb1_data";
 220                 function = "scifb1";
 221         };
 222
 223         vin0_8bit_pins: vin0 {
 224                 groups = "vin0_data8", "vin0_clk", "vin0_sync";
 225                 function = "vin0";
 226         };
 227
 228         vin1_8bit_pins: vin1 {
 229                 groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b";
 230                 function = "vin1";
 231         };
 232
 233         vin2_pins: vin2 {
 234                 groups = "vin2_g8", "vin2_clk";
 235                 function = "vin2";
 236         };
 237
 238         vin3_pins: vin3 {
 239                 groups = "vin3_data8", "vin3_clk", "vin3_sync";
 240                 function = "vin3";
 241         };
 242 };
 243
 244 &qspi {
 245         /* Pins shared with VIN2, keep status disabled */
 246         status = "disabled";
 247 };
 248
 249 &scif0 {
 250         pinctrl-0 = <&scif0_pins>;
 251         pinctrl-names = "default";
 252         status = "okay";
 253 };
 254
 255 &scif1 {
 256         pinctrl-0 = <&scif1_pins>;
 257         pinctrl-names = "default";
 258         status = "okay";
 259 };
 260
 261 &scifb1 {
 262         pinctrl-0 = <&scifb1_pins>;
 263         pinctrl-names = "default";
 264         status = "okay";
 265
 266         rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
 267         cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
 268 };
 269
 270 &vin0 {
 271         /*
 272          * Set SW2 switch on the SOM to 'ON'
 273          * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode
 274          */
 275         status = "okay";
 276         pinctrl-0 = <&vin0_8bit_pins>;
 277         pinctrl-names = "default";
 278
 279         port {
 280                 vin0ep: endpoint {
 281                         remote-endpoint = <&ov5640_0>;
 282                         bus-width = <8>;
 283                         bus-type = <6>;
 284                 };
 285         };
 286 };
 287
 288 &vin1 {
 289         /* Set SW1 switch on the SOM to 'ON' */
 290         status = "okay";
 291         pinctrl-0 = <&vin1_8bit_pins>;
 292         pinctrl-names = "default";
 293
 294         port {
 295                 vin1ep: endpoint {
 296                         remote-endpoint = <&ov5640_1>;
 297                         bus-width = <8>;
 298                         bus-type = <6>;
 299                 };
 300         };
 301 };
 302
 303 &vin2 {
 304         status = "okay";
 305         pinctrl-0 = <&vin2_pins>;
 306         pinctrl-names = "default";
 307
 308         port {
 309                 vin2ep: endpoint {
 310                         remote-endpoint = <&ov5640_2>;
 311                         bus-width = <8>;
 312                         data-shift = <8>;
 313                         bus-type = <6>;
 314                 };
 315         };
 316 };
 317
 318 &vin3 {
 319         status = "okay";
 320         pinctrl-0 = <&vin3_pins>;
 321         pinctrl-names = "default";
 322
 323         port {
 324                 vin3ep: endpoint {
 325                         remote-endpoint = <&ov5640_3>;
 326                         bus-width = <8>;
 327                         bus-type = <6>;
 328                 };
 329         };
 330 };