arch/arm/boot/dts/qcom-msm8226.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         chosen { };
  17
  18         memory@0 {
  19                 device_type = "memory";
  20                 reg = <0x0 0x0>;
  21         };
  22
  23         soc: soc {
  24                 compatible = "simple-bus";
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27                 ranges;
  28
  29                 intc: interrupt-controller@f9000000 {
  30                         compatible = "qcom,msm-qgic2";
  31                         reg = <0xf9000000 0x1000>,
  32                               <0xf9002000 0x1000>;
  33                         interrupt-controller;
  34                         #interrupt-cells = <3>;
  35                 };
  36
  37                 gcc: clock-controller@fc400000 {
  38                         compatible = "qcom,gcc-msm8226";
  39                         reg = <0xfc400000 0x4000>;
  40                         #clock-cells = <1>;
  41                         #reset-cells = <1>;
  42                         #power-domain-cells = <1>;
  43                 };
  44
  45                 tlmm: pinctrl@fd510000 {
  46                         compatible = "qcom,msm8226-pinctrl";
  47                         reg = <0xfd510000 0x4000>;
  48                         gpio-controller;
  49                         #gpio-cells = <2>;
  50                         gpio-ranges = <&tlmm 0 0 117>;
  51                         interrupt-controller;
  52                         #interrupt-cells = <2>;
  53                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  54                 };
  55
  56                 blsp1_uart3: serial@f991f000 {
  57                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  58                         reg = <0xf991f000 0x1000>;
  59                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
  60                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
  61                         clock-names = "core", "iface";
  62                         status = "disabled";
  63                 };
  64
  65                 restart@fc4ab000 {
  66                         compatible = "qcom,pshold";
  67                         reg = <0xfc4ab000 0x4>;
  68                 };
  69
  70                 rng@f9bff000 {
  71                         compatible = "qcom,prng";
  72                         reg = <0xf9bff000 0x200>;
  73                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
  74                         clock-names = "core";
  75                 };
  76
  77                 timer@f9020000 {
  78                         compatible = "arm,armv7-timer-mem";
  79                         reg = <0xf9020000 0x1000>;
  80                         #address-cells = <1>;
  81                         #size-cells = <1>;
  82                         ranges;
  83
  84                         frame@f9021000 {
  85                                 frame-number = <0>;
  86                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  87                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  88                                 reg = <0xf9021000 0x1000>,
  89                                       <0xf9022000 0x1000>;
  90                         };
  91
  92                         frame@f9023000 {
  93                                 frame-number = <1>;
  94                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  95                                 reg = <0xf9023000 0x1000>;
  96                                 status = "disabled";
  97                         };
  98
  99                         frame@f9024000 {
 100                                 frame-number = <2>;
 101                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 102                                 reg = <0xf9024000 0x1000>;
 103                                 status = "disabled";
 104                         };
 105
 106                         frame@f9025000 {
 107                                 frame-number = <3>;
 108                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 109                                 reg = <0xf9025000 0x1000>;
 110                                 status = "disabled";
 111                         };
 112
 113                         frame@f9026000 {
 114                                 frame-number = <4>;
 115                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 116                                 reg = <0xf9026000 0x1000>;
 117                                 status = "disabled";
 118                         };
 119
 120                         frame@f9027000 {
 121                                 frame-number = <5>;
 122                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 123                                 reg = <0xf9027000 0x1000>;
 124                                 status = "disabled";
 125                         };
 126
 127                         frame@f9028000 {
 128                                 frame-number = <6>;
 129                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 130                                 reg = <0xf9028000 0x1000>;
 131                                 status = "disabled";
 132                         };
 133                 };
 134         };
 135
 136         timer {
 137                 compatible = "arm,armv7-timer";
 138                 interrupts = <GIC_PPI 2
 139                                 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
 140                              <GIC_PPI 3
 141                                 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
 142                              <GIC_PPI 4
 143                                 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
 144                              <GIC_PPI 1
 145                                 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
 146         };
 147 };