arch/arm/boot/dts/omap4.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 #include <dt-bindings/bus/ti-sysc.h>
   7 #include <dt-bindings/clock/omap4.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/pinctrl/omap.h>
  11 #include <dt-bindings/clock/omap4.h>
  12
  13 / {
  14         compatible = "ti,omap4430", "ti,omap4";
  15         interrupt-parent = <&wakeupgen>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         chosen { };
  19
  20         aliases {
  21                 i2c0 = &i2c1;
  22                 i2c1 = &i2c2;
  23                 i2c2 = &i2c3;
  24                 i2c3 = &i2c4;
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28                 serial3 = &uart4;
  29                 rproc0 = &dsp;
  30                 rproc1 = &ipu;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         compatible = "arm,cortex-a9";
  39                         device_type = "cpu";
  40                         next-level-cache = <&L2>;
  41                         reg = <0x0>;
  42
  43                         clocks = <&dpll_mpu_ck>;
  44                         clock-names = "cpu";
  45
  46                         clock-latency = <300000>; /* From omap-cpufreq driver */
  47                 };
  48                 cpu@1 {
  49                         compatible = "arm,cortex-a9";
  50                         device_type = "cpu";
  51                         next-level-cache = <&L2>;
  52                         reg = <0x1>;
  53                 };
  54         };
  55
  56         /*
  57          * Note that 4430 needs cross trigger interface (CTI) supported
  58          * before we can configure the interrupts. This means sampling
  59          * events are not supported for pmu. Note that 4460 does not use
  60          * CTI, see also 4460.dtsi.
  61          */
  62         pmu {
  63                 compatible = "arm,cortex-a9-pmu";
  64                 ti,hwmods = "debugss";
  65         };
  66
  67         gic: interrupt-controller@48241000 {
  68                 compatible = "arm,cortex-a9-gic";
  69                 interrupt-controller;
  70                 #interrupt-cells = <3>;
  71                 reg = <0x48241000 0x1000>,
  72                       <0x48240100 0x0100>;
  73                 interrupt-parent = <&gic>;
  74         };
  75
  76         L2: cache-controller@48242000 {
  77                 compatible = "arm,pl310-cache";
  78                 reg = <0x48242000 0x1000>;
  79                 cache-unified;
  80                 cache-level = <2>;
  81         };
  82
  83         local-timer@48240600 {
  84                 compatible = "arm,cortex-a9-twd-timer";
  85                 clocks = <&mpu_periphclk>;
  86                 reg = <0x48240600 0x20>;
  87                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
  88                 interrupt-parent = <&gic>;
  89         };
  90
  91         wakeupgen: interrupt-controller@48281000 {
  92                 compatible = "ti,omap4-wugen-mpu";
  93                 interrupt-controller;
  94                 #interrupt-cells = <3>;
  95                 reg = <0x48281000 0x1000>;
  96                 interrupt-parent = <&gic>;
  97         };
  98
  99         /*
 100          * The soc node represents the soc top level view. It is used for IPs
 101          * that are not memory mapped in the MPU view or for the MPU itself.
 102          */
 103         soc {
 104                 compatible = "ti,omap-infra";
 105                 mpu {
 106                         compatible = "ti,omap4-mpu";
 107                         ti,hwmods = "mpu";
 108                         sram = <&ocmcram>;
 109                 };
 110         };
 111
 112         /*
 113          * XXX: Use a flat representation of the OMAP4 interconnect.
 114          * The real OMAP interconnect network is quite complex.
 115          * Since it will not bring real advantage to represent that in DT for
 116          * the moment, just use a fake OCP bus entry to represent the whole bus
 117          * hierarchy.
 118          */
 119         ocp {
 120                 compatible = "ti,omap4-l3-noc", "simple-bus";
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 ranges;
 124                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 125                 reg = <0x44000000 0x1000>,
 126                       <0x44800000 0x2000>,
 127                       <0x45000000 0x1000>;
 128                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 129                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 130
 131                 l4_wkup: interconnect@4a300000 {
 132                 };
 133
 134                 l4_cfg: interconnect@4a000000 {
 135                 };
 136
 137                 l4_per: interconnect@48000000 {
 138                 };
 139
 140                 l4_abe: interconnect@40100000 {
 141                 };
 142
 143                 ocmcram: sram@40304000 {
 144                         compatible = "mmio-sram";
 145                         reg = <0x40304000 0xa000>; /* 40k */
 146                 };
 147
 148                 target-module@50000000 {
 149                         compatible = "ti,sysc-omap2", "ti,sysc";
 150                         reg = <0x50000000 4>,
 151                               <0x50000010 4>,
 152                               <0x50000014 4>;
 153                         reg-names = "rev", "sysc", "syss";
 154                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 155                                         <SYSC_IDLE_NO>,
 156                                         <SYSC_IDLE_SMART>;
 157                         ti,syss-mask = <1>;
 158                         ti,no-idle-on-init;
 159                         clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
 160                         clock-names = "fck";
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                         ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
 164                                  <0x00000000 0x00000000 0x40000000>; /* data */
 165
 166                         gpmc: gpmc@50000000 {
 167                                 compatible = "ti,omap4430-gpmc";
 168                                 reg = <0x50000000 0x1000>;
 169                                 #address-cells = <2>;
 170                                 #size-cells = <1>;
 171                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 172                                 dmas = <&sdma 4>;
 173                                 dma-names = "rxtx";
 174                                 gpmc,num-cs = <8>;
 175                                 gpmc,num-waitpins = <4>;
 176                                 clocks = <&l3_div_ck>;
 177                                 clock-names = "fck";
 178                                 interrupt-controller;
 179                                 #interrupt-cells = <2>;
 180                                 gpio-controller;
 181                                 #gpio-cells = <2>;
 182                         };
 183                 };
 184
 185                 target-module@52000000 {
 186                         compatible = "ti,sysc-omap4", "ti,sysc";
 187                         ti,hwmods = "iss";
 188                         reg = <0x52000000 0x4>,
 189                               <0x52000010 0x4>;
 190                         reg-names = "rev", "sysc";
 191                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 192                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 193                                         <SYSC_IDLE_NO>,
 194                                         <SYSC_IDLE_SMART>,
 195                                         <SYSC_IDLE_SMART_WKUP>;
 196                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 197                                         <SYSC_IDLE_NO>,
 198                                         <SYSC_IDLE_SMART>,
 199                                         <SYSC_IDLE_SMART_WKUP>;
 200                         ti,sysc-delay-us = <2>;
 201                         clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
 202                         clock-names = "fck";
 203                         #address-cells = <1>;
 204                         #size-cells = <1>;
 205                         ranges = <0 0x52000000 0x1000000>;
 206
 207                         /* No child device binding, driver in staging */
 208                 };
 209
 210                 target-module@55082000 {
 211                         compatible = "ti,sysc-omap2", "ti,sysc";
 212                         reg = <0x55082000 0x4>,
 213                               <0x55082010 0x4>,
 214                               <0x55082014 0x4>;
 215                         reg-names = "rev", "sysc", "syss";
 216                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 217                                         <SYSC_IDLE_NO>,
 218                                         <SYSC_IDLE_SMART>;
 219                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 220                                          SYSC_OMAP2_SOFTRESET |
 221                                          SYSC_OMAP2_AUTOIDLE)>;
 222                         clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
 223                         clock-names = "fck";
 224                         resets = <&prm_core 2>;
 225                         reset-names = "rstctrl";
 226                         ranges = <0x0 0x55082000 0x100>;
 227                         #size-cells = <1>;
 228                         #address-cells = <1>;
 229
 230                         mmu_ipu: mmu@0 {
 231                                 compatible = "ti,omap4-iommu";
 232                                 reg = <0x0 0x100>;
 233                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 234                                 #iommu-cells = <0>;
 235                                 ti,iommu-bus-err-back;
 236                         };
 237                 };
 238
 239                 target-module@4012c000 {
 240                         compatible = "ti,sysc-omap4", "ti,sysc";
 241                         reg = <0x4012c000 0x4>,
 242                               <0x4012c010 0x4>;
 243                         reg-names = "rev", "sysc";
 244                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 245                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 246                                         <SYSC_IDLE_NO>,
 247                                         <SYSC_IDLE_SMART>,
 248                                         <SYSC_IDLE_SMART_WKUP>;
 249                         clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
 250                         clock-names = "fck";
 251                         #address-cells = <1>;
 252                         #size-cells = <1>;
 253                         ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
 254                                  <0x4902c000 0x4902c000 0x1000>; /* L3 */
 255
 256                         /* No child device binding or driver in mainline */
 257                 };
 258
 259                 dmm@4e000000 {
 260                         compatible = "ti,omap4-dmm";
 261                         reg = <0x4e000000 0x800>;
 262                         interrupts = <0 113 0x4>;
 263                         ti,hwmods = "dmm";
 264                 };
 265
 266                 emif1: emif@4c000000 {
 267                         compatible = "ti,emif-4d";
 268                         reg = <0x4c000000 0x100>;
 269                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 270                         ti,hwmods = "emif1";
 271                         ti,no-idle-on-init;
 272                         phy-type = <1>;
 273                         hw-caps-read-idle-ctrl;
 274                         hw-caps-ll-interface;
 275                         hw-caps-temp-alert;
 276                 };
 277
 278                 emif2: emif@4d000000 {
 279                         compatible = "ti,emif-4d";
 280                         reg = <0x4d000000 0x100>;
 281                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 282                         ti,hwmods = "emif2";
 283                         ti,no-idle-on-init;
 284                         phy-type = <1>;
 285                         hw-caps-read-idle-ctrl;
 286                         hw-caps-ll-interface;
 287                         hw-caps-temp-alert;
 288                 };
 289
 290                 dsp: dsp {
 291                         compatible = "ti,omap4-dsp";
 292                         ti,bootreg = <&scm_conf 0x304 0>;
 293                         iommus = <&mmu_dsp>;
 294                         resets = <&prm_tesla 0>;
 295                         clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
 296                         firmware-name = "omap4-dsp-fw.xe64T";
 297                         mboxes = <&mailbox &mbox_dsp>;
 298                         status = "disabled";
 299                 };
 300
 301                 ipu: ipu@55020000 {
 302                         compatible = "ti,omap4-ipu";
 303                         reg = <0x55020000 0x10000>;
 304                         reg-names = "l2ram";
 305                         iommus = <&mmu_ipu>;
 306                         resets = <&prm_core 0>, <&prm_core 1>;
 307                         clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
 308                         firmware-name = "omap4-ipu-fw.xem3";
 309                         mboxes = <&mailbox &mbox_ipu>;
 310                         status = "disabled";
 311                 };
 312
 313                 aes1_target: target-module@4b501000 {
 314                         compatible = "ti,sysc-omap2", "ti,sysc";
 315                         reg = <0x4b501080 0x4>,
 316                               <0x4b501084 0x4>,
 317                               <0x4b501088 0x4>;
 318                         reg-names = "rev", "sysc", "syss";
 319                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 320                                          SYSC_OMAP2_AUTOIDLE)>;
 321                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 322                                         <SYSC_IDLE_NO>,
 323                                         <SYSC_IDLE_SMART>,
 324                                         <SYSC_IDLE_SMART_WKUP>;
 325                         ti,syss-mask = <1>;
 326                         /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
 327                         clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
 328                         clock-names = "fck";
 329                         #address-cells = <1>;
 330                         #size-cells = <1>;
 331                         ranges = <0x0 0x4b501000 0x1000>;
 332
 333                         aes1: aes@0 {
 334                                 compatible = "ti,omap4-aes";
 335                                 reg = <0 0xa0>;
 336                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 337                                 dmas = <&sdma 111>, <&sdma 110>;
 338                                 dma-names = "tx", "rx";
 339                         };
 340                 };
 341
 342                 aes2_target: target-module@4b701000 {
 343                         compatible = "ti,sysc-omap2", "ti,sysc";
 344                         reg = <0x4b701080 0x4>,
 345                               <0x4b701084 0x4>,
 346                               <0x4b701088 0x4>;
 347                         reg-names = "rev", "sysc", "syss";
 348                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 349                                          SYSC_OMAP2_AUTOIDLE)>;
 350                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 351                                         <SYSC_IDLE_NO>,
 352                                         <SYSC_IDLE_SMART>,
 353                                         <SYSC_IDLE_SMART_WKUP>;
 354                         ti,syss-mask = <1>;
 355                         /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
 356                         clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
 357                         clock-names = "fck";
 358                         #address-cells = <1>;
 359                         #size-cells = <1>;
 360                         ranges = <0x0 0x4b701000 0x1000>;
 361
 362                         aes2: aes@0 {
 363                                 compatible = "ti,omap4-aes";
 364                                 reg = <0 0xa0>;
 365                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 366                                 dmas = <&sdma 114>, <&sdma 113>;
 367                                 dma-names = "tx", "rx";
 368                         };
 369                 };
 370
 371                 sham_target: target-module@4b100000 {
 372                         compatible = "ti,sysc-omap3-sham", "ti,sysc";
 373                         reg = <0x4b100100 0x4>,
 374                               <0x4b100110 0x4>,
 375                               <0x4b100114 0x4>;
 376                         reg-names = "rev", "sysc", "syss";
 377                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 378                                          SYSC_OMAP2_AUTOIDLE)>;
 379                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 380                                         <SYSC_IDLE_NO>,
 381                                         <SYSC_IDLE_SMART>;
 382                         ti,syss-mask = <1>;
 383                         /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
 384                         clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
 385                         clock-names = "fck";
 386                         #address-cells = <1>;
 387                         #size-cells = <1>;
 388                         ranges = <0x0 0x4b100000 0x1000>;
 389
 390                         sham: sham@0 {
 391                                 compatible = "ti,omap4-sham";
 392                                 reg = <0 0x300>;
 393                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 394                                 dmas = <&sdma 119>;
 395                                 dma-names = "rx";
 396                         };
 397                 };
 398
 399                 abb_mpu: regulator-abb-mpu {
 400                         compatible = "ti,abb-v2";
 401                         regulator-name = "abb_mpu";
 402                         #address-cells = <0>;
 403                         #size-cells = <0>;
 404                         ti,tranxdone-status-mask = <0x80>;
 405                         clocks = <&sys_clkin_ck>;
 406                         ti,settling-time = <50>;
 407                         ti,clock-cycles = <16>;
 408
 409                         status = "disabled";
 410                 };
 411
 412                 abb_iva: regulator-abb-iva {
 413                         compatible = "ti,abb-v2";
 414                         regulator-name = "abb_iva";
 415                         #address-cells = <0>;
 416                         #size-cells = <0>;
 417                         ti,tranxdone-status-mask = <0x80000000>;
 418                         clocks = <&sys_clkin_ck>;
 419                         ti,settling-time = <50>;
 420                         ti,clock-cycles = <16>;
 421
 422                         status = "disabled";
 423                 };
 424
 425                 sgx_module: target-module@56000000 {
 426                         compatible = "ti,sysc-omap4", "ti,sysc";
 427                         reg = <0x5600fe00 0x4>,
 428                               <0x5600fe10 0x4>;
 429                         reg-names = "rev", "sysc";
 430                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 431                                         <SYSC_IDLE_NO>,
 432                                         <SYSC_IDLE_SMART>,
 433                                         <SYSC_IDLE_SMART_WKUP>;
 434                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 435                                         <SYSC_IDLE_NO>,
 436                                         <SYSC_IDLE_SMART>,
 437                                         <SYSC_IDLE_SMART_WKUP>;
 438                         clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
 439                         clock-names = "fck";
 440                         #address-cells = <1>;
 441                         #size-cells = <1>;
 442                         ranges = <0 0x56000000 0x2000000>;
 443
 444                         /*
 445                          * Closed source PowerVR driver, no child device
 446                          * binding or driver in mainline
 447                          */
 448                 };
 449
 450                 /*
 451                  * DSS is only using l3 mapping without l4 as noted in the TRM
 452                  * "10.1.3 DSS Register Manual" for omap4460.
 453                  */
 454                 target-module@58000000 {
 455                         compatible = "ti,sysc-omap2", "ti,sysc";
 456                         reg = <0x58000000 4>,
 457                               <0x58000014 4>;
 458                         reg-names = "rev", "syss";
 459                         ti,syss-mask = <1>;
 460                         power-domains = <&prm_dss>;
 461                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
 462                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
 463                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
 464                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
 465                         clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
 466                         #address-cells = <1>;
 467                         #size-cells = <1>;
 468                         ranges = <0 0x58000000 0x1000000>;
 469
 470                         dss: dss@0 {
 471                                 compatible = "ti,omap4-dss";
 472                                 reg = <0 0x80>;
 473                                 status = "disabled";
 474                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 475                                 clock-names = "fck";
 476                                 #address-cells = <1>;
 477                                 #size-cells = <1>;
 478                                 ranges = <0 0 0x1000000>;
 479
 480                                 target-module@1000 {
 481                                         compatible = "ti,sysc-omap2", "ti,sysc";
 482                                         reg = <0x1000 0x4>,
 483                                               <0x1010 0x4>,
 484                                               <0x1014 0x4>;
 485                                         reg-names = "rev", "sysc", "syss";
 486                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 487                                                         <SYSC_IDLE_NO>,
 488                                                         <SYSC_IDLE_SMART>;
 489                                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 490                                                         <SYSC_IDLE_NO>,
 491                                                         <SYSC_IDLE_SMART>;
 492                                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 493                                                          SYSC_OMAP2_ENAWAKEUP |
 494                                                          SYSC_OMAP2_SOFTRESET |
 495                                                          SYSC_OMAP2_AUTOIDLE)>;
 496                                         ti,syss-mask = <1>;
 497                                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 498                                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 499                                         clock-names = "fck", "sys_clk";
 500                                         #address-cells = <1>;
 501                                         #size-cells = <1>;
 502                                         ranges = <0 0x1000 0x1000>;
 503
 504                                         dispc@0 {
 505                                                 compatible = "ti,omap4-dispc";
 506                                                 reg = <0 0x1000>;
 507                                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 508                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 509                                                 clock-names = "fck";
 510                                         };
 511                                 };
 512
 513                                 target-module@2000 {
 514                                         compatible = "ti,sysc-omap2", "ti,sysc";
 515                                         reg = <0x2000 0x4>,
 516                                               <0x2010 0x4>,
 517                                               <0x2014 0x4>;
 518                                         reg-names = "rev", "sysc", "syss";
 519                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 520                                                         <SYSC_IDLE_NO>,
 521                                                         <SYSC_IDLE_SMART>;
 522                                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 523                                                          SYSC_OMAP2_AUTOIDLE)>;
 524                                         ti,syss-mask = <1>;
 525                                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 526                                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 527                                         clock-names = "fck", "sys_clk";
 528                                         #address-cells = <1>;
 529                                         #size-cells = <1>;
 530                                         ranges = <0 0x2000 0x1000>;
 531
 532                                         rfbi: encoder@0  {
 533                                                 reg = <0 0x1000>;
 534                                                 status = "disabled";
 535                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
 536                                                 clock-names = "fck", "ick";
 537                                         };
 538                                 };
 539
 540                                 target-module@3000 {
 541                                         compatible = "ti,sysc-omap2", "ti,sysc";
 542                                         reg = <0x3000 0x4>;
 543                                         reg-names = "rev";
 544                                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 545                                         clock-names = "sys_clk";
 546                                         #address-cells = <1>;
 547                                         #size-cells = <1>;
 548                                         ranges = <0 0x3000 0x1000>;
 549
 550                                         venc: encoder@0 {
 551                                                 compatible = "ti,omap4-venc";
 552                                                 reg = <0 0x1000>;
 553                                                 status = "disabled";
 554                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
 555                                                 clock-names = "fck";
 556                                         };
 557                                 };
 558
 559                                 target-module@4000 {
 560                                         compatible = "ti,sysc-omap2", "ti,sysc";
 561                                         reg = <0x4000 0x4>,
 562                                               <0x4010 0x4>,
 563                                               <0x4014 0x4>;
 564                                         reg-names = "rev", "sysc", "syss";
 565                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 566                                                         <SYSC_IDLE_NO>,
 567                                                         <SYSC_IDLE_SMART>;
 568                                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 569                                                          SYSC_OMAP2_ENAWAKEUP |
 570                                                          SYSC_OMAP2_SOFTRESET |
 571                                                          SYSC_OMAP2_AUTOIDLE)>;
 572                                         ti,syss-mask = <1>;
 573                                         #address-cells = <1>;
 574                                         #size-cells = <1>;
 575                                         ranges = <0 0x4000 0x1000>;
 576
 577                                         dsi1: encoder@0 {
 578                                                 compatible = "ti,omap4-dsi";
 579                                                 reg = <0 0x200>,
 580                                                       <0x200 0x40>,
 581                                                       <0x300 0x20>;
 582                                                 reg-names = "proto", "phy", "pll";
 583                                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 584                                                 status = "disabled";
 585                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 586                                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 587                                                 clock-names = "fck", "sys_clk";
 588
 589                                                 #address-cells = <1>;
 590                                                 #size-cells = <0>;
 591                                         };
 592                                 };
 593
 594                                 target-module@5000 {
 595                                         compatible = "ti,sysc-omap2", "ti,sysc";
 596                                         reg = <0x5000 0x4>,
 597                                               <0x5010 0x4>,
 598                                               <0x5014 0x4>;
 599                                         reg-names = "rev", "sysc", "syss";
 600                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 601                                                         <SYSC_IDLE_NO>,
 602                                                         <SYSC_IDLE_SMART>;
 603                                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 604                                                          SYSC_OMAP2_ENAWAKEUP |
 605                                                          SYSC_OMAP2_SOFTRESET |
 606                                                          SYSC_OMAP2_AUTOIDLE)>;
 607                                         ti,syss-mask = <1>;
 608                                         #address-cells = <1>;
 609                                         #size-cells = <1>;
 610                                         ranges = <0 0x5000 0x1000>;
 611
 612                                         dsi2: encoder@0 {
 613                                                 compatible = "ti,omap4-dsi";
 614                                                 reg = <0 0x200>,
 615                                                       <0x200 0x40>,
 616                                                       <0x300 0x20>;
 617                                                 reg-names = "proto", "phy", "pll";
 618                                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 619                                                 status = "disabled";
 620                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 621                                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 622                                                 clock-names = "fck", "sys_clk";
 623
 624                                                 #address-cells = <1>;
 625                                                 #size-cells = <0>;
 626                                         };
 627                                 };
 628
 629                                 target-module@6000 {
 630                                         compatible = "ti,sysc-omap4", "ti,sysc";
 631                                         reg = <0x6000 0x4>,
 632                                               <0x6010 0x4>;
 633                                         reg-names = "rev", "sysc";
 634                                         /*
 635                                          * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
 636                                          * but HDMI audio will fail with them.
 637                                          */
 638                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 639                                                         <SYSC_IDLE_NO>;
 640                                         ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
 641                                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
 642                                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 643                                         clock-names = "fck", "dss_clk";
 644                                         #address-cells = <1>;
 645                                         #size-cells = <1>;
 646                                         ranges = <0 0x6000 0x2000>;
 647
 648                                         hdmi: encoder@0 {
 649                                         compatible = "ti,omap4-hdmi";
 650                                                 reg = <0 0x200>,
 651                                                       <0x200 0x100>,
 652                                                       <0x300 0x100>,
 653                                                       <0x400 0x1000>;
 654                                                 reg-names = "wp", "pll", "phy", "core";
 655                                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 656                                                 status = "disabled";
 657                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
 658                                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 659                                                 clock-names = "fck", "sys_clk";
 660                                                 dmas = <&sdma 76>;
 661                                                 dma-names = "audio_tx";
 662                                         };
 663                                 };
 664                         };
 665                 };
 666
 667                 iva_hd_target: target-module@5a000000 {
 668                         compatible = "ti,sysc-omap4", "ti,sysc";
 669                         reg = <0x5a05a400 0x4>,
 670                               <0x5a05a410 0x4>;
 671                         reg-names = "rev", "sysc";
 672                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 673                                         <SYSC_IDLE_NO>,
 674                                         <SYSC_IDLE_SMART>;
 675                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 676                                         <SYSC_IDLE_NO>,
 677                                         <SYSC_IDLE_SMART>;
 678                         power-domains = <&prm_ivahd>;
 679                         resets = <&prm_ivahd 2>;
 680                         reset-names = "rstctrl";
 681                         clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
 682                         clock-names = "fck";
 683                         #address-cells = <1>;
 684                         #size-cells = <1>;
 685                         ranges = <0x5a000000 0x5a000000 0x1000000>,
 686                                  <0x5b000000 0x5b000000 0x1000000>;
 687
 688                         iva {
 689                                 compatible = "ti,ivahd";
 690                         };
 691                 };
 692         };
 693 };
 694
 695 #include "omap4-l4.dtsi"
 696 #include "omap4-l4-abe.dtsi"
 697 #include "omap44xx-clocks.dtsi"
 698
 699 &prm {
 700         prm_mpu: prm@300 {
 701                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 702                 reg = <0x300 0x100>;
 703                 #power-domain-cells = <0>;
 704         };
 705
 706         prm_tesla: prm@400 {
 707                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 708                 reg = <0x400 0x100>;
 709                 #reset-cells = <1>;
 710                 #power-domain-cells = <0>;
 711         };
 712
 713         prm_abe: prm@500 {
 714                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 715                 reg = <0x500 0x100>;
 716                 #power-domain-cells = <0>;
 717         };
 718
 719         prm_always_on_core: prm@600 {
 720                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 721                 reg = <0x600 0x100>;
 722                 #power-domain-cells = <0>;
 723         };
 724
 725         prm_core: prm@700 {
 726                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 727                 reg = <0x700 0x100>;
 728                 #reset-cells = <1>;
 729                 #power-domain-cells = <0>;
 730         };
 731
 732         prm_ivahd: prm@f00 {
 733                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 734                 reg = <0xf00 0x100>;
 735                 #reset-cells = <1>;
 736                 #power-domain-cells = <0>;
 737         };
 738
 739         prm_cam: prm@1000 {
 740                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 741                 reg = <0x1000 0x100>;
 742                 #power-domain-cells = <0>;
 743         };
 744
 745         prm_dss: prm@1100 {
 746                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 747                 reg = <0x1100 0x100>;
 748                 #power-domain-cells = <0>;
 749         };
 750
 751         prm_gfx: prm@1200 {
 752                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 753                 reg = <0x1200 0x100>;
 754                 #power-domain-cells = <0>;
 755         };
 756
 757         prm_l3init: prm@1300 {
 758                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 759                 reg = <0x1300 0x100>;
 760                 #power-domain-cells = <0>;
 761         };
 762
 763         prm_l4per: prm@1400 {
 764                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 765                 reg = <0x1400 0x100>;
 766                 #power-domain-cells = <0>;
 767         };
 768
 769         prm_cefuse: prm@1600 {
 770                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 771                 reg = <0x1600 0x100>;
 772                 #power-domain-cells = <0>;
 773         };
 774
 775         prm_wkup: prm@1700 {
 776                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 777                 reg = <0x1700 0x100>;
 778                 #power-domain-cells = <0>;
 779         };
 780
 781         prm_emu: prm@1900 {
 782                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 783                 reg = <0x1900 0x100>;
 784                 #power-domain-cells = <0>;
 785         };
 786
 787         prm_dss: prm@1100 {
 788                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 789                 reg = <0x1100 0x40>;
 790                 #power-domain-cells = <0>;
 791         };
 792
 793         prm_device: prm@1b00 {
 794                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 795                 reg = <0x1b00 0x40>;
 796                 #reset-cells = <1>;
 797         };
 798 };
 799
 800 /* Preferred always-on timer for clockevent */
 801 &timer1_target {
 802         ti,no-reset-on-init;
 803         ti,no-idle;
 804         timer@0 {
 805                 assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
 806                 assigned-clock-parents = <&sys_32k_ck>;
 807         };
 808 };