arch/arm/boot/dts/omap36xx.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 SoC
   3  *
   4  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/bus/ti-sysc.h>
  12 #include <dt-bindings/media/omap3-isp.h>
  13
  14 #include "omap3.dtsi"
  15
  16 / {
  17         aliases {
  18                 serial3 = &uart4;
  19         };
  20
  21         cpus {
  22                 /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
  23                 cpu: cpu@0 {
  24                         operating-points-v2 = <&cpu0_opp_table>;
  25
  26                         vbb-supply = <&abb_mpu_iva>;
  27                         clock-latency = <300000>; /* From omap-cpufreq driver */
  28                         #cooling-cells = <2>;
  29                 };
  30         };
  31
  32         cpu0_opp_table: opp-table {
  33                 compatible = "operating-points-v2-ti-cpu";
  34                 syscon = <&scm_conf>;
  35
  36                 opp50-300000000 {
  37                         opp-hz = /bits/ 64 <300000000>;
  38                         /*
  39                          * we currently only select the max voltage from table
  40                          * Table 4-19 of the DM3730 Data sheet (SPRS685B)
  41                          * Format is:   cpu0-supply:    <target min max>
  42                          *              vbb-supply:     <target min max>
  43                          */
  44                         opp-microvolt = <1012500 1012500 1012500>,
  45                                          <1012500 1012500 1012500>;
  46                         /*
  47                          * first value is silicon revision bit mask
  48                          * second one is "speed binned" bit mask
  49                          */
  50                         opp-supported-hw = <0xffffffff 3>;
  51                         opp-suspend;
  52                 };
  53
  54                 opp100-600000000 {
  55                         opp-hz = /bits/ 64 <600000000>;
  56                         opp-microvolt = <1200000 1200000 1200000>,
  57                                          <1200000 1200000 1200000>;
  58                         opp-supported-hw = <0xffffffff 3>;
  59                 };
  60
  61                 opp130-800000000 {
  62                         opp-hz = /bits/ 64 <800000000>;
  63                         opp-microvolt = <1325000 1325000 1325000>,
  64                                          <1325000 1325000 1325000>;
  65                         opp-supported-hw = <0xffffffff 3>;
  66                 };
  67
  68                 opp1g-1000000000 {
  69                         opp-hz = /bits/ 64 <1000000000>;
  70                         opp-microvolt = <1375000 1375000 1375000>,
  71                                          <1375000 1375000 1375000>;
  72                         /* only on am/dm37x with speed-binned bit set */
  73                         opp-supported-hw = <0xffffffff 2>;
  74                 };
  75         };
  76
  77         opp_supply_mpu_iva: opp_supply {
  78                 compatible = "ti,omap-opp-supply";
  79                 ti,absolute-max-voltage-uv = <1375000>;
  80         };
  81
  82         ocp@68000000 {
  83                 uart4: serial@49042000 {
  84                         compatible = "ti,omap3-uart";
  85                         reg = <0x49042000 0x400>;
  86                         interrupts = <80>;
  87                         dmas = <&sdma 81 &sdma 82>;
  88                         dma-names = "tx", "rx";
  89                         ti,hwmods = "uart4";
  90                         clock-frequency = <48000000>;
  91                 };
  92
  93                 abb_mpu_iva: regulator-abb-mpu {
  94                         compatible = "ti,abb-v1";
  95                         regulator-name = "abb_mpu_iva";
  96                         #address-cells = <0>;
  97                         #size-cells = <0>;
  98                         reg = <0x483072f0 0x8>, <0x48306818 0x4>;
  99                         reg-names = "base-address", "int-address";
 100                         ti,tranxdone-status-mask = <0x4000000>;
 101                         clocks = <&sys_ck>;
 102                         ti,settling-time = <30>;
 103                         ti,clock-cycles = <8>;
 104                         ti,abb_info = <
 105                         /*uV            ABB     efuse   rbb_m   fbb_m   vset_m*/
 106                         1012500         0       0       0       0       0
 107                         1200000         0       0       0       0       0
 108                         1325000         0       0       0       0       0
 109                         1375000         1       0       0       0       0
 110                         >;
 111                 };
 112
 113                 omap3_pmx_core2: pinmux@480025a0 {
 114                         compatible = "ti,omap3-padconf", "pinctrl-single";
 115                         reg = <0x480025a0 0x5c>;
 116                         #address-cells = <1>;
 117                         #size-cells = <0>;
 118                         #pinctrl-cells = <1>;
 119                         #interrupt-cells = <1>;
 120                         interrupt-controller;
 121                         pinctrl-single,register-width = <16>;
 122                         pinctrl-single,function-mask = <0xff1f>;
 123                 };
 124
 125                 isp: isp@480bc000 {
 126                         compatible = "ti,omap3-isp";
 127                         reg = <0x480bc000 0x12fc
 128                                0x480bd800 0x0600>;
 129                         interrupts = <24>;
 130                         iommus = <&mmu_isp>;
 131                         syscon = <&scm_conf 0x2f0>;
 132                         ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
 133                         #clock-cells = <1>;
 134                         ports {
 135                                 #address-cells = <1>;
 136                                 #size-cells = <0>;
 137                         };
 138                 };
 139
 140                 bandgap: bandgap@48002524 {
 141                         reg = <0x48002524 0x4>;
 142                         compatible = "ti,omap36xx-bandgap";
 143                         #thermal-sensor-cells = <0>;
 144                 };
 145
 146                 target-module@480cb000 {
 147                         compatible = "ti,sysc-omap3630-sr", "ti,sysc";
 148                         ti,hwmods = "smartreflex_core";
 149                         reg = <0x480cb038 0x4>;
 150                         reg-names = "sysc";
 151                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 152                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 153                                         <SYSC_IDLE_NO>,
 154                                         <SYSC_IDLE_SMART>;
 155                         clocks = <&sr2_fck>;
 156                         clock-names = "fck";
 157                         #address-cells = <1>;
 158                         #size-cells = <1>;
 159                         ranges = <0 0x480cb000 0x001000>;
 160
 161                         smartreflex_core: smartreflex@0 {
 162                                 compatible = "ti,omap3-smartreflex-core";
 163                                 reg = <0 0x400>;
 164                                 interrupts = <19>;
 165                         };
 166                 };
 167
 168                 target-module@480c9000 {
 169                         compatible = "ti,sysc-omap3630-sr", "ti,sysc";
 170                         ti,hwmods = "smartreflex_mpu_iva";
 171                         reg = <0x480c9038 0x4>;
 172                         reg-names = "sysc";
 173                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 174                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 175                                         <SYSC_IDLE_NO>,
 176                                         <SYSC_IDLE_SMART>;
 177                         clocks = <&sr1_fck>;
 178                         clock-names = "fck";
 179                         #address-cells = <1>;
 180                         #size-cells = <1>;
 181                         ranges = <0 0x480c9000 0x001000>;
 182
 183
 184                         smartreflex_mpu_iva: smartreflex@480c9000 {
 185                                 compatible = "ti,omap3-smartreflex-mpu-iva";
 186                                 reg = <0 0x400>;
 187                                 interrupts = <18>;
 188                         };
 189                 };
 190
 191                 /*
 192                  * Note that the sysconfig register layout is a subset of the
 193                  * "ti,sysc-omap4" type register with just sidle and midle bits
 194                  * available while omap34xx has "ti,sysc-omap2" type sysconfig.
 195                  */
 196                 sgx_module: target-module@50000000 {
 197                         compatible = "ti,sysc-omap4", "ti,sysc";
 198                         reg = <0x5000fe00 0x4>,
 199                               <0x5000fe10 0x4>;
 200                         reg-names = "rev", "sysc";
 201                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 202                                         <SYSC_IDLE_NO>,
 203                                         <SYSC_IDLE_SMART>;
 204                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 205                                         <SYSC_IDLE_NO>,
 206                                         <SYSC_IDLE_SMART>;
 207                         clocks = <&sgx_fck>, <&sgx_ick>;
 208                         clock-names = "fck", "ick";
 209                         #address-cells = <1>;
 210                         #size-cells = <1>;
 211                         ranges = <0 0x50000000 0x2000000>;
 212
 213                         /*
 214                          * Closed source PowerVR driver, no child device
 215                          * binding or driver in mainline
 216                          */
 217                 };
 218         };
 219
 220         thermal_zones: thermal-zones {
 221                 #include "omap3-cpu-thermal.dtsi"
 222         };
 223 };
 224
 225 &sdma {
 226         compatible = "ti,omap3630-sdma", "ti,omap-sdma";
 227 };
 228
 229 /* OMAP3630 needs dss_96m_fck for VENC */
 230 &venc {
 231         clocks = <&dss_tv_fck>, <&dss_96m_fck>;
 232         clock-names = "fck", "tv_dac_clk";
 233 };
 234
 235 &ssi {
 236         status = "okay";
 237
 238         clocks = <&ssi_ssr_fck>,
 239                  <&ssi_sst_fck>,
 240                  <&ssi_ick>;
 241         clock-names = "ssi_ssr_fck",
 242                       "ssi_sst_fck",
 243                       "ssi_ick";
 244 };
 245
 246 /include/ "omap34xx-omap36xx-clocks.dtsi"
 247 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
 248 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
 249 /include/ "omap36xx-clocks.dtsi"