arch/arm/boot/dts/nuvoton-npcm730.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2020 Nuvoton Technology
   3
   4 #include "nuvoton-common-npcm7xx.dtsi"
   5
   6 / {
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&gic>;
  10
  11         cpus {
  12                 #address-cells = <1>;
  13                 #size-cells = <0>;
  14                 enable-method = "nuvoton,npcm750-smp";
  15
  16                 cpu@0 {
  17                         device_type = "cpu";
  18                         compatible = "arm,cortex-a9";
  19                         clocks = <&clk NPCM7XX_CLK_CPU>;
  20                         clock-names = "clk_cpu";
  21                         reg = <0>;
  22                         next-level-cache = <&l2>;
  23                 };
  24
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         clocks = <&clk NPCM7XX_CLK_CPU>;
  29                         clock-names = "clk_cpu";
  30                         reg = <1>;
  31                         next-level-cache = <&l2>;
  32                 };
  33         };
  34
  35         soc {
  36                 timer@3fe600 {
  37                         compatible = "arm,cortex-a9-twd-timer";
  38                         reg = <0x3fe600 0x20>;
  39                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  40                                                   IRQ_TYPE_LEVEL_HIGH)>;
  41                         clocks = <&clk NPCM7XX_CLK_AHB>;
  42                 };
  43         };
  44 };