arch/arm/boot/dts/mstar-v7.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (c) 2020 thingy.jp.
   4  * Author: Daniel Palmer <daniel@thingy.jp>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13         interrupt-parent = <&gic>;
  14
  15         cpus: cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a7";
  22                         reg = <0x0>;
  23                 };
  24         };
  25
  26         arch_timer {
  27                 compatible = "arm,armv7-timer";
  28                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
  29                                 | IRQ_TYPE_LEVEL_LOW)>,
  30                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
  31                                 | IRQ_TYPE_LEVEL_LOW)>,
  32                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
  33                                 | IRQ_TYPE_LEVEL_LOW)>,
  34                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
  35                                 | IRQ_TYPE_LEVEL_LOW)>;
  36                 /*
  37                  * we shouldn't need this but the vendor
  38                  * u-boot is broken
  39                  */
  40                 clock-frequency = <6000000>;
  41         };
  42
  43         pmu: pmu {
  44                 compatible = "arm,cortex-a7-pmu";
  45                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  46                 interrupt-affinity = <&cpu0>;
  47         };
  48
  49         soc: soc {
  50                 compatible = "simple-bus";
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 ranges = <0x16001000 0x16001000 0x00007000>,
  54                          <0x1f000000 0x1f000000 0x00400000>,
  55                          <0xa0000000 0xa0000000 0x20000>;
  56
  57                 gic: interrupt-controller@16001000 {
  58                         compatible = "arm,cortex-a7-gic";
  59                         reg = <0x16001000 0x1000>,
  60                               <0x16002000 0x2000>,
  61                               <0x16004000 0x2000>,
  62                               <0x16006000 0x2000>;
  63                         #interrupt-cells = <3>;
  64                         interrupt-controller;
  65                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
  66                                         | IRQ_TYPE_LEVEL_LOW)>;
  67                 };
  68
  69                 riu: bus@1f000000 {
  70                         compatible = "simple-bus";
  71                         reg = <0x1f000000 0x00400000>;
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         ranges = <0x0 0x1f000000 0x00400000>;
  75
  76                         pmsleep: syscon@1c00 {
  77                                 compatible = "mstar,msc313-pmsleep", "syscon";
  78                                 reg = <0x1c00 0x100>;
  79                         };
  80
  81                         reboot {
  82                                 compatible = "syscon-reboot";
  83                                 regmap = <&pmsleep>;
  84                                 offset = <0xb8>;
  85                                 mask = <0x79>;
  86                         };
  87
  88                         intc_fiq: interrupt-controller@201310 {
  89                                 compatible = "mstar,mst-intc";
  90                                 reg = <0x201310 0x40>;
  91                                 #interrupt-cells = <3>;
  92                                 interrupt-controller;
  93                                 interrupt-parent = <&gic>;
  94                                 mstar,irqs-map-range = <96 127>;
  95                         };
  96
  97                         intc_irq: interrupt-controller@201350 {
  98                                 compatible = "mstar,mst-intc";
  99                                 reg = <0x201350 0x40>;
 100                                 #interrupt-cells = <3>;
 101                                 interrupt-controller;
 102                                 interrupt-parent = <&gic>;
 103                                 mstar,irqs-map-range = <32 95>;
 104                                 mstar,intc-no-eoi;
 105                         };
 106
 107                         l3bridge: l3bridge@204400 {
 108                                 compatible = "mstar,l3bridge";
 109                                 reg = <0x204400 0x200>;
 110                         };
 111
 112                         gpio: gpio@207800 {
 113                                 #gpio-cells = <2>;
 114                                 reg = <0x207800 0x200>;
 115                                 gpio-controller;
 116                                 #interrupt-cells = <2>;
 117                                 interrupt-controller;
 118                                 interrupt-parent = <&intc_fiq>;
 119                                 status = "disabled";
 120                         };
 121
 122                         pm_uart: uart@221000 {
 123                                 compatible = "ns16550a";
 124                                 reg = <0x221000 0x100>;
 125                                 reg-shift = <3>;
 126                                 interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 127                                 clock-frequency = <172000000>;
 128                                 status = "disabled";
 129                         };
 130                 };
 131
 132                 imi: sram@a0000000 {
 133                         compatible = "mmio-sram";
 134                         reg = <0xa0000000 0x10000>;
 135                 };
 136         };
 137 };