arch/arm/boot/dts/ls1021a.dtsi

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54         compatible = "fsl,ls1021a";
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 crypto = &crypto;
  59                 ethernet0 = &enet0;
  60                 ethernet1 = &enet1;
  61                 ethernet2 = &enet2;
  62                 rtc1 = &ftm_alarm0;
  63                 serial0 = &lpuart0;
  64                 serial1 = &lpuart1;
  65                 serial2 = &lpuart2;
  66                 serial3 = &lpuart3;
  67                 serial4 = &lpuart4;
  68                 serial5 = &lpuart5;
  69                 sysclk = &sysclk;
  70         };
  71
  72         cpus {
  73                 #address-cells = <1>;
  74                 #size-cells = <0>;
  75
  76                 cpu0: cpu@f00 {
  77                         compatible = "arm,cortex-a7";
  78                         device_type = "cpu";
  79                         reg = <0xf00>;
  80                         clocks = <&clockgen 1 0>;
  81                         #cooling-cells = <2>;
  82                 };
  83
  84                 cpu1: cpu@f01 {
  85                         compatible = "arm,cortex-a7";
  86                         device_type = "cpu";
  87                         reg = <0xf01>;
  88                         clocks = <&clockgen 1 0>;
  89                         #cooling-cells = <2>;
  90                 };
  91         };
  92
  93         memory {
  94                 device_type = "memory";
  95                 reg = <0x0 0x0 0x0 0x0>;
  96         };
  97
  98         sysclk: sysclk {
  99                 compatible = "fixed-clock";
 100                 #clock-cells = <0>;
 101                 clock-frequency = <100000000>;
 102                 clock-output-names = "sysclk";
 103         };
 104
 105         timer {
 106                 compatible = "arm,armv7-timer";
 107                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 108                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 109                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 110                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 111         };
 112
 113         pmu {
 114                 compatible = "arm,cortex-a7-pmu";
 115                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 116                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 117                 interrupt-affinity = <&cpu0>, <&cpu1>;
 118         };
 119
 120         reboot {
 121                 compatible = "syscon-reboot";
 122                 regmap = <&dcfg>;
 123                 offset = <0xb0>;
 124                 mask = <0x02>;
 125         };
 126
 127         soc {
 128                 compatible = "simple-bus";
 129                 #address-cells = <2>;
 130                 #size-cells = <2>;
 131                 device_type = "soc";
 132                 interrupt-parent = <&gic>;
 133                 ranges;
 134
 135                 ddr: memory-controller@1080000 {
 136                         compatible = "fsl,qoriq-memory-controller";
 137                         reg = <0x0 0x1080000 0x0 0x1000>;
 138                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 139                         big-endian;
 140                 };
 141
 142                 gic: interrupt-controller@1400000 {
 143                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
 144                         #interrupt-cells = <3>;
 145                         interrupt-controller;
 146                         reg = <0x0 0x1401000 0x0 0x1000>,
 147                               <0x0 0x1402000 0x0 0x2000>,
 148                               <0x0 0x1404000 0x0 0x2000>,
 149                               <0x0 0x1406000 0x0 0x2000>;
 150                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 151
 152                 };
 153
 154                 msi1: msi-controller@1570e00 {
 155                         compatible = "fsl,ls1021a-msi";
 156                         reg = <0x0 0x1570e00 0x0 0x8>;
 157                         msi-controller;
 158                         interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 159                 };
 160
 161                 msi2: msi-controller@1570e08 {
 162                         compatible = "fsl,ls1021a-msi";
 163                         reg = <0x0 0x1570e08 0x0 0x8>;
 164                         msi-controller;
 165                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 166                 };
 167
 168                 ifc: ifc@1530000 {
 169                         compatible = "fsl,ifc", "simple-bus";
 170                         reg = <0x0 0x1530000 0x0 0x10000>;
 171                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 172                 };
 173
 174                 dcfg: dcfg@1ee0000 {
 175                         compatible = "fsl,ls1021a-dcfg", "syscon";
 176                         reg = <0x0 0x1ee0000 0x0 0x1000>;
 177                         big-endian;
 178                 };
 179
 180                 qspi: spi@1550000 {
 181                         compatible = "fsl,ls1021a-qspi";
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         reg = <0x0 0x1550000 0x0 0x10000>,
 185                               <0x0 0x40000000 0x0 0x20000000>;
 186                         reg-names = "QuadSPI", "QuadSPI-memory";
 187                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 188                         clock-names = "qspi_en", "qspi";
 189                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 190                         status = "disabled";
 191                 };
 192
 193                 esdhc: esdhc@1560000 {
 194                         compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
 195                         reg = <0x0 0x1560000 0x0 0x10000>;
 196                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 197                         clock-frequency = <0>;
 198                         voltage-ranges = <1800 1800 3300 3300>;
 199                         sdhci,auto-cmd12;
 200                         big-endian;
 201                         bus-width = <4>;
 202                         status = "disabled";
 203                 };
 204
 205                 sata: sata@3200000 {
 206                         compatible = "fsl,ls1021a-ahci";
 207                         reg = <0x0 0x3200000 0x0 0x10000>,
 208                               <0x0 0x20220520 0x0 0x4>;
 209                         reg-names = "ahci", "sata-ecc";
 210                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 211                         clocks = <&clockgen 4 1>;
 212                         dma-coherent;
 213                         status = "disabled";
 214                 };
 215
 216                 scfg: scfg@1570000 {
 217                         compatible = "fsl,ls1021a-scfg", "syscon";
 218                         reg = <0x0 0x1570000 0x0 0x10000>;
 219                         big-endian;
 220                         #address-cells = <1>;
 221                         #size-cells = <1>;
 222                         ranges = <0x0 0x0 0x1570000 0x10000>;
 223
 224                         extirq: interrupt-controller@1ac {
 225                                 compatible = "fsl,ls1021a-extirq";
 226                                 #interrupt-cells = <2>;
 227                                 #address-cells = <0>;
 228                                 interrupt-controller;
 229                                 reg = <0x1ac 4>;
 230                                 interrupt-map =
 231                                         <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 232                                         <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 233                                         <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 234                                         <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 235                                         <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 236                                         <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 237                                 interrupt-map-mask = <0xffffffff 0x0>;
 238                         };
 239                 };
 240
 241                 crypto: crypto@1700000 {
 242                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 243                         fsl,sec-era = <7>;
 244                         #address-cells = <1>;
 245                         #size-cells = <1>;
 246                         reg              = <0x0 0x1700000 0x0 0x100000>;
 247                         ranges           = <0x0 0x0 0x1700000 0x100000>;
 248                         interrupts       = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 249
 250                         sec_jr0: jr@10000 {
 251                                 compatible = "fsl,sec-v5.0-job-ring",
 252                                      "fsl,sec-v4.0-job-ring";
 253                                 reg = <0x10000 0x10000>;
 254                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 255                         };
 256
 257                         sec_jr1: jr@20000 {
 258                                 compatible = "fsl,sec-v5.0-job-ring",
 259                                      "fsl,sec-v4.0-job-ring";
 260                                 reg = <0x20000 0x10000>;
 261                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 262                         };
 263
 264                         sec_jr2: jr@30000 {
 265                                 compatible = "fsl,sec-v5.0-job-ring",
 266                                      "fsl,sec-v4.0-job-ring";
 267                                 reg = <0x30000 0x10000>;
 268                                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 269                         };
 270
 271                         sec_jr3: jr@40000 {
 272                                 compatible = "fsl,sec-v5.0-job-ring",
 273                                      "fsl,sec-v4.0-job-ring";
 274                                 reg = <0x40000 0x10000>;
 275                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 276                         };
 277
 278                 };
 279
 280                 clockgen: clocking@1ee1000 {
 281                         compatible = "fsl,ls1021a-clockgen";
 282                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 283                         #clock-cells = <2>;
 284                         clocks = <&sysclk>;
 285                 };
 286
 287                 tmu: tmu@1f00000 {
 288                         compatible = "fsl,qoriq-tmu";
 289                         reg = <0x0 0x1f00000 0x0 0x10000>;
 290                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 291                         fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
 292                         fsl,tmu-calibration = <0x00000000 0x00000020
 293                                                0x00000001 0x00000024
 294                                                0x00000002 0x0000002a
 295                                                0x00000003 0x00000032
 296                                                0x00000004 0x00000038
 297                                                0x00000005 0x0000003e
 298                                                0x00000006 0x00000043
 299                                                0x00000007 0x0000004a
 300                                                0x00000008 0x00000050
 301                                                0x00000009 0x00000059
 302                                                0x0000000a 0x0000005f
 303                                                0x0000000b 0x00000066
 304
 305                                                0x00010000 0x00000023
 306                                                0x00010001 0x0000002b
 307                                                0x00010002 0x00000033
 308                                                0x00010003 0x0000003a
 309                                                0x00010004 0x00000042
 310                                                0x00010005 0x0000004a
 311                                                0x00010006 0x00000054
 312                                                0x00010007 0x0000005c
 313                                                0x00010008 0x00000065
 314                                                0x00010009 0x0000006f
 315
 316                                                0x00020000 0x00000029
 317                                                0x00020001 0x00000033
 318                                                0x00020002 0x0000003d
 319                                                0x00020003 0x00000048
 320                                                0x00020004 0x00000054
 321                                                0x00020005 0x00000060
 322                                                0x00020006 0x0000006c
 323
 324                                                0x00030000 0x00000025
 325                                                0x00030001 0x00000033
 326                                                0x00030002 0x00000043
 327                                                0x00030003 0x00000055>;
 328                         #thermal-sensor-cells = <1>;
 329                 };
 330
 331                 thermal-zones {
 332                         cpu_thermal: cpu-thermal {
 333                                 polling-delay-passive = <1000>;
 334                                 polling-delay = <5000>;
 335
 336                                 thermal-sensors = <&tmu 0>;
 337
 338                                 trips {
 339                                         cpu_alert: cpu-alert {
 340                                                 temperature = <85000>;
 341                                                 hysteresis = <2000>;
 342                                                 type = "passive";
 343                                         };
 344                                         cpu_crit: cpu-crit {
 345                                                 temperature = <95000>;
 346                                                 hysteresis = <2000>;
 347                                                 type = "critical";
 348                                         };
 349                                 };
 350
 351                                 cooling-maps {
 352                                         map0 {
 353                                                 trip = <&cpu_alert>;
 354                                                 cooling-device =
 355                                                         <&cpu0 THERMAL_NO_LIMIT
 356                                                         THERMAL_NO_LIMIT>,
 357                                                         <&cpu1 THERMAL_NO_LIMIT
 358                                                         THERMAL_NO_LIMIT>;
 359                                         };
 360                                 };
 361                         };
 362                 };
 363
 364                 dspi0: spi@2100000 {
 365                         compatible = "fsl,ls1021a-v1.0-dspi";
 366                         #address-cells = <1>;
 367                         #size-cells = <0>;
 368                         reg = <0x0 0x2100000 0x0 0x10000>;
 369                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 370                         clock-names = "dspi";
 371                         clocks = <&clockgen 4 1>;
 372                         spi-num-chipselects = <6>;
 373                         big-endian;
 374                         status = "disabled";
 375                 };
 376
 377                 dspi1: spi@2110000 {
 378                         compatible = "fsl,ls1021a-v1.0-dspi";
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         reg = <0x0 0x2110000 0x0 0x10000>;
 382                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 383                         clock-names = "dspi";
 384                         clocks = <&clockgen 4 1>;
 385                         spi-num-chipselects = <6>;
 386                         big-endian;
 387                         status = "disabled";
 388                 };
 389
 390                 i2c0: i2c@2180000 {
 391                         compatible = "fsl,vf610-i2c";
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                         reg = <0x0 0x2180000 0x0 0x10000>;
 395                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 396                         clock-names = "i2c";
 397                         clocks = <&clockgen 4 1>;
 398                         dma-names = "tx", "rx";
 399                         dmas = <&edma0 1 39>, <&edma0 1 38>;
 400                         status = "disabled";
 401                 };
 402
 403                 i2c1: i2c@2190000 {
 404                         compatible = "fsl,vf610-i2c";
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                         reg = <0x0 0x2190000 0x0 0x10000>;
 408                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 409                         clock-names = "i2c";
 410                         clocks = <&clockgen 4 1>;
 411                         dma-names = "tx", "rx";
 412                         dmas = <&edma0 1 37>, <&edma0 1 36>;
 413                         status = "disabled";
 414                 };
 415
 416                 i2c2: i2c@21a0000 {
 417                         compatible = "fsl,vf610-i2c";
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         reg = <0x0 0x21a0000 0x0 0x10000>;
 421                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 422                         clock-names = "i2c";
 423                         clocks = <&clockgen 4 1>;
 424                         dma-names = "tx", "rx";
 425                         dmas = <&edma0 1 35>, <&edma0 1 34>;
 426                         status = "disabled";
 427                 };
 428
 429                 uart0: serial@21c0500 {
 430                         compatible = "fsl,16550-FIFO64", "ns16550a";
 431                         reg = <0x0 0x21c0500 0x0 0x100>;
 432                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 433                         clock-frequency = <0>;
 434                         fifo-size = <15>;
 435                         status = "disabled";
 436                 };
 437
 438                 uart1: serial@21c0600 {
 439                         compatible = "fsl,16550-FIFO64", "ns16550a";
 440                         reg = <0x0 0x21c0600 0x0 0x100>;
 441                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 442                         clock-frequency = <0>;
 443                         fifo-size = <15>;
 444                         status = "disabled";
 445                 };
 446
 447                 uart2: serial@21d0500 {
 448                         compatible = "fsl,16550-FIFO64", "ns16550a";
 449                         reg = <0x0 0x21d0500 0x0 0x100>;
 450                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 451                         clock-frequency = <0>;
 452                         fifo-size = <15>;
 453                         status = "disabled";
 454                 };
 455
 456                 uart3: serial@21d0600 {
 457                         compatible = "fsl,16550-FIFO64", "ns16550a";
 458                         reg = <0x0 0x21d0600 0x0 0x100>;
 459                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 460                         clock-frequency = <0>;
 461                         fifo-size = <15>;
 462                         status = "disabled";
 463                 };
 464
 465                 counter0: counter@29d0000 {
 466                         compatible = "fsl,ftm-quaddec";
 467                         reg = <0x0 0x29d0000 0x0 0x10000>;
 468                         big-endian;
 469                         status = "disabled";
 470                 };
 471
 472                 counter1: counter@29e0000 {
 473                         compatible = "fsl,ftm-quaddec";
 474                         reg = <0x0 0x29e0000 0x0 0x10000>;
 475                         big-endian;
 476                         status = "disabled";
 477                 };
 478
 479                 counter2: counter@29f0000 {
 480                         compatible = "fsl,ftm-quaddec";
 481                         reg = <0x0 0x29f0000 0x0 0x10000>;
 482                         big-endian;
 483                         status = "disabled";
 484                 };
 485
 486                 counter3: counter@2a00000 {
 487                         compatible = "fsl,ftm-quaddec";
 488                         reg = <0x0 0x2a00000 0x0 0x10000>;
 489                         big-endian;
 490                         status = "disabled";
 491                 };
 492
 493                 gpio0: gpio@2300000 {
 494                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 495                         reg = <0x0 0x2300000 0x0 0x10000>;
 496                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 497                         gpio-controller;
 498                         #gpio-cells = <2>;
 499                         interrupt-controller;
 500                         #interrupt-cells = <2>;
 501                 };
 502
 503                 gpio1: gpio@2310000 {
 504                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 505                         reg = <0x0 0x2310000 0x0 0x10000>;
 506                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 507                         gpio-controller;
 508                         #gpio-cells = <2>;
 509                         interrupt-controller;
 510                         #interrupt-cells = <2>;
 511                 };
 512
 513                 gpio2: gpio@2320000 {
 514                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 515                         reg = <0x0 0x2320000 0x0 0x10000>;
 516                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 517                         gpio-controller;
 518                         #gpio-cells = <2>;
 519                         interrupt-controller;
 520                         #interrupt-cells = <2>;
 521                 };
 522
 523                 gpio3: gpio@2330000 {
 524                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 525                         reg = <0x0 0x2330000 0x0 0x10000>;
 526                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 527                         gpio-controller;
 528                         #gpio-cells = <2>;
 529                         interrupt-controller;
 530                         #interrupt-cells = <2>;
 531                 };
 532
 533                 lpuart0: serial@2950000 {
 534                         compatible = "fsl,ls1021a-lpuart";
 535                         reg = <0x0 0x2950000 0x0 0x1000>;
 536                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 537                         clocks = <&sysclk>;
 538                         clock-names = "ipg";
 539                         status = "disabled";
 540                 };
 541
 542                 lpuart1: serial@2960000 {
 543                         compatible = "fsl,ls1021a-lpuart";
 544                         reg = <0x0 0x2960000 0x0 0x1000>;
 545                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 546                         clocks = <&clockgen 4 1>;
 547                         clock-names = "ipg";
 548                         status = "disabled";
 549                 };
 550
 551                 lpuart2: serial@2970000 {
 552                         compatible = "fsl,ls1021a-lpuart";
 553                         reg = <0x0 0x2970000 0x0 0x1000>;
 554                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 555                         clocks = <&clockgen 4 1>;
 556                         clock-names = "ipg";
 557                         status = "disabled";
 558                 };
 559
 560                 lpuart3: serial@2980000 {
 561                         compatible = "fsl,ls1021a-lpuart";
 562                         reg = <0x0 0x2980000 0x0 0x1000>;
 563                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&clockgen 4 1>;
 565                         clock-names = "ipg";
 566                         status = "disabled";
 567                 };
 568
 569                 lpuart4: serial@2990000 {
 570                         compatible = "fsl,ls1021a-lpuart";
 571                         reg = <0x0 0x2990000 0x0 0x1000>;
 572                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 573                         clocks = <&clockgen 4 1>;
 574                         clock-names = "ipg";
 575                         status = "disabled";
 576                 };
 577
 578                 lpuart5: serial@29a0000 {
 579                         compatible = "fsl,ls1021a-lpuart";
 580                         reg = <0x0 0x29a0000 0x0 0x1000>;
 581                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 582                         clocks = <&clockgen 4 1>;
 583                         clock-names = "ipg";
 584                         status = "disabled";
 585                 };
 586
 587                 pwm0: pwm@29d0000 {
 588                         compatible = "fsl,vf610-ftm-pwm";
 589                         #pwm-cells = <3>;
 590                         reg = <0x0 0x29d0000 0x0 0x10000>;
 591                         clock-names = "ftm_sys", "ftm_ext",
 592                                 "ftm_fix", "ftm_cnt_clk_en";
 593                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 594                                 <&clockgen 4 1>, <&clockgen 4 1>;
 595                         big-endian;
 596                         status = "disabled";
 597                 };
 598
 599                 pwm1: pwm@29e0000 {
 600                         compatible = "fsl,vf610-ftm-pwm";
 601                         #pwm-cells = <3>;
 602                         reg = <0x0 0x29e0000 0x0 0x10000>;
 603                         clock-names = "ftm_sys", "ftm_ext",
 604                                 "ftm_fix", "ftm_cnt_clk_en";
 605                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 606                                 <&clockgen 4 1>, <&clockgen 4 1>;
 607                         big-endian;
 608                         status = "disabled";
 609                 };
 610
 611                 pwm2: pwm@29f0000 {
 612                         compatible = "fsl,vf610-ftm-pwm";
 613                         #pwm-cells = <3>;
 614                         reg = <0x0 0x29f0000 0x0 0x10000>;
 615                         clock-names = "ftm_sys", "ftm_ext",
 616                                 "ftm_fix", "ftm_cnt_clk_en";
 617                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 618                                 <&clockgen 4 1>, <&clockgen 4 1>;
 619                         big-endian;
 620                         status = "disabled";
 621                 };
 622
 623                 pwm3: pwm@2a00000 {
 624                         compatible = "fsl,vf610-ftm-pwm";
 625                         #pwm-cells = <3>;
 626                         reg = <0x0 0x2a00000 0x0 0x10000>;
 627                         clock-names = "ftm_sys", "ftm_ext",
 628                                 "ftm_fix", "ftm_cnt_clk_en";
 629                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 630                                 <&clockgen 4 1>, <&clockgen 4 1>;
 631                         big-endian;
 632                         status = "disabled";
 633                 };
 634
 635                 pwm4: pwm@2a10000 {
 636                         compatible = "fsl,vf610-ftm-pwm";
 637                         #pwm-cells = <3>;
 638                         reg = <0x0 0x2a10000 0x0 0x10000>;
 639                         clock-names = "ftm_sys", "ftm_ext",
 640                                 "ftm_fix", "ftm_cnt_clk_en";
 641                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 642                                 <&clockgen 4 1>, <&clockgen 4 1>;
 643                         big-endian;
 644                         status = "disabled";
 645                 };
 646
 647                 pwm5: pwm@2a20000 {
 648                         compatible = "fsl,vf610-ftm-pwm";
 649                         #pwm-cells = <3>;
 650                         reg = <0x0 0x2a20000 0x0 0x10000>;
 651                         clock-names = "ftm_sys", "ftm_ext",
 652                                 "ftm_fix", "ftm_cnt_clk_en";
 653                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 654                                 <&clockgen 4 1>, <&clockgen 4 1>;
 655                         big-endian;
 656                         status = "disabled";
 657                 };
 658
 659                 pwm6: pwm@2a30000 {
 660                         compatible = "fsl,vf610-ftm-pwm";
 661                         #pwm-cells = <3>;
 662                         reg = <0x0 0x2a30000 0x0 0x10000>;
 663                         clock-names = "ftm_sys", "ftm_ext",
 664                                 "ftm_fix", "ftm_cnt_clk_en";
 665                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 666                                 <&clockgen 4 1>, <&clockgen 4 1>;
 667                         big-endian;
 668                         status = "disabled";
 669                 };
 670
 671                 pwm7: pwm@2a40000 {
 672                         compatible = "fsl,vf610-ftm-pwm";
 673                         #pwm-cells = <3>;
 674                         reg = <0x0 0x2a40000 0x0 0x10000>;
 675                         clock-names = "ftm_sys", "ftm_ext",
 676                                 "ftm_fix", "ftm_cnt_clk_en";
 677                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 678                                 <&clockgen 4 1>, <&clockgen 4 1>;
 679                         big-endian;
 680                         status = "disabled";
 681                 };
 682
 683                 wdog0: watchdog@2ad0000 {
 684                         compatible = "fsl,imx21-wdt";
 685                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 686                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 687                         clocks = <&clockgen 4 1>;
 688                         clock-names = "wdog-en";
 689                         big-endian;
 690                 };
 691
 692                 sai1: sai@2b50000 {
 693                         #sound-dai-cells = <0>;
 694                         compatible = "fsl,vf610-sai";
 695                         reg = <0x0 0x2b50000 0x0 0x10000>;
 696                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 697                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 698                                  <&clockgen 4 1>, <&clockgen 4 1>;
 699                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 700                         dma-names = "tx", "rx";
 701                         dmas = <&edma0 1 47>,
 702                                <&edma0 1 46>;
 703                         status = "disabled";
 704                 };
 705
 706                 sai2: sai@2b60000 {
 707                         #sound-dai-cells = <0>;
 708                         compatible = "fsl,vf610-sai";
 709                         reg = <0x0 0x2b60000 0x0 0x10000>;
 710                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 711                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 712                                  <&clockgen 4 1>, <&clockgen 4 1>;
 713                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 714                         dma-names = "tx", "rx";
 715                         dmas = <&edma0 1 45>,
 716                                <&edma0 1 44>;
 717                         status = "disabled";
 718                 };
 719
 720                 edma0: edma@2c00000 {
 721                         #dma-cells = <2>;
 722                         compatible = "fsl,vf610-edma";
 723                         reg = <0x0 0x2c00000 0x0 0x10000>,
 724                               <0x0 0x2c10000 0x0 0x10000>,
 725                               <0x0 0x2c20000 0x0 0x10000>;
 726                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 727                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 728                         interrupt-names = "edma-tx", "edma-err";
 729                         dma-channels = <32>;
 730                         big-endian;
 731                         clock-names = "dmamux0", "dmamux1";
 732                         clocks = <&clockgen 4 1>,
 733                                  <&clockgen 4 1>;
 734                 };
 735
 736                 dcu: dcu@2ce0000 {
 737                         compatible = "fsl,ls1021a-dcu";
 738                         reg = <0x0 0x2ce0000 0x0 0x10000>;
 739                         interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 740                         clocks = <&clockgen 4 0>,
 741                                 <&clockgen 4 0>;
 742                         clock-names = "dcu", "pix";
 743                         big-endian;
 744                         status = "disabled";
 745                 };
 746
 747                 mdio0: mdio@2d24000 {
 748                         compatible = "gianfar";
 749                         device_type = "mdio";
 750                         #address-cells = <1>;
 751                         #size-cells = <0>;
 752                         reg = <0x0 0x2d24000 0x0 0x4000>,
 753                               <0x0 0x2d10030 0x0 0x4>;
 754                 };
 755
 756                 mdio1: mdio@2d64000 {
 757                         compatible = "gianfar";
 758                         device_type = "mdio";
 759                         #address-cells = <1>;
 760                         #size-cells = <0>;
 761                         reg = <0x0 0x2d64000 0x0 0x4000>,
 762                               <0x0 0x2d50030 0x0 0x4>;
 763                 };
 764
 765                 ptp_clock@2d10e00 {
 766                         compatible = "fsl,etsec-ptp";
 767                         reg = <0x0 0x2d10e00 0x0 0xb0>;
 768                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 769                         fsl,tclk-period = <5>;
 770                         fsl,tmr-prsc    = <2>;
 771                         fsl,tmr-add     = <0xaaaaaaab>;
 772                         fsl,tmr-fiper1  = <999999995>;
 773                         fsl,tmr-fiper2  = <999999995>;
 774                         fsl,max-adj     = <499999999>;
 775                         fsl,extts-fifo;
 776                 };
 777
 778                 enet0: ethernet@2d10000 {
 779                         compatible = "fsl,etsec2";
 780                         device_type = "network";
 781                         #address-cells = <2>;
 782                         #size-cells = <2>;
 783                         interrupt-parent = <&gic>;
 784                         model = "eTSEC";
 785                         fsl,magic-packet;
 786                         ranges;
 787                         dma-coherent;
 788
 789                         queue-group@2d10000 {
 790                                 #address-cells = <2>;
 791                                 #size-cells = <2>;
 792                                 reg = <0x0 0x2d10000 0x0 0x1000>;
 793                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 794                                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 795                                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 796                         };
 797
 798                         queue-group@2d14000  {
 799                                 #address-cells = <2>;
 800                                 #size-cells = <2>;
 801                                 reg = <0x0 0x2d14000 0x0 0x1000>;
 802                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 803                                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 804                                         <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 805                         };
 806                 };
 807
 808                 enet1: ethernet@2d50000 {
 809                         compatible = "fsl,etsec2";
 810                         device_type = "network";
 811                         #address-cells = <2>;
 812                         #size-cells = <2>;
 813                         interrupt-parent = <&gic>;
 814                         model = "eTSEC";
 815                         ranges;
 816                         dma-coherent;
 817
 818                         queue-group@2d50000  {
 819                                 #address-cells = <2>;
 820                                 #size-cells = <2>;
 821                                 reg = <0x0 0x2d50000 0x0 0x1000>;
 822                                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 823                                         <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 824                                         <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 825                         };
 826
 827                         queue-group@2d54000  {
 828                                 #address-cells = <2>;
 829                                 #size-cells = <2>;
 830                                 reg = <0x0 0x2d54000 0x0 0x1000>;
 831                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 832                                         <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 833                                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 834                         };
 835                 };
 836
 837                 enet2: ethernet@2d90000 {
 838                         compatible = "fsl,etsec2";
 839                         device_type = "network";
 840                         #address-cells = <2>;
 841                         #size-cells = <2>;
 842                         interrupt-parent = <&gic>;
 843                         model = "eTSEC";
 844                         ranges;
 845                         dma-coherent;
 846
 847                         queue-group@2d90000  {
 848                                 #address-cells = <2>;
 849                                 #size-cells = <2>;
 850                                 reg = <0x0 0x2d90000 0x0 0x1000>;
 851                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 852                                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 853                                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 854                         };
 855
 856                         queue-group@2d94000  {
 857                                 #address-cells = <2>;
 858                                 #size-cells = <2>;
 859                                 reg = <0x0 0x2d94000 0x0 0x1000>;
 860                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 861                                         <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 862                                         <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 863                         };
 864                 };
 865
 866                 usb2: usb@8600000 {
 867                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 868                         reg = <0x0 0x8600000 0x0 0x1000>;
 869                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 870                         dr_mode = "host";
 871                         phy_type = "ulpi";
 872                 };
 873
 874                 usb3: usb3@3100000 {
 875                         compatible = "snps,dwc3";
 876                         reg = <0x0 0x3100000 0x0 0x10000>;
 877                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 878                         dr_mode = "host";
 879                         snps,quirk-frame-length-adjustment = <0x20>;
 880                         snps,dis_rxdet_inp3_quirk;
 881                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 882                 };
 883
 884                 pcie@3400000 {
 885                         compatible = "fsl,ls1021a-pcie";
 886                         reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 887                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 888                         reg-names = "regs", "config";
 889                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 890                         fsl,pcie-scfg = <&scfg 0>;
 891                         #address-cells = <3>;
 892                         #size-cells = <2>;
 893                         device_type = "pci";
 894                         num-viewport = <6>;
 895                         bus-range = <0x0 0xff>;
 896                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 897                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 898                         msi-parent = <&msi1>, <&msi2>;
 899                         #interrupt-cells = <1>;
 900                         interrupt-map-mask = <0 0 0 7>;
 901                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
 902                                         <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 903                                         <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 904                                         <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 905                         status = "disabled";
 906                 };
 907
 908                 pcie@3500000 {
 909                         compatible = "fsl,ls1021a-pcie";
 910                         reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
 911                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 912                         reg-names = "regs", "config";
 913                         interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 914                         fsl,pcie-scfg = <&scfg 1>;
 915                         #address-cells = <3>;
 916                         #size-cells = <2>;
 917                         device_type = "pci";
 918                         num-viewport = <6>;
 919                         bus-range = <0x0 0xff>;
 920                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 921                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 922                         msi-parent = <&msi1>, <&msi2>;
 923                         #interrupt-cells = <1>;
 924                         interrupt-map-mask = <0 0 0 7>;
 925                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
 926                                         <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 927                                         <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 928                                         <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 929                         status = "disabled";
 930                 };
 931
 932                 can0: can@2a70000 {
 933                         compatible = "fsl,ls1021ar2-flexcan";
 934                         reg = <0x0 0x2a70000 0x0 0x1000>;
 935                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 936                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 937                         clock-names = "ipg", "per";
 938                         big-endian;
 939                 };
 940
 941                 can1: can@2a80000 {
 942                         compatible = "fsl,ls1021ar2-flexcan";
 943                         reg = <0x0 0x2a80000 0x0 0x1000>;
 944                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 945                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 946                         clock-names = "ipg", "per";
 947                         big-endian;
 948                 };
 949
 950                 can2: can@2a90000 {
 951                         compatible = "fsl,ls1021ar2-flexcan";
 952                         reg = <0x0 0x2a90000 0x0 0x1000>;
 953                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 954                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 955                         clock-names = "ipg", "per";
 956                         big-endian;
 957                 };
 958
 959                 can3: can@2aa0000 {
 960                         compatible = "fsl,ls1021ar2-flexcan";
 961                         reg = <0x0 0x2aa0000 0x0 0x1000>;
 962                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 963                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 964                         clock-names = "ipg", "per";
 965                         big-endian;
 966                 };
 967
 968                 ocram1: sram@10000000 {
 969                         compatible = "mmio-sram";
 970                         reg = <0x0 0x10000000 0x0 0x10000>;
 971                         #address-cells = <1>;
 972                         #size-cells = <1>;
 973                         ranges = <0x0 0x0 0x10000000 0x10000>;
 974                 };
 975
 976                 ocram2: sram@10010000 {
 977                         compatible = "mmio-sram";
 978                         reg = <0x0 0x10010000 0x0 0x10000>;
 979                         #address-cells = <1>;
 980                         #size-cells = <1>;
 981                         ranges = <0x0 0x0 0x10010000 0x10000>;
 982                 };
 983
 984                 qdma: dma-controller@8390000 {
 985                         compatible = "fsl,ls1021a-qdma";
 986                         reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
 987                               <0x0 0x8389000 0x0 0x1000>, /* Status regs */
 988                               <0x0 0x838a000 0x0 0x2000>; /* Block regs */
 989                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 990                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 991                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 992                         interrupt-names = "qdma-error",
 993                                 "qdma-queue0", "qdma-queue1";
 994                         dma-channels = <8>;
 995                         block-number = <1>;
 996                         block-offset = <0x1000>;
 997                         fsl,dma-queues = <2>;
 998                         status-sizes = <64>;
 999                         queue-sizes = <64 64>;
1000                         big-endian;
1001                 };
1002
1003                 rcpm: power-controller@1ee2140 {
1004                         compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
1005                         reg = <0x0 0x1ee2140 0x0 0x8>;
1006                         #fsl,rcpm-wakeup-cells = <2>;
1007                 };
1008
1009                 ftm_alarm0: timer0@29d0000 {
1010                         compatible = "fsl,ls1021a-ftm-alarm";
1011                         reg = <0x0 0x29d0000 0x0 0x10000>;
1012                         reg-names = "ftm";
1013                         fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
1014                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1015                         big-endian;
1016                 };
1017         };
1018 };