arch/arm/boot/dts/imx6qdl-gw5904.dtsi

   1 /*
   2  * Copyright 2017 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/input/linux-event-codes.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51
  52 / {
  53         /* these are used by bootloader for disabling nodes */
  54         aliases {
  55                 led0 = &led0;
  56                 led1 = &led1;
  57                 led2 = &led2;
  58                 usb0 = &usbh1;
  59                 usb1 = &usbotg;
  60         };
  61
  62         chosen {
  63                 stdout-path = &uart2;
  64         };
  65
  66         backlight {
  67                 compatible = "pwm-backlight";
  68                 pwms = <&pwm4 0 5000000>;
  69                 brightness-levels = <0 4 8 16 32 64 128 255>;
  70                 default-brightness-level = <7>;
  71         };
  72
  73         gpio-keys {
  74                 compatible = "gpio-keys";
  75
  76                 user-pb {
  77                         label = "user_pb";
  78                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  79                         linux,code = <BTN_0>;
  80                 };
  81
  82                 user-pb1x {
  83                         label = "user_pb1x";
  84                         linux,code = <BTN_1>;
  85                         interrupt-parent = <&gsc>;
  86                         interrupts = <0>;
  87                 };
  88
  89                 key-erased {
  90                         label = "key-erased";
  91                         linux,code = <BTN_2>;
  92                         interrupt-parent = <&gsc>;
  93                         interrupts = <1>;
  94                 };
  95
  96                 eeprom-wp {
  97                         label = "eeprom_wp";
  98                         linux,code = <BTN_3>;
  99                         interrupt-parent = <&gsc>;
 100                         interrupts = <2>;
 101                 };
 102
 103                 tamper {
 104                         label = "tamper";
 105                         linux,code = <BTN_4>;
 106                         interrupt-parent = <&gsc>;
 107                         interrupts = <5>;
 108                 };
 109
 110                 switch-hold {
 111                         label = "switch_hold";
 112                         linux,code = <BTN_5>;
 113                         interrupt-parent = <&gsc>;
 114                         interrupts = <7>;
 115                 };
 116         };
 117
 118         leds {
 119                 compatible = "gpio-leds";
 120                 pinctrl-names = "default";
 121                 pinctrl-0 = <&pinctrl_gpio_leds>;
 122
 123                 led0: user1 {
 124                         label = "user1";
 125                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
 126                         default-state = "on";
 127                         linux,default-trigger = "heartbeat";
 128                 };
 129
 130                 led1: user2 {
 131                         label = "user2";
 132                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
 133                         default-state = "off";
 134                 };
 135
 136                 led2: user3 {
 137                         label = "user3";
 138                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
 139                         default-state = "off";
 140                 };
 141         };
 142
 143         memory@10000000 {
 144                 device_type = "memory";
 145                 reg = <0x10000000 0x40000000>;
 146         };
 147
 148         pps {
 149                 compatible = "pps-gpio";
 150                 pinctrl-names = "default";
 151                 pinctrl-0 = <&pinctrl_pps>;
 152                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 153         };
 154
 155         reg_1p0v: regulator-1p0v {
 156                 compatible = "regulator-fixed";
 157                 regulator-name = "1P0V";
 158                 regulator-min-microvolt = <1000000>;
 159                 regulator-max-microvolt = <1000000>;
 160                 regulator-always-on;
 161         };
 162
 163         reg_3p3v: regulator-3p3v {
 164                 compatible = "regulator-fixed";
 165                 regulator-name = "3P3V";
 166                 regulator-min-microvolt = <3300000>;
 167                 regulator-max-microvolt = <3300000>;
 168                 regulator-always-on;
 169         };
 170
 171         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 172                 compatible = "regulator-fixed";
 173                 regulator-name = "usb_h1_vbus";
 174                 regulator-min-microvolt = <5000000>;
 175                 regulator-max-microvolt = <5000000>;
 176                 regulator-always-on;
 177         };
 178
 179         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 180                 compatible = "regulator-fixed";
 181                 regulator-name = "usb_otg_vbus";
 182                 regulator-min-microvolt = <5000000>;
 183                 regulator-max-microvolt = <5000000>;
 184                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 185                 enable-active-high;
 186         };
 187 };
 188
 189 &clks {
 190         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 191                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 192         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 193                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 194 };
 195
 196 &fec {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_enet>;
 199         phy-mode = "rgmii-id";
 200         status = "okay";
 201
 202         fixed-link {
 203                 speed = <1000>;
 204                 full-duplex;
 205         };
 206
 207         mdio {
 208                 #address-cells = <1>;
 209                 #size-cells = <0>;
 210
 211                 switch@0 {
 212                         compatible = "marvell,mv88e6085";
 213                         reg = <0>;
 214
 215                         ports {
 216                                 #address-cells = <1>;
 217                                 #size-cells = <0>;
 218
 219                                 port@0 {
 220                                         reg = <0>;
 221                                         label = "lan4";
 222                                 };
 223
 224                                 port@1 {
 225                                         reg = <1>;
 226                                         label = "lan3";
 227                                 };
 228
 229                                 port@2 {
 230                                         reg = <2>;
 231                                         label = "lan2";
 232                                 };
 233
 234                                 port@3 {
 235                                         reg = <3>;
 236                                         label = "lan1";
 237                                 };
 238
 239                                 port@5 {
 240                                         reg = <5>;
 241                                         label = "cpu";
 242                                         ethernet = <&fec>;
 243                                 };
 244                         };
 245                 };
 246         };
 247 };
 248
 249 &i2c1 {
 250         clock-frequency = <100000>;
 251         pinctrl-names = "default";
 252         pinctrl-0 = <&pinctrl_i2c1>;
 253         status = "okay";
 254
 255         gsc: gsc@20 {
 256                 compatible = "gw,gsc";
 257                 reg = <0x20>;
 258                 interrupt-parent = <&gpio1>;
 259                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 260                 interrupt-controller;
 261                 #interrupt-cells = <1>;
 262                 #size-cells = <0>;
 263
 264                 adc {
 265                         compatible = "gw,gsc-adc";
 266                         #address-cells = <1>;
 267                         #size-cells = <0>;
 268
 269                         channel@0 {
 270                                 gw,mode = <0>;
 271                                 reg = <0x00>;
 272                                 label = "temp";
 273                         };
 274
 275                         channel@2 {
 276                                 gw,mode = <1>;
 277                                 reg = <0x02>;
 278                                 label = "vdd_vin";
 279                         };
 280
 281                         channel@5 {
 282                                 gw,mode = <1>;
 283                                 reg = <0x05>;
 284                                 label = "vdd_3p3";
 285                         };
 286
 287                         channel@8 {
 288                                 gw,mode = <1>;
 289                                 reg = <0x08>;
 290                                 label = "vdd_bat";
 291                         };
 292
 293                         channel@b {
 294                                 gw,mode = <1>;
 295                                 reg = <0x0b>;
 296                                 label = "vdd_5p0";
 297                         };
 298
 299                         channel@e {
 300                                 gw,mode = <1>;
 301                                 reg = <0xe>;
 302                                 label = "vdd_arm";
 303                         };
 304
 305                         channel@11 {
 306                                 gw,mode = <1>;
 307                                 reg = <0x11>;
 308                                 label = "vdd_soc";
 309                         };
 310
 311                         channel@14 {
 312                                 gw,mode = <1>;
 313                                 reg = <0x14>;
 314                                 label = "vdd_3p0";
 315                         };
 316
 317                         channel@17 {
 318                                 gw,mode = <1>;
 319                                 reg = <0x17>;
 320                                 label = "vdd_1p5";
 321                         };
 322
 323                         channel@1d {
 324                                 gw,mode = <1>;
 325                                 reg = <0x1d>;
 326                                 label = "vdd_1p8";
 327                         };
 328
 329                         channel@20 {
 330                                 gw,mode = <1>;
 331                                 reg = <0x20>;
 332                                 label = "vdd_an1";
 333                         };
 334
 335                         channel@23 {
 336                                 gw,mode = <1>;
 337                                 reg = <0x23>;
 338                                 label = "vdd_2p5";
 339                         };
 340                 };
 341         };
 342
 343         gsc_gpio: gpio@23 {
 344                 compatible = "nxp,pca9555";
 345                 reg = <0x23>;
 346                 gpio-controller;
 347                 #gpio-cells = <2>;
 348                 interrupt-parent = <&gsc>;
 349                 interrupts = <4>;
 350         };
 351
 352         eeprom1: eeprom@50 {
 353                 compatible = "atmel,24c02";
 354                 reg = <0x50>;
 355                 pagesize = <16>;
 356         };
 357
 358         eeprom2: eeprom@51 {
 359                 compatible = "atmel,24c02";
 360                 reg = <0x51>;
 361                 pagesize = <16>;
 362         };
 363
 364         eeprom3: eeprom@52 {
 365                 compatible = "atmel,24c02";
 366                 reg = <0x52>;
 367                 pagesize = <16>;
 368         };
 369
 370         eeprom4: eeprom@53 {
 371                 compatible = "atmel,24c02";
 372                 reg = <0x53>;
 373                 pagesize = <16>;
 374         };
 375
 376         dts1672: rtc@68 {
 377                 compatible = "dallas,ds1672";
 378                 reg = <0x68>;
 379         };
 380 };
 381
 382 &i2c2 {
 383         clock-frequency = <100000>;
 384         pinctrl-names = "default";
 385         pinctrl-0 = <&pinctrl_i2c2>;
 386         status = "okay";
 387
 388         magn@1c {
 389                 compatible = "st,lsm9ds1-magn";
 390                 reg = <0x1c>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&pinctrl_mag>;
 393                 interrupt-parent = <&gpio5>;
 394                 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 395         };
 396
 397         ltc3676: pmic@3c {
 398                 compatible = "lltc,ltc3676";
 399                 reg = <0x3c>;
 400                 interrupt-parent = <&gpio1>;
 401                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 402
 403                 regulators {
 404                         /* VDD_SOC (1+R1/R2 = 1.635) */
 405                         reg_vdd_soc: sw1 {
 406                                 regulator-name = "vddsoc";
 407                                 regulator-min-microvolt = <674400>;
 408                                 regulator-max-microvolt = <1308000>;
 409                                 lltc,fb-voltage-divider = <127000 200000>;
 410                                 regulator-ramp-delay = <7000>;
 411                                 regulator-boot-on;
 412                                 regulator-always-on;
 413                         };
 414
 415                         /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
 416                         reg_1p8v: sw2 {
 417                                 regulator-name = "vdd1p8";
 418                                 regulator-min-microvolt = <1033310>;
 419                                 regulator-max-microvolt = <2004000>;
 420                                 lltc,fb-voltage-divider = <301000 200000>;
 421                                 regulator-ramp-delay = <7000>;
 422                                 regulator-boot-on;
 423                                 regulator-always-on;
 424                         };
 425
 426                         /* VDD_ARM (1+R1/R2 = 1.635) */
 427                         reg_vdd_arm: sw3 {
 428                                 regulator-name = "vddarm";
 429                                 regulator-min-microvolt = <674400>;
 430                                 regulator-max-microvolt = <1308000>;
 431                                 lltc,fb-voltage-divider = <127000 200000>;
 432                                 regulator-ramp-delay = <7000>;
 433                                 regulator-boot-on;
 434                                 regulator-always-on;
 435                         };
 436
 437                         /* VDD_DDR (1+R1/R2 = 2.105) */
 438                         reg_vdd_ddr: sw4 {
 439                                 regulator-name = "vddddr";
 440                                 regulator-min-microvolt = <868310>;
 441                                 regulator-max-microvolt = <1684000>;
 442                                 lltc,fb-voltage-divider = <221000 200000>;
 443                                 regulator-ramp-delay = <7000>;
 444                                 regulator-boot-on;
 445                                 regulator-always-on;
 446                         };
 447
 448                         /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
 449                         reg_2p5v: ldo2 {
 450                                 regulator-name = "vdd2p5";
 451                                 regulator-min-microvolt = <2490375>;
 452                                 regulator-max-microvolt = <2490375>;
 453                                 lltc,fb-voltage-divider = <487000 200000>;
 454                                 regulator-boot-on;
 455                                 regulator-always-on;
 456                         };
 457
 458                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 459                         reg_3p0v: ldo4 {
 460                                 regulator-name = "vdd3p0";
 461                                 regulator-min-microvolt = <3023250>;
 462                                 regulator-max-microvolt = <3023250>;
 463                                 lltc,fb-voltage-divider = <634000 200000>;
 464                                 regulator-boot-on;
 465                                 regulator-always-on;
 466                         };
 467                 };
 468         };
 469
 470         crypto@60 {
 471                 compatible = "atmel,atecc508a";
 472                 reg = <0x60>;
 473         };
 474
 475         imu@6a {
 476                 compatible = "st,lsm9ds1-imu";
 477                 reg = <0x6a>;
 478                 st,drdy-int-pin = <1>;
 479                 pinctrl-names = "default";
 480                 pinctrl-0 = <&pinctrl_imu>;
 481                 interrupt-parent = <&gpio4>;
 482                 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
 483         };
 484 };
 485
 486 &i2c3 {
 487         clock-frequency = <100000>;
 488         pinctrl-names = "default";
 489         pinctrl-0 = <&pinctrl_i2c3>;
 490         status = "okay";
 491
 492         egalax_ts: touchscreen@4 {
 493                 compatible = "eeti,egalax_ts";
 494                 reg = <0x04>;
 495                 interrupt-parent = <&gpio1>;
 496                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 497                 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 498         };
 499 };
 500
 501 &ldb {
 502         status = "okay";
 503
 504         lvds-channel@0 {
 505                 fsl,data-mapping = "spwg";
 506                 fsl,data-width = <18>;
 507                 status = "okay";
 508
 509                 display-timings {
 510                         native-mode = <&timing0>;
 511                         timing0: hsd100pxn1 {
 512                                 clock-frequency = <65000000>;
 513                                 hactive = <1024>;
 514                                 vactive = <768>;
 515                                 hback-porch = <220>;
 516                                 hfront-porch = <40>;
 517                                 vback-porch = <21>;
 518                                 vfront-porch = <7>;
 519                                 hsync-len = <60>;
 520                                 vsync-len = <10>;
 521                         };
 522                 };
 523         };
 524 };
 525
 526 &pcie {
 527         pinctrl-names = "default";
 528         pinctrl-0 = <&pinctrl_pcie>;
 529         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 530         status = "okay";
 531 };
 532
 533 &pwm2 {
 534         pinctrl-names = "default";
 535         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 536         status = "disabled";
 537 };
 538
 539 &pwm3 {
 540         pinctrl-names = "default";
 541         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 542         status = "disabled";
 543 };
 544
 545 &pwm4 {
 546         #pwm-cells = <2>;
 547         pinctrl-names = "default";
 548         pinctrl-0 = <&pinctrl_pwm4>;
 549         status = "okay";
 550 };
 551
 552 &uart1 {
 553         pinctrl-names = "default";
 554         pinctrl-0 = <&pinctrl_uart1>;
 555         status = "okay";
 556 };
 557
 558 &uart2 {
 559         pinctrl-names = "default";
 560         pinctrl-0 = <&pinctrl_uart2>;
 561         status = "okay";
 562 };
 563
 564 &uart3 {
 565         pinctrl-names = "default";
 566         pinctrl-0 = <&pinctrl_uart3>;
 567         uart-has-rtscts;
 568         status = "okay";
 569 };
 570
 571 &uart4 {
 572         pinctrl-names = "default";
 573         pinctrl-0 = <&pinctrl_uart4>;
 574         uart-has-rtscts;
 575         status = "okay";
 576 };
 577
 578 &uart5 {
 579         pinctrl-names = "default";
 580         pinctrl-0 = <&pinctrl_uart5>;
 581         status = "okay";
 582 };
 583
 584 &usbotg {
 585         vbus-supply = <&reg_usb_otg_vbus>;
 586         pinctrl-names = "default";
 587         pinctrl-0 = <&pinctrl_usbotg>;
 588         disable-over-current;
 589         status = "okay";
 590 };
 591
 592 &usbh1 {
 593         vbus-supply = <&reg_usb_h1_vbus>;
 594         status = "okay";
 595 };
 596
 597 &usdhc3 {
 598         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 599         pinctrl-0 = <&pinctrl_usdhc3>;
 600         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 601         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 602         non-removable;
 603         vmmc-supply = <&reg_3p3v>;
 604         keep-power-in-suspend;
 605         status = "okay";
 606 };
 607
 608 &wdog1 {
 609         pinctrl-names = "default";
 610         pinctrl-0 = <&pinctrl_wdog>;
 611         fsl,ext-reset-output;
 612 };
 613
 614 &iomuxc {
 615         pinctrl_enet: enetgrp {
 616                 fsl,pins = <
 617                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 618                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 619                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 620                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 621                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 622                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 623                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 624                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 625                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 626                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 627                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 628                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 629                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 630                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 631                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 632                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 633                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x4001b0b0 /* PHY_RST# */
 634                 >;
 635         };
 636
 637         pinctrl_gpio_leds: gpioledsgrp {
 638                 fsl,pins = <
 639                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 640                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 641                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 642                 >;
 643         };
 644
 645         pinctrl_i2c1: i2c1grp {
 646                 fsl,pins = <
 647                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 648                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 649                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0 /* GSC_IRQ# */
 650                 >;
 651         };
 652
 653         pinctrl_i2c2: i2c2grp {
 654                 fsl,pins = <
 655                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 656                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 657                 >;
 658         };
 659
 660         pinctrl_i2c3: i2c3grp {
 661                 fsl,pins = <
 662                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 663                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 664                 >;
 665         };
 666
 667         pinctrl_imu: imugrp {
 668                 fsl,pins = <
 669                         MX6QDL_PAD_DI0_PIN2__GPIO4_IO18         0x1b0b0
 670                 >;
 671         };
 672
 673         pinctrl_mag: maggrp {
 674                 fsl,pins = <
 675                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 676                 >;
 677         };
 678
 679         pinctrl_pcie: pciegrp {
 680                 fsl,pins = <
 681                         MX6QDL_PAD_GPIO_0__GPIO1_IO00   0x1b0b0 /* PCIE RST */
 682                 >;
 683         };
 684
 685         pinctrl_pmic: pmicgrp {
 686                 fsl,pins = <
 687                         MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x1b0b0 /* PMIC_IRQ# */
 688                 >;
 689         };
 690
 691         pinctrl_pps: ppsgrp {
 692                 fsl,pins = <
 693                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 694                 >;
 695         };
 696
 697         pinctrl_pwm2: pwm2grp {
 698                 fsl,pins = <
 699                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 700                 >;
 701         };
 702
 703         pinctrl_pwm3: pwm3grp {
 704                 fsl,pins = <
 705                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 706                 >;
 707         };
 708
 709         pinctrl_pwm4: pwm4grp {
 710                 fsl,pins = <
 711                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 712                 >;
 713         };
 714
 715         pinctrl_uart1: uart1grp {
 716                 fsl,pins = <
 717                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 718                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 719                 >;
 720         };
 721
 722         pinctrl_uart2: uart2grp {
 723                 fsl,pins = <
 724                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 725                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 726                 >;
 727         };
 728
 729         pinctrl_uart3: uart3grp {
 730                 fsl,pins = <
 731                         MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
 732                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 733                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 734                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 735                 >;
 736         };
 737
 738         pinctrl_uart4: uart4grp {
 739                 fsl,pins = <
 740                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 741                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 742                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 743                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 744                 >;
 745         };
 746
 747         pinctrl_uart5: uart5grp {
 748                 fsl,pins = <
 749                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 750                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 751                 >;
 752         };
 753
 754         pinctrl_usbotg: usbotggrp {
 755                 fsl,pins = <
 756                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 757                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 758                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
 759                 >;
 760         };
 761
 762         pinctrl_usdhc3: usdhc3grp {
 763                 fsl,pins = <
 764                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 765                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 766                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x10059
 767                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 768                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 769                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 770                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 771                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 772                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 773                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 774                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 775                 >;
 776         };
 777
 778         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 779                 fsl,pins = <
 780                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 781                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 782                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100b9
 783                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 784                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 785                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 786                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 787                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 788                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 789                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 790                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 791                 >;
 792         };
 793
 794         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 795                 fsl,pins = <
 796                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 797                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 798                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100f9
 799                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 800                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 801                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 802                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 803                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 804                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 805                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 806                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 807                 >;
 808         };
 809
 810         pinctrl_wdog: wdoggrp {
 811                 fsl,pins = <
 812                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 813                 >;
 814         };
 815 };