arch/arm/boot/dts/imx6qdl-gw553x.dtsi

   1 /*
   2  * Copyright 2016 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/input/linux-event-codes.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51
  52 / {
  53         /* these are used by bootloader for disabling nodes */
  54         aliases {
  55                 led0 = &led0;
  56                 led1 = &led1;
  57                 nand = &gpmi;
  58                 usb0 = &usbh1;
  59                 usb1 = &usbotg;
  60         };
  61
  62         chosen {
  63                 stdout-path = &uart2;
  64         };
  65
  66         gpio-keys {
  67                 compatible = "gpio-keys";
  68
  69                 user-pb {
  70                         label = "user_pb";
  71                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  72                         linux,code = <BTN_0>;
  73                 };
  74
  75                 user-pb1x {
  76                         label = "user_pb1x";
  77                         linux,code = <BTN_1>;
  78                         interrupt-parent = <&gsc>;
  79                         interrupts = <0>;
  80                 };
  81
  82                 key-erased {
  83                         label = "key-erased";
  84                         linux,code = <BTN_2>;
  85                         interrupt-parent = <&gsc>;
  86                         interrupts = <1>;
  87                 };
  88
  89                 eeprom-wp {
  90                         label = "eeprom_wp";
  91                         linux,code = <BTN_3>;
  92                         interrupt-parent = <&gsc>;
  93                         interrupts = <2>;
  94                 };
  95
  96                 tamper {
  97                         label = "tamper";
  98                         linux,code = <BTN_4>;
  99                         interrupt-parent = <&gsc>;
 100                         interrupts = <5>;
 101                 };
 102
 103                 switch-hold {
 104                         label = "switch_hold";
 105                         linux,code = <BTN_5>;
 106                         interrupt-parent = <&gsc>;
 107                         interrupts = <7>;
 108                 };
 109         };
 110
 111         leds {
 112                 compatible = "gpio-leds";
 113                 pinctrl-names = "default";
 114                 pinctrl-0 = <&pinctrl_gpio_leds>;
 115
 116                 led0: user1 {
 117                         label = "user1";
 118                         gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
 119                         default-state = "on";
 120                         linux,default-trigger = "heartbeat";
 121                 };
 122
 123                 led1: user2 {
 124                         label = "user2";
 125                         gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
 126                         default-state = "off";
 127                 };
 128         };
 129
 130         memory@10000000 {
 131                 device_type = "memory";
 132                 reg = <0x10000000 0x20000000>;
 133         };
 134
 135         pps {
 136                 compatible = "pps-gpio";
 137                 pinctrl-names = "default";
 138                 pinctrl-0 = <&pinctrl_pps>;
 139                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 140                 status = "okay";
 141         };
 142
 143         reg_5p0v: regulator-5p0v {
 144                 compatible = "regulator-fixed";
 145                 regulator-name = "5P0V";
 146                 regulator-min-microvolt = <5000000>;
 147                 regulator-max-microvolt = <5000000>;
 148                 regulator-always-on;
 149         };
 150
 151         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 152                 compatible = "regulator-fixed";
 153                 regulator-name = "usb_otg_vbus";
 154                 regulator-min-microvolt = <5000000>;
 155                 regulator-max-microvolt = <5000000>;
 156                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 157                 enable-active-high;
 158         };
 159 };
 160
 161 &gpmi {
 162         pinctrl-names = "default";
 163         pinctrl-0 = <&pinctrl_gpmi_nand>;
 164         status = "okay";
 165 };
 166
 167 &hdmi {
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&pinctrl_hdmi>;
 170         ddc-i2c-bus = <&i2c3>;
 171         status = "okay";
 172 };
 173
 174 &i2c1 {
 175         clock-frequency = <100000>;
 176         pinctrl-names = "default";
 177         pinctrl-0 = <&pinctrl_i2c1>;
 178         status = "okay";
 179
 180         gsc: gsc@20 {
 181                 compatible = "gw,gsc";
 182                 reg = <0x20>;
 183                 interrupt-parent = <&gpio1>;
 184                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 185                 interrupt-controller;
 186                 #interrupt-cells = <1>;
 187                 #size-cells = <0>;
 188
 189                 adc {
 190                         compatible = "gw,gsc-adc";
 191                         #address-cells = <1>;
 192                         #size-cells = <0>;
 193
 194                         channel@0 {
 195                                 gw,mode = <0>;
 196                                 reg = <0x00>;
 197                                 label = "temp";
 198                         };
 199
 200                         channel@2 {
 201                                 gw,mode = <1>;
 202                                 reg = <0x02>;
 203                                 label = "vdd_vin";
 204                         };
 205
 206                         channel@5 {
 207                                 gw,mode = <1>;
 208                                 reg = <0x05>;
 209                                 label = "vdd_3p3";
 210                         };
 211
 212                         channel@8 {
 213                                 gw,mode = <1>;
 214                                 reg = <0x08>;
 215                                 label = "vdd_bat";
 216                         };
 217
 218                         channel@b {
 219                                 gw,mode = <1>;
 220                                 reg = <0x0b>;
 221                                 label = "vdd_5p0";
 222                         };
 223
 224                         channel@e {
 225                                 gw,mode = <1>;
 226                                 reg = <0xe>;
 227                                 label = "vdd_arm";
 228                         };
 229
 230                         channel@11 {
 231                                 gw,mode = <1>;
 232                                 reg = <0x11>;
 233                                 label = "vdd_soc";
 234                         };
 235
 236                         channel@14 {
 237                                 gw,mode = <1>;
 238                                 reg = <0x14>;
 239                                 label = "vdd_3p0";
 240                         };
 241
 242                         channel@17 {
 243                                 gw,mode = <1>;
 244                                 reg = <0x17>;
 245                                 label = "vdd_1p5";
 246                         };
 247
 248                         channel@1d {
 249                                 gw,mode = <1>;
 250                                 reg = <0x1d>;
 251                                 label = "vdd_1p8a";
 252                         };
 253
 254                         channel@20 {
 255                                 gw,mode = <1>;
 256                                 reg = <0x20>;
 257                                 label = "vdd_1p0b";
 258                         };
 259
 260                         channel@26 {
 261                                 gw,mode = <1>;
 262                                 reg = <0x26>;
 263                                 label = "vdd_an1";
 264                         };
 265                 };
 266         };
 267
 268         gsc_gpio: gpio@23 {
 269                 compatible = "nxp,pca9555";
 270                 reg = <0x23>;
 271                 gpio-controller;
 272                 #gpio-cells = <2>;
 273                 interrupt-parent = <&gsc>;
 274                 interrupts = <4>;
 275         };
 276
 277         eeprom1: eeprom@50 {
 278                 compatible = "atmel,24c02";
 279                 reg = <0x50>;
 280                 pagesize = <16>;
 281         };
 282
 283         eeprom2: eeprom@51 {
 284                 compatible = "atmel,24c02";
 285                 reg = <0x51>;
 286                 pagesize = <16>;
 287         };
 288
 289         eeprom3: eeprom@52 {
 290                 compatible = "atmel,24c02";
 291                 reg = <0x52>;
 292                 pagesize = <16>;
 293         };
 294
 295         eeprom4: eeprom@53 {
 296                 compatible = "atmel,24c02";
 297                 reg = <0x53>;
 298                 pagesize = <16>;
 299         };
 300
 301         rtc: ds1672@68 {
 302                 compatible = "dallas,ds1672";
 303                 reg = <0x68>;
 304         };
 305 };
 306
 307 &i2c2 {
 308         clock-frequency = <100000>;
 309         pinctrl-names = "default";
 310         pinctrl-0 = <&pinctrl_i2c2>;
 311         status = "okay";
 312
 313         magn@1c {
 314                 compatible = "st,lsm9ds1-magn";
 315                 reg = <0x1c>;
 316                 pinctrl-names = "default";
 317                 pinctrl-0 = <&pinctrl_mag>;
 318                 interrupt-parent = <&gpio1>;
 319                 interrupts = <2 IRQ_TYPE_EDGE_RISING>;
 320         };
 321
 322         imu@6a {
 323                 compatible = "st,lsm9ds1-imu";
 324                 reg = <0x6a>;
 325                 st,drdy-int-pin = <1>;
 326                 pinctrl-names = "default";
 327                 pinctrl-0 = <&pinctrl_imu>;
 328                 interrupt-parent = <&gpio7>;
 329                 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
 330         };
 331
 332         ltc3676: pmic@3c {
 333                 compatible = "lltc,ltc3676";
 334                 reg = <0x3c>;
 335                 pinctrl-names = "default";
 336                 pinctrl-0 = <&pinctrl_pmic>;
 337                 interrupt-parent = <&gpio1>;
 338                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 339
 340                 regulators {
 341                         /* VDD_SOC (1+R1/R2 = 1.635) */
 342                         reg_vdd_soc: sw1 {
 343                                 regulator-name = "vddsoc";
 344                                 regulator-min-microvolt = <674400>;
 345                                 regulator-max-microvolt = <1308000>;
 346                                 lltc,fb-voltage-divider = <127000 200000>;
 347                                 regulator-ramp-delay = <7000>;
 348                                 regulator-boot-on;
 349                                 regulator-always-on;
 350                         };
 351
 352                         /* VDD_DDR (1+R1/R2 = 2.105) */
 353                         reg_vdd_ddr: sw2 {
 354                                 regulator-name = "vddddr";
 355                                 regulator-min-microvolt = <868310>;
 356                                 regulator-max-microvolt = <1684000>;
 357                                 lltc,fb-voltage-divider = <221000 200000>;
 358                                 regulator-ramp-delay = <7000>;
 359                                 regulator-boot-on;
 360                                 regulator-always-on;
 361                         };
 362
 363                         /* VDD_ARM (1+R1/R2 = 1.635) */
 364                         reg_vdd_arm: sw3 {
 365                                 regulator-name = "vddarm";
 366                                 regulator-min-microvolt = <674400>;
 367                                 regulator-max-microvolt = <1308000>;
 368                                 lltc,fb-voltage-divider = <127000 200000>;
 369                                 regulator-ramp-delay = <7000>;
 370                                 regulator-boot-on;
 371                                 regulator-always-on;
 372                         };
 373
 374                         /* VDD_3P3 (1+R1/R2 = 1.281) */
 375                         reg_3p3v: sw4 {
 376                                 regulator-name = "vdd3p3";
 377                                 regulator-min-microvolt = <1880000>;
 378                                 regulator-max-microvolt = <3647000>;
 379                                 lltc,fb-voltage-divider = <200000 56200>;
 380                                 regulator-ramp-delay = <7000>;
 381                                 regulator-boot-on;
 382                                 regulator-always-on;
 383                         };
 384
 385                         /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */
 386                         reg_1p8a: ldo2 {
 387                                 regulator-name = "vdd1p8a";
 388                                 regulator-min-microvolt = <1816125>;
 389                                 regulator-max-microvolt = <1816125>;
 390                                 lltc,fb-voltage-divider = <301000 200000>;
 391                                 regulator-boot-on;
 392                                 regulator-always-on;
 393                         };
 394
 395                         /* VDD_1P8b: microSD VDD_1P8 */
 396                         reg_1p8b: ldo3 {
 397                                 regulator-name = "vdd1p8b";
 398                                 regulator-min-microvolt = <1800000>;
 399                                 regulator-max-microvolt = <1800000>;
 400                                 regulator-boot-on;
 401                         };
 402
 403                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 404                         reg_3p0v: ldo4 {
 405                                 regulator-name = "vdd3p0";
 406                                 regulator-min-microvolt = <3023250>;
 407                                 regulator-max-microvolt = <3023250>;
 408                                 lltc,fb-voltage-divider = <634000 200000>;
 409                                 regulator-boot-on;
 410                                 regulator-always-on;
 411                         };
 412                 };
 413         };
 414 };
 415
 416 &i2c3 {
 417         clock-frequency = <100000>;
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_i2c3>;
 420         status = "okay";
 421
 422         adv7180: camera@20 {
 423                 compatible = "adi,adv7180";
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&pinctrl_adv7180>;
 426                 reg = <0x20>;
 427                 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
 428                 interrupt-parent = <&gpio5>;
 429                 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
 430
 431                 port {
 432                         adv7180_to_ipu1_csi0_mux: endpoint {
 433                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 434                                 bus-width = <8>;
 435                         };
 436                 };
 437         };
 438 };
 439
 440 &ipu1_csi0_from_ipu1_csi0_mux {
 441         bus-width = <8>;
 442 };
 443
 444 &ipu1_csi0_mux_from_parallel_sensor {
 445         remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
 446         bus-width = <8>;
 447 };
 448
 449 &ipu1_csi0 {
 450         pinctrl-names = "default";
 451         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 452 };
 453
 454 &pcie {
 455         pinctrl-names = "default";
 456         pinctrl-0 = <&pinctrl_pcie>;
 457         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 458         status = "okay";
 459 };
 460
 461 &pwm2 {
 462         pinctrl-names = "default";
 463         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 464         status = "disabled";
 465 };
 466
 467 &pwm3 {
 468         pinctrl-names = "default";
 469         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 470         status = "disabled";
 471 };
 472
 473 &pwm4 {
 474         pinctrl-names = "default";
 475         pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 476         status = "disabled";
 477 };
 478
 479 &uart2 {
 480         pinctrl-names = "default";
 481         pinctrl-0 = <&pinctrl_uart2>;
 482         status = "okay";
 483 };
 484
 485 &uart3 {
 486         pinctrl-names = "default";
 487         pinctrl-0 = <&pinctrl_uart3>;
 488         status = "okay";
 489 };
 490
 491 &uart4 {
 492         pinctrl-names = "default";
 493         pinctrl-0 = <&pinctrl_uart4>;
 494         status = "okay";
 495 };
 496
 497 &uart5 {
 498         pinctrl-names = "default";
 499         pinctrl-0 = <&pinctrl_uart5>;
 500         status = "okay";
 501 };
 502
 503 &usbh1 {
 504         status = "okay";
 505 };
 506
 507 &usbotg {
 508         vbus-supply = <&reg_usb_otg_vbus>;
 509         pinctrl-names = "default";
 510         pinctrl-0 = <&pinctrl_usbotg>;
 511         disable-over-current;
 512         status = "okay";
 513 };
 514
 515 &usdhc3 {
 516         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 517         pinctrl-0 = <&pinctrl_usdhc3>;
 518         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 519         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 520         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 521         status = "okay";
 522 };
 523
 524 &wdog1 {
 525         pinctrl-names = "default";
 526         pinctrl-0 = <&pinctrl_wdog>;
 527         fsl,ext-reset-output;
 528 };
 529
 530 &iomuxc {
 531         pinctrl_adv7180: adv7180grp {
 532                 fsl,pins = <
 533                         MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23        0x0001b0b0
 534                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x4001b0b0
 535                 >;
 536         };
 537
 538         pinctrl_gpmi_nand: gpminandgrp {
 539                 fsl,pins = <
 540                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 541                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 542                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 543                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 544                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 545                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 546                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 547                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 548                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 549                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 550                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 551                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 552                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 553                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 554                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 555                 >;
 556         };
 557
 558         pinctrl_hdmi: hdmigrp {
 559                 fsl,pins = <
 560                         MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE    0x1f8b0
 561                 >;
 562         };
 563
 564         pinctrl_i2c1: i2c1grp {
 565                 fsl,pins = <
 566                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 567                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 568                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0xb0b1
 569                 >;
 570         };
 571
 572         pinctrl_i2c2: i2c2grp {
 573                 fsl,pins = <
 574                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 575                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 576                 >;
 577         };
 578
 579         pinctrl_i2c3: i2c3grp {
 580                 fsl,pins = <
 581                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 582                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 583                 >;
 584         };
 585
 586         pinctrl_imu: imugrp {
 587                 fsl,pins = <
 588                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b0
 589                 >;
 590         };
 591
 592         pinctrl_ipu1_csi0: ipu1csi0grp {
 593                 fsl,pins = <
 594                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
 595                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
 596                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
 597                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
 598                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
 599                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
 600                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
 601                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
 602                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
 603                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
 604                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
 605                 >;
 606         };
 607
 608         pinctrl_gpio_leds: gpioledsgrp {
 609                 fsl,pins = <
 610                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 611                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
 612                 >;
 613         };
 614
 615         pinctrl_mag: maggrp {
 616                 fsl,pins = <
 617                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 618                 >;
 619         };
 620
 621         pinctrl_pcie: pciegrp {
 622                 fsl,pins = <
 623                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 624                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x4001b0b0 /* PCIESKT_WDIS# */
 625                 >;
 626         };
 627
 628         pinctrl_pmic: pmicgrp {
 629                 fsl,pins = <
 630                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 631                 >;
 632         };
 633
 634         pinctrl_pps: ppsgrp {
 635                 fsl,pins = <
 636                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 637                 >;
 638         };
 639
 640         pinctrl_pwm2: pwm2grp {
 641                 fsl,pins = <
 642                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 643                 >;
 644         };
 645
 646         pinctrl_pwm3: pwm3grp {
 647                 fsl,pins = <
 648                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 649                 >;
 650         };
 651
 652         pinctrl_pwm4: pwm4grp {
 653                 fsl,pins = <
 654                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 655                 >;
 656         };
 657
 658         pinctrl_uart2: uart2grp {
 659                 fsl,pins = <
 660                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 661                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 662                 >;
 663         };
 664
 665         pinctrl_uart3: uart3grp {
 666                 fsl,pins = <
 667                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 668                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 669                 >;
 670         };
 671
 672         pinctrl_uart4: uart4grp {
 673                 fsl,pins = <
 674                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 675                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 676                 >;
 677         };
 678
 679         pinctrl_uart5: uart5grp {
 680                 fsl,pins = <
 681                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 682                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 683                 >;
 684         };
 685
 686         pinctrl_usbotg: usbotggrp {
 687                 fsl,pins = <
 688                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 689                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* OTG_PWR_EN */
 690                         MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x17059
 691                 >;
 692         };
 693
 694         pinctrl_usdhc3: usdhc3grp {
 695                 fsl,pins = <
 696                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 697                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 698                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 699                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 700                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 701                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 702                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 703                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 704                 >;
 705         };
 706
 707         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 708                 fsl,pins = <
 709                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 710                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 711                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 712                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 713                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 714                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 715                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 716                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 717                 >;
 718         };
 719
 720         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 721                 fsl,pins = <
 722                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 723                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 724                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 725                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 726                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 727                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 728                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 729                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 730                 >;
 731         };
 732
 733         pinctrl_wdog: wdoggrp {
 734                 fsl,pins = <
 735                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 736                 >;
 737         };
 738 };