arch/arm/boot/dts/imx6dl-qmx6.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 or MIT
   2 //
   3 // Device Tree Source for i.MX6DL based congatec QMX6
   4 // System on Module
   5 //
   6 // Copyright 2018-2021 General Electric Company
   7 // Copyright 2018-2021 Collabora
   8 // Copyright 2016 congatec AG
   9
  10 #include "imx6dl.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/sound/fsl-imx-audmux.h>
  13
  14 / {
  15         memory@10000000 {
  16                 reg = <0x10000000 0x40000000>;
  17         };
  18
  19         reg_3p3v: 3p3v {
  20                 compatible = "regulator-fixed";
  21                 regulator-name = "3P3V";
  22                 regulator-min-microvolt = <3300000>;
  23                 regulator-max-microvolt = <3300000>;
  24         };
  25
  26         i2cmux {
  27                 compatible = "i2c-mux-gpio";
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30                 mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
  31                 i2c-parent = <&i2c2>;
  32
  33                 i2c5: i2c@0 {
  34                         reg = <0>;
  35                         #address-cells = <1>;
  36                         #size-cells = <0>;
  37                 };
  38
  39                 i2c6: i2c@1 {
  40                         reg = <1>;
  41                         #address-cells = <1>;
  42                         #size-cells = <0>;
  43                 };
  44         };
  45 };
  46
  47 &audmux {
  48         pinctrl-names = "default";
  49         pinctrl-0 = <&pinctrl_audmux>;
  50
  51         audmux_ssi1 {
  52                 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
  53                 fsl,port-config = <
  54                         (IMX_AUDMUX_V2_PTCR_TFSDIR |
  55                         IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) |
  56                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
  57                         IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) |
  58                         IMX_AUDMUX_V2_PTCR_SYN)
  59                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6)
  60                 >;
  61         };
  62
  63         audmux_aud6 {
  64                 fsl,audmux-port = <MX51_AUDMUX_PORT6>;
  65                 fsl,port-config = <
  66                         IMX_AUDMUX_V2_PTCR_SYN
  67                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
  68                 >;
  69         };
  70 };
  71
  72 &clks {
  73         clocks = <&rtc_sqw>;
  74         clock-names = "ckil";
  75         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  76                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  77         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
  78                                  <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
  79 };
  80
  81 &ecspi1 {
  82         cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_spi1>;
  85         status = "okay";
  86
  87         flash@0 {
  88                 #address-cells = <1>;
  89                 #size-cells = <1>;
  90                 compatible = "sst,sst25vf032b", "jedec,spi-nor";
  91                 spi-max-frequency = <20000000>;
  92                 reg = <0>;
  93
  94                 partition@0 {
  95                         label = "bootloader";
  96                         reg = <0x0000000 0x100000>;
  97                 };
  98
  99                 partition@100000 {
 100                         label = "user";
 101                         reg = <0x0100000 0x2fc000>;
 102                 };
 103
 104                 partition@3fc000 {
 105                         label = "reserved";
 106                         reg = <0x03fc000 0x4000>;
 107                         read-only;
 108                 };
 109         };
 110 };
 111
 112 &fec {
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>;
 115         phy-mode = "rgmii-id";
 116         phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 117         fsl,magic-packet;
 118         phy-handle = <&phy0>;
 119
 120         mdio {
 121                 #address-cells = <1>;
 122                 #size-cells = <0>;
 123
 124                 phy0: ethernet-phy@6 {
 125                         reg = <6>;
 126                         qca,clk-out-frequency = <125000000>;
 127                 };
 128         };
 129 };
 130
 131 &i2c1 {
 132         clock-frequency = <100000>;
 133         pinctrl-names = "default", "gpio";
 134         pinctrl-0 = <&pinctrl_i2c1>;
 135         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 136         scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 137         sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 138         status = "okay";
 139 };
 140
 141 &i2c2 {
 142         clock-frequency = <100000>;
 143         pinctrl-names = "default", "gpio";
 144         pinctrl-0 = <&pinctrl_i2c2>;
 145         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 146         scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 147         sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 148         status = "okay";
 149 };
 150
 151 &i2c3 {
 152         clock-frequency = <100000>;
 153         pinctrl-names = "default", "gpio";
 154         pinctrl-0 = <&pinctrl_i2c3>;
 155         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 156         scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 157         sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 158         status = "okay";
 159
 160         rtc: m41t62@68 {
 161                 compatible = "st,m41t62";
 162                 reg = <0x68>;
 163
 164                 rtc_sqw: clock {
 165                         compatible = "fixed-clock";
 166                         #clock-cells = <0>;
 167                         clock-frequency = <32768>;
 168                 };
 169         };
 170 };
 171
 172 &i2c6 {
 173         pmic@8 {
 174                 compatible = "fsl,pfuze100";
 175                 reg = <0x08>;
 176
 177                 regulators {
 178                         sw1a_reg: sw1ab {
 179                                 regulator-min-microvolt = <300000>;
 180                                 regulator-max-microvolt = <1875000>;
 181                                 regulator-boot-on;
 182                                 regulator-always-on;
 183                                 regulator-ramp-delay = <6250>;
 184                         };
 185
 186                         sw1c_reg: sw1c {
 187                                 regulator-min-microvolt = <300000>;
 188                                 regulator-max-microvolt = <1875000>;
 189                                 regulator-boot-on;
 190                                 regulator-always-on;
 191                                 regulator-ramp-delay = <6250>;
 192                         };
 193
 194                         sw2_reg: sw2 {
 195                                 regulator-min-microvolt = <800000>;
 196                                 regulator-max-microvolt = <3300000>;
 197                                 regulator-boot-on;
 198                                 regulator-always-on;
 199                         };
 200
 201                         sw3a_reg: sw3a {
 202                                 regulator-min-microvolt = <400000>;
 203                                 regulator-max-microvolt = <1975000>;
 204                                 regulator-boot-on;
 205                                 regulator-always-on;
 206                         };
 207
 208                         sw3b_reg: sw3b {
 209                                 regulator-min-microvolt = <400000>;
 210                                 regulator-max-microvolt = <1975000>;
 211                                 regulator-boot-on;
 212                                 regulator-always-on;
 213                         };
 214
 215                         sw4_reg: sw4 {
 216                                 regulator-min-microvolt = <675000>;
 217                                 regulator-max-microvolt = <3300000>;
 218                                 regulator-boot-on;
 219                                 regulator-always-on;
 220                         };
 221
 222                         swbst_reg: swbst {
 223                                 regulator-min-microvolt = <5000000>;
 224                                 regulator-max-microvolt = <5150000>;
 225                         };
 226
 227                         snvs_reg: vsnvs {
 228                                 regulator-min-microvolt = <1000000>;
 229                                 regulator-max-microvolt = <3000000>;
 230                                 regulator-boot-on;
 231                                 regulator-always-on;
 232                         };
 233
 234                         vref_reg: vrefddr {
 235                                 regulator-boot-on;
 236                                 regulator-always-on;
 237                         };
 238
 239                         /*
 240                          * keep VGEN3, VGEN4 and VGEN5 enabled in order to
 241                          * maintain backward compatibility with hw-rev. A.0
 242                          */
 243                         vgen3_reg: vgen3 {
 244                                 regulator-min-microvolt = <1800000>;
 245                                 regulator-max-microvolt = <3300000>;
 246                                 regulator-always-on;
 247                         };
 248
 249                         vgen4_reg: vgen4 {
 250                                 regulator-min-microvolt = <2500000>;
 251                                 regulator-max-microvolt = <2500000>;
 252                                 regulator-always-on;
 253                         };
 254
 255                         vgen5_reg: vgen5 {
 256                                 regulator-min-microvolt = <1800000>;
 257                                 regulator-max-microvolt = <3300000>;
 258                                 regulator-always-on;
 259                         };
 260
 261                         /* supply voltage for eMMC */
 262                         vgen6_reg: vgen6 {
 263                                 regulator-min-microvolt = <1800000>;
 264                                 regulator-max-microvolt = <1800000>;
 265                                 regulator-boot-on;
 266                                 regulator-always-on;
 267                         };
 268                 };
 269         };
 270 };
 271
 272 &pcie {
 273         reset-gpio = <&gpio1 20 0>;
 274 };
 275
 276 &pwm4 {
 277         pinctrl-names = "default";
 278         pinctrl-0 = <&pinctrl_pwm4>;
 279 };
 280
 281 &reg_arm {
 282         vin-supply = <&sw1a_reg>;
 283 };
 284
 285 &reg_pu {
 286         vin-supply = <&sw1c_reg>;
 287 };
 288
 289 &reg_soc {
 290         vin-supply = <&sw1c_reg>;
 291 };
 292
 293 &snvs_poweroff {
 294         status = "okay";
 295 };
 296
 297 &uart2 {
 298         pinctrl-names = "default";
 299         pinctrl-0 = <&pinctrl_uart2>;
 300         status = "okay";
 301 };
 302
 303 &uart3 {
 304         pinctrl-names = "default";
 305         pinctrl-0 = <&pinctrl_uart3>;
 306         status = "okay";
 307 };
 308
 309 &usbh1 {
 310         /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */
 311         vbus-supply = <&reg_5v>;
 312         status = "okay";
 313 };
 314
 315 &usbotg {
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&pinctrl_usbotg>;
 318 };
 319
 320 &usdhc2 {
 321         /* MicroSD card slot */
 322         pinctrl-names = "default";
 323         pinctrl-0 = <&pinctrl_usdhc2>;
 324         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 325         no-1-8-v;
 326         keep-power-in-suspend;
 327         wakeup-source;
 328         vmmc-supply = <&reg_3p3v>;
 329         status = "okay";
 330 };
 331
 332 &usdhc3 {
 333         /* eMMC module */
 334         pinctrl-names = "default";
 335         pinctrl-0 = <&pinctrl_usdhc3>;
 336         non-removable;
 337         bus-width = <8>;
 338         no-1-8-v;
 339         keep-power-in-suspend;
 340         wakeup-source;
 341         vmmc-supply = <&reg_3p3v>;
 342         status = "okay";
 343 };
 344
 345 &wdog1 {
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_wdog>;
 348         fsl,ext-reset-output;
 349 };
 350
 351 &iomuxc {
 352         pinctrl-names = "default";
 353         pinctrl-0 = <&pinctrl_hog>;
 354
 355         qmx6mux: imx6qdl-qmx6 {
 356                 pinctrl_audmux: audmuxgrp {
 357                         fsl,pins = <
 358                                 MX6QDL_PAD_DI0_PIN2__AUD6_TXD           0x110b0 /* Q7[67] HDA_SDO */
 359                                 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS          0x30b0 /* Q7[59] HDA_SYNC */
 360                                 MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x30b0 /* Q7[65] HDA_SDI */
 361                                 MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x30b0 /* Q7[63] HDA_BITCLK */
 362                         >;
 363                 };
 364
 365                 /* PHY is on System on Module, Q7[3-15] have Ethernet lines */
 366                 pinctrl_enet: enet {
 367                         fsl,pins = <
 368                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 369                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 370                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 371                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 372                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 373                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 374                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 375                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 376                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 377                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 378                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 379                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 380                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 381                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 382                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 383                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 384                         >;
 385                 };
 386
 387                 pinctrl_hog: hoggrp {
 388                         fsl,pins = <
 389                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x80000000 /* PCIE_WAKE_B */
 390                                 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09       0x80000000 /* I2C multiplexer */
 391                                 MX6QDL_PAD_NANDF_D6__GPIO2_IO06         0x80000000 /* SD4_CD# */
 392                                 MX6QDL_PAD_NANDF_D7__GPIO2_IO07         0x80000000 /* SD4_WP */
 393                                 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1         0x80000000 /* Camera MCLK */
 394                         >;
 395                 };
 396
 397                 pinctrl_i2c1: i2c1 {
 398                         fsl,pins = <
 399                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1 /* Q7[66] I2C_CLK */
 400                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1 /* Q7[68] I2C_DAT */
 401                         >;
 402                 };
 403
 404                 pinctrl_i2c1_gpio: i2c1-gpio {
 405                         fsl,pins = <
 406                                 MX6QDL_PAD_EIM_D21__GPIO3_IO21          0x1b0b0 /* Q7[66] I2C_CLK */
 407                                 MX6QDL_PAD_EIM_D28__GPIO3_IO28          0x1b0b0 /* Q7[68] I2C_DAT */
 408                         >;
 409                 };
 410
 411                 pinctrl_i2c2: i2c2 {
 412                         fsl,pins = <
 413                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */
 414                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */
 415                         >;
 416                 };
 417
 418                 pinctrl_i2c2_gpio: i2c2-gpio {
 419                         fsl,pins = <
 420                                 MX6QDL_PAD_KEY_COL3__GPIO4_IO12         0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */
 421                                 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13         0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */
 422                         >;
 423                 };
 424
 425                 pinctrl_i2c3: i2c3 {
 426                         fsl,pins = <
 427                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1 /* Q7[60] SMB_CLK */
 428                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1 /* Q7[62] SMB_DAT */
 429                         >;
 430                 };
 431
 432                 pinctrl_i2c3_gpio: i2c3-gpio {
 433                         fsl,pins = <
 434                                 MX6QDL_PAD_GPIO_3__GPIO1_IO03           0x1b0b0 /* Q7[60] SMB_CLK */
 435                                 MX6QDL_PAD_GPIO_6__GPIO1_IO06           0x1b0b0 /* Q7[62] SMB_DAT */
 436                         >;
 437                 };
 438
 439                 pinctrl_phy_reset: phy-reset {
 440                         fsl,pins = <
 441                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x1b0b0 /* RGMII Phy Reset */
 442                         >;
 443                 };
 444
 445                 pinctrl_pwm4: pwm4 {
 446                         fsl,pins = <
 447                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */
 448                         >;
 449                 };
 450
 451                 pinctrl_q7_backlight_enable: q7-backlight-enable {
 452                         fsl,pins = <
 453                                 MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x1b0b0 /* Q7[112] LVDS_BLEN */
 454                         >;
 455                 };
 456
 457                 pinctrl_q7_gpio0: q7-gpio0 {
 458                         fsl,pins = <
 459                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b0 /* Q7[185] GPIO0 */
 460                         >;
 461                 };
 462
 463                 pinctrl_q7_gpio1: q7-gpio1 {
 464                         fsl,pins = <
 465                                 MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x1b0b0 /* Q7[186] GPIO1 */
 466                         >;
 467                 };
 468
 469                 pinctrl_q7_gpio2: q7-gpio2 {
 470                         fsl,pins = <
 471                                 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26       0x1b0b0 /* Q7[187] GPIO2 */
 472                         >;
 473                 };
 474
 475                 pinctrl_q7_gpio3: q7-gpio3 {
 476                         fsl,pins = <
 477                                 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27       0x1b0b0 /* Q7[188] GPIO3 */
 478                         >;
 479                 };
 480
 481                 pinctrl_q7_gpio4: q7-gpio4 {
 482                         fsl,pins = <
 483                                 MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0 /* Q7[189] GPIO4 */
 484                         >;
 485                 };
 486
 487                 pinctrl_q7_gpio5: q7-gpio5 {
 488                         fsl,pins = <
 489                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0 /* Q7[190] GPIO5 */
 490                         >;
 491                 };
 492
 493                 pinctrl_q7_gpio6: q7-gpio6 {
 494                         fsl,pins = <
 495                                 MX6QDL_PAD_GPIO_16__GPIO7_IO11          0x1b0b0 /* Q7[191] GPIO6 */
 496                         >;
 497                 };
 498
 499                 pinctrl_q7_gpio7: q7-gpio7 {
 500                         fsl,pins = <
 501                                 MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* Q7[192] GPIO7 */
 502                         >;
 503                 };
 504
 505                 pinctrl_q7_hda_reset: q7-hda-reset {
 506                         fsl,pins = <
 507                                 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x1b0b0 /* Q7[61] HDA_RST_N */
 508                         >;
 509                 };
 510
 511                 pinctrl_q7_lcd_power: lcd-power {
 512                         fsl,pins = <
 513                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* Q7[111] LVDS_PPEN */
 514                         >;
 515                 };
 516
 517                 pinctrl_q7_sdio_power: q7-sdio-power {
 518                         fsl,pins = <
 519                                 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30       0x1b0b0 /* Q7[47] SDIO_PWR# */
 520                         >;
 521                 };
 522
 523                 pinctrl_q7_sleep_button: q7-sleep-button {
 524                         fsl,pins = <
 525                                 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0 /* Q7[21] SLP_BTN# */
 526                         >;
 527                 };
 528
 529                 pinctrl_q7_spi_cs1: spi-cs1 {
 530                         fsl,pins = <
 531                                 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25       0x1b0b0 /* Q7[202] SPI_CS1# */
 532                         >;
 533                 };
 534
 535                 /* SPI1 bus does not leave System on Module */
 536                 pinctrl_spi1: spi1 {
 537                         fsl,pins = <
 538                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 539                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 540                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 541                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x1b0b0
 542                         >;
 543                 };
 544
 545                 /* Debug connector on Q7 module */
 546                 pinctrl_uart2: uart2 {
 547                         fsl,pins = <
 548                                 MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
 549                                 MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
 550                         >;
 551                 };
 552
 553                 pinctrl_uart3: uart3 {
 554                         fsl,pins = <
 555                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1 /* Q7[177] UART0_RX */
 556                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1 /* Q7[171] UART0_TX */
 557                         >;
 558                 };
 559
 560                 pinctrl_usbotg: usbotg {
 561                         fsl,pins = <
 562                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059 /* Q7[92] USB_ID */
 563                         >;
 564                 };
 565
 566                 /* µSD card slot on Q7 module */
 567                 pinctrl_usdhc2: usdhc2 {
 568                         fsl,pins = <
 569                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 570                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 571                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 572                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 573                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 574                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 575                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* SD2_CD */
 576                         >;
 577                 };
 578
 579                 /* eMMC module on Q7 module */
 580                 pinctrl_usdhc3: usdhc3 {
 581                         fsl,pins = <
 582                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 583                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 584                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 585                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 586                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 587                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 588                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 589                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 590                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 591                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 592                         >;
 593                 };
 594
 595                 pinctrl_usdhc4: usdhc4 {
 596                         fsl,pins = <
 597                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059 /* Q7[45] SDIO_CMD */
 598                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x17059 /* Q7[42] SDIO_CLK */
 599                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059 /* Q7[48] SDIO_DAT1 */
 600                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059 /* Q7[49] SDIO_DAT0 */
 601                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059 /* Q7[50] SDIO_DAT3 */
 602                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059 /* Q7[51] SDIO_DAT2 */
 603                         >;
 604                 };
 605
 606                 pinctrl_wdog: wdog {
 607                         fsl,pins = <
 608                                 MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0 /* Watchdog output signal */
 609                         >;
 610                 };
 611         };
 612 };