arch/arm/boot/dts/hisi-x5hd2.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2014 Linaro Ltd.
   4  * Copyright (c) 2013-2014 Hisilicon Limited.
   5  */
   6
   7 #include <dt-bindings/clock/hix5hd2-clock.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12
  13         aliases {
  14                 serial0 = &uart0;
  15         };
  16
  17         gic: interrupt-controller@f8a01000 {
  18                 compatible = "arm,cortex-a9-gic";
  19                 #interrupt-cells = <3>;
  20                 #address-cells = <0>;
  21                 interrupt-controller;
  22                 /* gic dist base, gic cpu base */
  23                 reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
  24         };
  25
  26         soc {
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29                 compatible = "simple-bus";
  30                 interrupt-parent = <&gic>;
  31                 ranges = <0 0xf8000000 0x8000000>;
  32
  33                 amba-bus {
  34                         #address-cells = <1>;
  35                         #size-cells = <1>;
  36                         compatible = "simple-bus";
  37                         ranges;
  38
  39                         timer0: timer@2000 {
  40                                 compatible = "arm,sp804", "arm,primecell";
  41                                 reg = <0x00002000 0x1000>;
  42                                 /* timer00 & timer01 */
  43                                 interrupts = <0 24 4>;
  44                                 clocks = <&clock HIX5HD2_FIXED_24M>;
  45                                 status = "disabled";
  46                         };
  47
  48                         timer1: timer@a29000 {
  49                                 /*
  50                                  * Only used in NORMAL state, not available ins
  51                                  * SLOW or DOZE state.
  52                                  * The rate is fixed in 24MHz.
  53                                  */
  54                                 compatible = "arm,sp804", "arm,primecell";
  55                                 reg = <0x00a29000 0x1000>;
  56                                 /* timer10 & timer11 */
  57                                 interrupts = <0 25 4>;
  58                                 clocks = <&clock HIX5HD2_FIXED_24M>;
  59                                 status = "disabled";
  60                         };
  61
  62                         timer2: timer@a2a000 {
  63                                 compatible = "arm,sp804", "arm,primecell";
  64                                 reg = <0x00a2a000 0x1000>;
  65                                 /* timer20 & timer21 */
  66                                 interrupts = <0 26 4>;
  67                                 clocks = <&clock HIX5HD2_FIXED_24M>;
  68                                 status = "disabled";
  69                         };
  70
  71                         timer3: timer@a2b000 {
  72                                 compatible = "arm,sp804", "arm,primecell";
  73                                 reg = <0x00a2b000 0x1000>;
  74                                 /* timer30 & timer31 */
  75                                 interrupts = <0 27 4>;
  76                                 clocks = <&clock HIX5HD2_FIXED_24M>;
  77                                 status = "disabled";
  78                         };
  79
  80                         timer4: timer@a81000 {
  81                                 compatible = "arm,sp804", "arm,primecell";
  82                                 reg = <0x00a81000 0x1000>;
  83                                 /* timer30 & timer31 */
  84                                 interrupts = <0 28 4>;
  85                                 clocks = <&clock HIX5HD2_FIXED_24M>;
  86                                 status = "disabled";
  87                         };
  88
  89                         uart0: serial@b00000 {
  90                                 compatible = "arm,pl011", "arm,primecell";
  91                                 reg = <0x00b00000 0x1000>;
  92                                 interrupts = <0 49 4>;
  93                                 clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
  94                                 clock-names = "uartclk", "apb_pclk";
  95                                 status = "disabled";
  96                         };
  97
  98                         uart1: serial@6000 {
  99                                 compatible = "arm,pl011", "arm,primecell";
 100                                 reg = <0x00006000 0x1000>;
 101                                 interrupts = <0 50 4>;
 102                                 clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
 103                                 clock-names = "uartclk", "apb_pclk";
 104                                 status = "disabled";
 105                         };
 106
 107                         uart2: serial@b02000 {
 108                                 compatible = "arm,pl011", "arm,primecell";
 109                                 reg = <0x00b02000 0x1000>;
 110                                 interrupts = <0 51 4>;
 111                                 clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
 112                                 clock-names = "uartclk", "apb_pclk";
 113                                 status = "disabled";
 114                         };
 115
 116                         uart3: serial@b03000 {
 117                                 compatible = "arm,pl011", "arm,primecell";
 118                                 reg = <0x00b03000 0x1000>;
 119                                 interrupts = <0 52 4>;
 120                                 clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
 121                                 clock-names = "uartclk", "apb_pclk";
 122                                 status = "disabled";
 123                         };
 124
 125                         uart4: serial@b04000 {
 126                                 compatible = "arm,pl011", "arm,primecell";
 127                                 reg = <0xb04000 0x1000>;
 128                                 interrupts = <0 53 4>;
 129                                 clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
 130                                 clock-names = "uartclk", "apb_pclk";
 131                                 status = "disabled";
 132                         };
 133
 134                         gpio0: gpio@b20000 {
 135                                 compatible = "arm,pl061", "arm,primecell";
 136                                 reg = <0xb20000 0x1000>;
 137                                 interrupts = <0 108 0x4>;
 138                                 gpio-controller;
 139                                 #gpio-cells = <2>;
 140                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 141                                 clock-names = "apb_pclk";
 142                                 interrupt-controller;
 143                                 #interrupt-cells = <2>;
 144                                 status = "disabled";
 145                         };
 146
 147                         gpio1: gpio@b21000 {
 148                                 compatible = "arm,pl061", "arm,primecell";
 149                                 reg = <0xb21000 0x1000>;
 150                                 interrupts = <0 109 0x4>;
 151                                 gpio-controller;
 152                                 #gpio-cells = <2>;
 153                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 154                                 clock-names = "apb_pclk";
 155                                 interrupt-controller;
 156                                 #interrupt-cells = <2>;
 157                                 status = "disabled";
 158                         };
 159
 160                         gpio2: gpio@b22000 {
 161                                 compatible = "arm,pl061", "arm,primecell";
 162                                 reg = <0xb22000 0x1000>;
 163                                 interrupts = <0 110 0x4>;
 164                                 gpio-controller;
 165                                 #gpio-cells = <2>;
 166                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 167                                 clock-names = "apb_pclk";
 168                                 interrupt-controller;
 169                                 #interrupt-cells = <2>;
 170                                 status = "disabled";
 171                         };
 172
 173                         gpio3: gpio@b23000 {
 174                                 compatible = "arm,pl061", "arm,primecell";
 175                                 reg = <0xb23000 0x1000>;
 176                                 interrupts = <0 111 0x4>;
 177                                 gpio-controller;
 178                                 #gpio-cells = <2>;
 179                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 180                                 clock-names = "apb_pclk";
 181                                 interrupt-controller;
 182                                 #interrupt-cells = <2>;
 183                                 status = "disabled";
 184                         };
 185
 186                         gpio4: gpio@b24000 {
 187                                 compatible = "arm,pl061", "arm,primecell";
 188                                 reg = <0xb24000 0x1000>;
 189                                 interrupts = <0 112 0x4>;
 190                                 gpio-controller;
 191                                 #gpio-cells = <2>;
 192                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 193                                 clock-names = "apb_pclk";
 194                                 interrupt-controller;
 195                                 #interrupt-cells = <2>;
 196                                 status = "disabled";
 197                         };
 198
 199                         gpio5: gpio@4000 {
 200                                 compatible = "arm,pl061", "arm,primecell";
 201                                 reg = <0x004000 0x1000>;
 202                                 interrupts = <0 113 0x4>;
 203                                 gpio-controller;
 204                                 #gpio-cells = <2>;
 205                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 206                                 clock-names = "apb_pclk";
 207                                 interrupt-controller;
 208                                 #interrupt-cells = <2>;
 209                                 status = "disabled";
 210                         };
 211
 212                         gpio6: gpio@b26000 {
 213                                 compatible = "arm,pl061", "arm,primecell";
 214                                 reg = <0xb26000 0x1000>;
 215                                 interrupts = <0 114 0x4>;
 216                                 gpio-controller;
 217                                 #gpio-cells = <2>;
 218                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 219                                 clock-names = "apb_pclk";
 220                                 interrupt-controller;
 221                                 #interrupt-cells = <2>;
 222                                 status = "disabled";
 223                         };
 224
 225                         gpio7: gpio@b27000 {
 226                                 compatible = "arm,pl061", "arm,primecell";
 227                                 reg = <0xb27000 0x1000>;
 228                                 interrupts = <0 115 0x4>;
 229                                 gpio-controller;
 230                                 #gpio-cells = <2>;
 231                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 232                                 clock-names = "apb_pclk";
 233                                 interrupt-controller;
 234                                 #interrupt-cells = <2>;
 235                                 status = "disabled";
 236                         };
 237
 238                         gpio8: gpio@b28000 {
 239                                 compatible = "arm,pl061", "arm,primecell";
 240                                 reg = <0xb28000 0x1000>;
 241                                 interrupts = <0 116 0x4>;
 242                                 gpio-controller;
 243                                 #gpio-cells = <2>;
 244                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 245                                 clock-names = "apb_pclk";
 246                                 interrupt-controller;
 247                                 #interrupt-cells = <2>;
 248                                 status = "disabled";
 249                         };
 250
 251                         gpio9: gpio@b29000 {
 252                                 compatible = "arm,pl061", "arm,primecell";
 253                                 reg = <0xb29000 0x1000>;
 254                                 interrupts = <0 117 0x4>;
 255                                 gpio-controller;
 256                                 #gpio-cells = <2>;
 257                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 258                                 clock-names = "apb_pclk";
 259                                 interrupt-controller;
 260                                 #interrupt-cells = <2>;
 261                                 status = "disabled";
 262                         };
 263
 264                         gpio10: gpio@b2a000 {
 265                                 compatible = "arm,pl061", "arm,primecell";
 266                                 reg = <0xb2a000 0x1000>;
 267                                 interrupts = <0 118 0x4>;
 268                                 gpio-controller;
 269                                 #gpio-cells = <2>;
 270                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 271                                 clock-names = "apb_pclk";
 272                                 interrupt-controller;
 273                                 #interrupt-cells = <2>;
 274                                 status = "disabled";
 275                         };
 276
 277                         gpio11: gpio@b2b000 {
 278                                 compatible = "arm,pl061", "arm,primecell";
 279                                 reg = <0xb2b000 0x1000>;
 280                                 interrupts = <0 119 0x4>;
 281                                 gpio-controller;
 282                                 #gpio-cells = <2>;
 283                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 284                                 clock-names = "apb_pclk";
 285                                 interrupt-controller;
 286                                 #interrupt-cells = <2>;
 287                                 status = "disabled";
 288                         };
 289
 290                         gpio12: gpio@b2c000 {
 291                                 compatible = "arm,pl061", "arm,primecell";
 292                                 reg = <0xb2c000 0x1000>;
 293                                 interrupts = <0 120 0x4>;
 294                                 gpio-controller;
 295                                 #gpio-cells = <2>;
 296                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 297                                 clock-names = "apb_pclk";
 298                                 interrupt-controller;
 299                                 #interrupt-cells = <2>;
 300                                 status = "disabled";
 301                         };
 302
 303                         gpio13: gpio@b2d000 {
 304                                 compatible = "arm,pl061", "arm,primecell";
 305                                 reg = <0xb2d000 0x1000>;
 306                                 interrupts = <0 121 0x4>;
 307                                 gpio-controller;
 308                                 #gpio-cells = <2>;
 309                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 310                                 clock-names = "apb_pclk";
 311                                 interrupt-controller;
 312                                 #interrupt-cells = <2>;
 313                                 status = "disabled";
 314                         };
 315
 316                         gpio14: gpio@b2e000 {
 317                                 compatible = "arm,pl061", "arm,primecell";
 318                                 reg = <0xb2e000 0x1000>;
 319                                 interrupts = <0 122 0x4>;
 320                                 gpio-controller;
 321                                 #gpio-cells = <2>;
 322                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 323                                 clock-names = "apb_pclk";
 324                                 interrupt-controller;
 325                                 #interrupt-cells = <2>;
 326                                 status = "disabled";
 327                         };
 328
 329                         gpio15: gpio@b2f000 {
 330                                 compatible = "arm,pl061", "arm,primecell";
 331                                 reg = <0xb2f000 0x1000>;
 332                                 interrupts = <0 123 0x4>;
 333                                 gpio-controller;
 334                                 #gpio-cells = <2>;
 335                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 336                                 clock-names = "apb_pclk";
 337                                 interrupt-controller;
 338                                 #interrupt-cells = <2>;
 339                                 status = "disabled";
 340                         };
 341
 342                         gpio16: gpio@b30000 {
 343                                 compatible = "arm,pl061", "arm,primecell";
 344                                 reg = <0xb30000 0x1000>;
 345                                 interrupts = <0 124 0x4>;
 346                                 gpio-controller;
 347                                 #gpio-cells = <2>;
 348                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 349                                 clock-names = "apb_pclk";
 350                                 interrupt-controller;
 351                                 #interrupt-cells = <2>;
 352                                 status = "disabled";
 353                         };
 354
 355                         gpio17: gpio@b31000 {
 356                                 compatible = "arm,pl061", "arm,primecell";
 357                                 reg = <0xb31000 0x1000>;
 358                                 interrupts = <0 125 0x4>;
 359                                 gpio-controller;
 360                                 #gpio-cells = <2>;
 361                                 clocks = <&clock HIX5HD2_FIXED_100M>;
 362                                 clock-names = "apb_pclk";
 363                                 interrupt-controller;
 364                                 #interrupt-cells = <2>;
 365                                 status = "disabled";
 366                         };
 367
 368                         wdt0: watchdog@a2c000 {
 369                                 compatible = "arm,sp805", "arm,primecell";
 370                                 arm,primecell-periphid = <0x00141805>;
 371                                 reg = <0xa2c000 0x1000>;
 372                                 interrupts = <0 29 4>;
 373                                 clocks = <&clock HIX5HD2_WDG0_RST>,
 374                                          <&clock HIX5HD2_WDG0_RST>;
 375                                 clock-names = "wdog_clk", "apb_pclk";
 376                         };
 377                 };
 378
 379                 local_timer@a00600 {
 380                         compatible = "arm,cortex-a9-twd-timer";
 381                         reg = <0x00a00600 0x20>;
 382                         interrupts = <1 13 0xf01>;
 383                 };
 384
 385                 l2: cache-controller {
 386                         compatible = "arm,pl310-cache";
 387                         reg = <0x00a10000 0x100000>;
 388                         interrupts = <0 15 4>;
 389                         cache-unified;
 390                         cache-level = <2>;
 391                 };
 392
 393                 sysctrl: system-controller@0 {
 394                         compatible = "hisilicon,sysctrl", "syscon";
 395                         reg = <0x00000000 0x1000>;
 396                 };
 397
 398                 reboot {
 399                         compatible = "syscon-reboot";
 400                         regmap = <&sysctrl>;
 401                         offset = <0x4>;
 402                         mask = <0xdeadbeef>;
 403                 };
 404
 405                 cpuctrl@a22000 {
 406                         compatible = "hisilicon,cpuctrl";
 407                         #address-cells = <1>;
 408                         #size-cells = <1>;
 409                         reg = <0x00a22000 0x2000>;
 410                         ranges = <0 0x00a22000 0x2000>;
 411
 412                         clock: clock@0 {
 413                                 compatible = "hisilicon,hix5hd2-clock";
 414                                 reg = <0 0x2000>;
 415                                 #clock-cells = <1>;
 416                         };
 417                 };
 418
 419                 /* unremovable emmc as mmcblk0 */
 420                 mmc: mmc@1830000 {
 421                         compatible = "snps,dw-mshc";
 422                         reg = <0x1830000 0x1000>;
 423                         interrupts = <0 35 4>;
 424                         clocks = <&clock HIX5HD2_MMC_CIU_RST>,
 425                                  <&clock HIX5HD2_MMC_BIU_CLK>;
 426                         clock-names = "biu", "ciu";
 427                 };
 428
 429                 sd: mmc@1820000 {
 430                         compatible = "snps,dw-mshc";
 431                         reg = <0x1820000 0x1000>;
 432                         interrupts = <0 34 4>;
 433                         clocks = <&clock HIX5HD2_SD_CIU_RST>,
 434                                  <&clock HIX5HD2_SD_BIU_CLK>;
 435                         clock-names = "biu", "ciu";
 436                 };
 437
 438                 gmac0: ethernet@1840000 {
 439                         compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
 440                         reg = <0x1840000 0x1000>,<0x184300c 0x4>;
 441                         interrupts = <0 71 4>;
 442                         clocks = <&clock HIX5HD2_MAC0_CLK>;
 443                         clock-names = "mac_core";
 444                         status = "disabled";
 445                 };
 446
 447                 gmac1: ethernet@1841000 {
 448                         compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
 449                         reg = <0x1841000 0x1000>,<0x1843010 0x4>;
 450                         interrupts = <0 72 4>;
 451                         clocks = <&clock HIX5HD2_MAC1_CLK>;
 452                         clock-names = "mac_core";
 453                         status = "disabled";
 454                 };
 455
 456                 usb0: usb@1890000 {
 457                         compatible = "generic-ehci";
 458                         reg = <0x1890000 0x1000>;
 459                         interrupts = <0 66 4>;
 460                         clocks = <&clock HIX5HD2_USB_CLK>;
 461                 };
 462
 463                 usb1: usb@1880000 {
 464                         compatible = "generic-ohci";
 465                         reg = <0x1880000 0x1000>;
 466                         interrupts = <0 67 4>;
 467                         clocks = <&clock HIX5HD2_USB_CLK>;
 468                 };
 469
 470                 peripheral_ctrl: syscon@a20000 {
 471                         compatible = "hisilicon,peri-subctrl", "syscon";
 472                         reg = <0xa20000 0x1000>;
 473                 };
 474
 475                 sata_phy: phy@1900000 {
 476                         compatible = "hisilicon,hix5hd2-sata-phy";
 477                         reg = <0x1900000 0x10000>;
 478                         #phy-cells = <0>;
 479                         hisilicon,peripheral-syscon = <&peripheral_ctrl>;
 480                         hisilicon,power-reg = <0x8 10>;
 481                 };
 482
 483                 ahci: sata@1900000 {
 484                         compatible = "hisilicon,hisi-ahci";
 485                         reg = <0x1900000 0x10000>;
 486                         interrupts = <0 70 4>;
 487                         clocks = <&clock HIX5HD2_SATA_CLK>;
 488                 };
 489
 490                 ir: ir@1000 {
 491                         compatible = "hisilicon,hix5hd2-ir";
 492                         reg = <0x001000 0x1000>;
 493                         interrupts = <0 47 4>;
 494                         clocks = <&clock HIX5HD2_FIXED_24M>;
 495                         hisilicon,power-syscon = <&sysctrl>;
 496                 };
 497
 498                 i2c0: i2c@b10000 {
 499                         compatible = "hisilicon,hix5hd2-i2c";
 500                         reg = <0xb10000 0x1000>;
 501                         interrupts = <0 38 4>;
 502                         clocks = <&clock HIX5HD2_I2C0_RST>;
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         status = "disabled";
 506                 };
 507
 508                 i2c1: i2c@b11000 {
 509                         compatible = "hisilicon,hix5hd2-i2c";
 510                         reg = <0xb11000 0x1000>;
 511                         interrupts = <0 39 4>;
 512                         clocks = <&clock HIX5HD2_I2C1_RST>;
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         status = "disabled";
 516                 };
 517
 518                 i2c2: i2c@b12000 {
 519                         compatible = "hisilicon,hix5hd2-i2c";
 520                         reg = <0xb12000 0x1000>;
 521                         interrupts = <0 40 4>;
 522                         clocks = <&clock HIX5HD2_I2C2_RST>;
 523                         #address-cells = <1>;
 524                         #size-cells = <0>;
 525                         status = "disabled";
 526                 };
 527
 528                 i2c3: i2c@b13000 {
 529                         compatible = "hisilicon,hix5hd2-i2c";
 530                         reg = <0xb13000 0x1000>;
 531                         interrupts = <0 41 4>;
 532                         clocks = <&clock HIX5HD2_I2C3_RST>;
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                         status = "disabled";
 536                 };
 537
 538                 i2c4: i2c@b16000 {
 539                         compatible = "hisilicon,hix5hd2-i2c";
 540                         reg = <0xb16000 0x1000>;
 541                         interrupts = <0 43 4>;
 542                         clocks = <&clock HIX5HD2_I2C4_RST>;
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                         status = "disabled";
 546                 };
 547
 548                 i2c5: i2c@b17000 {
 549                         compatible = "hisilicon,hix5hd2-i2c";
 550                         reg = <0xb17000 0x1000>;
 551                         interrupts = <0 44 4>;
 552                         clocks = <&clock HIX5HD2_I2C5_RST>;
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         status = "disabled";
 556                 };
 557         };
 558 };