arch/arm/boot/dts/exynos5422-odroid-core.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
   4  *
   5  * Copyright (c) 2017 Marek Szyprowski
   6  * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
   7  *              http://www.samsung.com
   8  */
   9
  10 #include <dt-bindings/clock/samsung,s2mps11.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include "exynos5800.dtsi"
  14 #include "exynos5422-cpus.dtsi"
  15
  16 / {
  17         memory@40000000 {
  18                 device_type = "memory";
  19                 reg = <0x40000000 0x7EA00000>;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial2:115200n8";
  24         };
  25
  26         firmware@2073000 {
  27                 compatible = "samsung,secure-firmware";
  28                 reg = <0x02073000 0x1000>;
  29         };
  30
  31         fixed-rate-clocks {
  32                 oscclk {
  33                         compatible = "samsung,exynos5420-oscclk";
  34                         clock-frequency = <24000000>;
  35                 };
  36         };
  37
  38         bus_wcore_opp_table: opp-table2 {
  39                 compatible = "operating-points-v2";
  40
  41                 /* derived from 532MHz MPLL */
  42                 opp00 {
  43                         opp-hz = /bits/ 64 <88700000>;
  44                         opp-microvolt = <925000 925000 1400000>;
  45                 };
  46                 opp01 {
  47                         opp-hz = /bits/ 64 <133000000>;
  48                         opp-microvolt = <950000 950000 1400000>;
  49                 };
  50                 opp02 {
  51                         opp-hz = /bits/ 64 <177400000>;
  52                         opp-microvolt = <950000 950000 1400000>;
  53                 };
  54                 opp03 {
  55                         opp-hz = /bits/ 64 <266000000>;
  56                         opp-microvolt = <950000 950000 1400000>;
  57                 };
  58                 opp04 {
  59                         opp-hz = /bits/ 64 <532000000>;
  60                         opp-microvolt = <1000000 1000000 1400000>;
  61                 };
  62         };
  63
  64         bus_noc_opp_table: opp-table3 {
  65                 compatible = "operating-points-v2";
  66
  67                 /* derived from 666MHz CPLL */
  68                 opp00 {
  69                         opp-hz = /bits/ 64 <66600000>;
  70                 };
  71                 opp01 {
  72                         opp-hz = /bits/ 64 <74000000>;
  73                 };
  74                 opp02 {
  75                         opp-hz = /bits/ 64 <83250000>;
  76                 };
  77                 opp03 {
  78                         opp-hz = /bits/ 64 <111000000>;
  79                 };
  80         };
  81
  82         bus_fsys_apb_opp_table: opp-table4 {
  83                 compatible = "operating-points-v2";
  84
  85                 /* derived from 666MHz CPLL */
  86                 opp00 {
  87                         opp-hz = /bits/ 64 <111000000>;
  88                 };
  89                 opp01 {
  90                         opp-hz = /bits/ 64 <222000000>;
  91                 };
  92         };
  93
  94         bus_fsys2_opp_table: opp-table5 {
  95                 compatible = "operating-points-v2";
  96
  97                 /* derived from 600MHz DPLL */
  98                 opp00 {
  99                         opp-hz = /bits/ 64 <75000000>;
 100                 };
 101                 opp01 {
 102                         opp-hz = /bits/ 64 <120000000>;
 103                 };
 104                 opp02 {
 105                         opp-hz = /bits/ 64 <200000000>;
 106                 };
 107         };
 108
 109         bus_mfc_opp_table: opp-table6 {
 110                 compatible = "operating-points-v2";
 111
 112                 /* derived from 666MHz CPLL */
 113                 opp00 {
 114                         opp-hz = /bits/ 64 <83250000>;
 115                 };
 116                 opp01 {
 117                         opp-hz = /bits/ 64 <111000000>;
 118                 };
 119                 opp02 {
 120                         opp-hz = /bits/ 64 <166500000>;
 121                 };
 122                 opp03 {
 123                         opp-hz = /bits/ 64 <222000000>;
 124                 };
 125                 opp04 {
 126                         opp-hz = /bits/ 64 <333000000>;
 127                 };
 128         };
 129
 130         bus_gen_opp_table: opp-table7 {
 131                 compatible = "operating-points-v2";
 132
 133                 /* derived from 532MHz MPLL */
 134                 opp00 {
 135                         opp-hz = /bits/ 64 <88700000>;
 136                 };
 137                 opp01 {
 138                         opp-hz = /bits/ 64 <133000000>;
 139                 };
 140                 opp02 {
 141                         opp-hz = /bits/ 64 <178000000>;
 142                 };
 143                 opp03 {
 144                         opp-hz = /bits/ 64 <266000000>;
 145                 };
 146         };
 147
 148         bus_peri_opp_table: opp-table8 {
 149                 compatible = "operating-points-v2";
 150
 151                 /* derived from 666MHz CPLL */
 152                 opp00 {
 153                         opp-hz = /bits/ 64 <66600000>;
 154                 };
 155         };
 156
 157         bus_g2d_opp_table: opp-table9 {
 158                 compatible = "operating-points-v2";
 159
 160                 /* derived from 666MHz CPLL */
 161                 opp00 {
 162                         opp-hz = /bits/ 64 <83250000>;
 163                 };
 164                 opp01 {
 165                         opp-hz = /bits/ 64 <111000000>;
 166                 };
 167                 opp02 {
 168                         opp-hz = /bits/ 64 <166500000>;
 169                 };
 170                 opp03 {
 171                         opp-hz = /bits/ 64 <222000000>;
 172                 };
 173                 opp04 {
 174                         opp-hz = /bits/ 64 <333000000>;
 175                 };
 176         };
 177
 178         bus_g2d_acp_opp_table: opp-table10 {
 179                 compatible = "operating-points-v2";
 180
 181                 /* derived from 532MHz MPLL */
 182                 opp00 {
 183                         opp-hz = /bits/ 64 <66500000>;
 184                 };
 185                 opp01 {
 186                         opp-hz = /bits/ 64 <133000000>;
 187                 };
 188                 opp02 {
 189                         opp-hz = /bits/ 64 <178000000>;
 190                 };
 191                 opp03 {
 192                         opp-hz = /bits/ 64 <266000000>;
 193                 };
 194         };
 195
 196         bus_jpeg_opp_table: opp-table11 {
 197                 compatible = "operating-points-v2";
 198
 199                 /* derived from 600MHz DPLL */
 200                 opp00 {
 201                         opp-hz = /bits/ 64 <75000000>;
 202                 };
 203                 opp01 {
 204                         opp-hz = /bits/ 64 <150000000>;
 205                 };
 206                 opp02 {
 207                         opp-hz = /bits/ 64 <200000000>;
 208                 };
 209                 opp03 {
 210                         opp-hz = /bits/ 64 <300000000>;
 211                 };
 212         };
 213
 214         bus_jpeg_apb_opp_table: opp-table12 {
 215                 compatible = "operating-points-v2";
 216
 217                 /* derived from 666MHz CPLL */
 218                 opp00 {
 219                         opp-hz = /bits/ 64 <83250000>;
 220                 };
 221                 opp01 {
 222                         opp-hz = /bits/ 64 <111000000>;
 223                 };
 224                 opp02 {
 225                         opp-hz = /bits/ 64 <133000000>;
 226                 };
 227                 opp03 {
 228                         opp-hz = /bits/ 64 <166500000>;
 229                 };
 230         };
 231
 232         bus_disp1_fimd_opp_table: opp-table13 {
 233                 compatible = "operating-points-v2";
 234
 235                 /* derived from 600MHz DPLL */
 236                 opp00 {
 237                         opp-hz = /bits/ 64 <120000000>;
 238                 };
 239                 opp01 {
 240                         opp-hz = /bits/ 64 <200000000>;
 241                 };
 242         };
 243
 244         bus_disp1_opp_table: opp-table14 {
 245                 compatible = "operating-points-v2";
 246
 247                 /* derived from 600MHz DPLL */
 248                 opp00 {
 249                         opp-hz = /bits/ 64 <120000000>;
 250                 };
 251                 opp01 {
 252                         opp-hz = /bits/ 64 <200000000>;
 253                 };
 254                 opp02 {
 255                         opp-hz = /bits/ 64 <300000000>;
 256                 };
 257         };
 258
 259         bus_gscl_opp_table: opp-table15 {
 260                 compatible = "operating-points-v2";
 261
 262                 /* derived from 600MHz DPLL */
 263                 opp00 {
 264                         opp-hz = /bits/ 64 <150000000>;
 265                 };
 266                 opp01 {
 267                         opp-hz = /bits/ 64 <200000000>;
 268                 };
 269                 opp02 {
 270                         opp-hz = /bits/ 64 <300000000>;
 271                 };
 272         };
 273
 274         bus_mscl_opp_table: opp-table16 {
 275                 compatible = "operating-points-v2";
 276
 277                 /* derived from 666MHz CPLL */
 278                 opp00 {
 279                         opp-hz = /bits/ 64 <84000000>;
 280                 };
 281                 opp01 {
 282                         opp-hz = /bits/ 64 <167000000>;
 283                 };
 284                 opp02 {
 285                         opp-hz = /bits/ 64 <222000000>;
 286                 };
 287                 opp03 {
 288                         opp-hz = /bits/ 64 <333000000>;
 289                 };
 290                 opp04 {
 291                         opp-hz = /bits/ 64 <666000000>;
 292                 };
 293         };
 294
 295         dmc_opp_table: opp-table17 {
 296                 compatible = "operating-points-v2";
 297
 298                 opp00 {
 299                         opp-hz = /bits/ 64 <165000000>;
 300                         opp-microvolt = <875000>;
 301                 };
 302                 opp01 {
 303                         opp-hz = /bits/ 64 <206000000>;
 304                         opp-microvolt = <875000>;
 305                 };
 306                 opp02 {
 307                         opp-hz = /bits/ 64 <275000000>;
 308                         opp-microvolt = <875000>;
 309                 };
 310                 opp03 {
 311                         opp-hz = /bits/ 64 <413000000>;
 312                         opp-microvolt = <887500>;
 313                 };
 314                 opp04 {
 315                         opp-hz = /bits/ 64 <543000000>;
 316                         opp-microvolt = <937500>;
 317                 };
 318                 opp05 {
 319                         opp-hz = /bits/ 64 <633000000>;
 320                         opp-microvolt = <1012500>;
 321                 };
 322                 opp06 {
 323                         opp-hz = /bits/ 64 <728000000>;
 324                         opp-microvolt = <1037500>;
 325                 };
 326                 opp07 {
 327                         opp-hz = /bits/ 64 <825000000>;
 328                         opp-microvolt = <1050000>;
 329                 };
 330         };
 331
 332         samsung_K3QF2F20DB: lpddr3 {
 333                 compatible      = "samsung,K3QF2F20DB", "jedec,lpddr3";
 334                 density         = <16384>;
 335                 io-width        = <32>;
 336                 #address-cells  = <1>;
 337                 #size-cells     = <0>;
 338
 339                 tRFC-min-tck            = <17>;
 340                 tRRD-min-tck            = <2>;
 341                 tRPab-min-tck           = <2>;
 342                 tRPpb-min-tck           = <2>;
 343                 tRCD-min-tck            = <3>;
 344                 tRC-min-tck             = <6>;
 345                 tRAS-min-tck            = <5>;
 346                 tWTR-min-tck            = <2>;
 347                 tWR-min-tck             = <7>;
 348                 tRTP-min-tck            = <2>;
 349                 tW2W-C2C-min-tck        = <0>;
 350                 tR2R-C2C-min-tck        = <0>;
 351                 tWL-min-tck             = <8>;
 352                 tDQSCK-min-tck          = <5>;
 353                 tRL-min-tck             = <14>;
 354                 tFAW-min-tck            = <5>;
 355                 tXSR-min-tck            = <12>;
 356                 tXP-min-tck             = <2>;
 357                 tCKE-min-tck            = <2>;
 358                 tCKESR-min-tck          = <2>;
 359                 tMRD-min-tck            = <5>;
 360
 361                 timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
 362                         compatible      = "jedec,lpddr3-timings";
 363                         /* workaround: 'reg' shows max-freq */
 364                         reg             = <800000000>;
 365                         min-freq        = <100000000>;
 366                         tRFC            = <65000>;
 367                         tRRD            = <6000>;
 368                         tRPab           = <12000>;
 369                         tRPpb           = <12000>;
 370                         tRCD            = <10000>;
 371                         tRC             = <33750>;
 372                         tRAS            = <23000>;
 373                         tWTR            = <3750>;
 374                         tWR             = <7500>;
 375                         tRTP            = <3750>;
 376                         tW2W-C2C        = <0>;
 377                         tR2R-C2C        = <0>;
 378                         tFAW            = <25000>;
 379                         tXSR            = <70000>;
 380                         tXP             = <3750>;
 381                         tCKE            = <3750>;
 382                         tCKESR          = <3750>;
 383                         tMRD            = <7000>;
 384                 };
 385         };
 386 };
 387
 388 &adc {
 389         vdd-supply = <&ldo4_reg>;
 390         status = "okay";
 391 };
 392
 393 &bus_wcore {
 394         operating-points-v2 = <&bus_wcore_opp_table>;
 395         devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
 396                         <&nocp_mem1_0>, <&nocp_mem1_1>;
 397         vdd-supply = <&buck3_reg>;
 398         exynos,saturation-ratio = <100>;
 399         status = "okay";
 400 };
 401
 402 &bus_noc {
 403         operating-points-v2 = <&bus_noc_opp_table>;
 404         devfreq = <&bus_wcore>;
 405         status = "okay";
 406 };
 407
 408 &bus_fsys_apb {
 409         operating-points-v2 = <&bus_fsys_apb_opp_table>;
 410         devfreq = <&bus_wcore>;
 411         status = "okay";
 412 };
 413
 414 &bus_fsys2 {
 415         operating-points-v2 = <&bus_fsys2_opp_table>;
 416         devfreq = <&bus_wcore>;
 417         status = "okay";
 418 };
 419
 420 &bus_mfc {
 421         operating-points-v2 = <&bus_mfc_opp_table>;
 422         devfreq = <&bus_wcore>;
 423         status = "okay";
 424 };
 425
 426 &bus_gen {
 427         operating-points-v2 = <&bus_gen_opp_table>;
 428         devfreq = <&bus_wcore>;
 429         status = "okay";
 430 };
 431
 432 &bus_peri {
 433         operating-points-v2 = <&bus_peri_opp_table>;
 434         devfreq = <&bus_wcore>;
 435         status = "okay";
 436 };
 437
 438 &bus_g2d {
 439         operating-points-v2 = <&bus_g2d_opp_table>;
 440         devfreq = <&bus_wcore>;
 441         status = "okay";
 442 };
 443
 444 &bus_g2d_acp {
 445         operating-points-v2 = <&bus_g2d_acp_opp_table>;
 446         devfreq = <&bus_wcore>;
 447         status = "okay";
 448 };
 449
 450 &bus_jpeg {
 451         operating-points-v2 = <&bus_jpeg_opp_table>;
 452         devfreq = <&bus_wcore>;
 453         status = "okay";
 454 };
 455
 456 &bus_jpeg_apb {
 457         operating-points-v2 = <&bus_jpeg_apb_opp_table>;
 458         devfreq = <&bus_wcore>;
 459         status = "okay";
 460 };
 461
 462 &bus_disp1_fimd {
 463         operating-points-v2 = <&bus_disp1_fimd_opp_table>;
 464         devfreq = <&bus_wcore>;
 465         status = "okay";
 466 };
 467
 468 &bus_disp1 {
 469         operating-points-v2 = <&bus_disp1_opp_table>;
 470         devfreq = <&bus_wcore>;
 471         status = "okay";
 472 };
 473
 474 &bus_gscl_scaler {
 475         operating-points-v2 = <&bus_gscl_opp_table>;
 476         devfreq = <&bus_wcore>;
 477         status = "okay";
 478 };
 479
 480 &bus_mscl {
 481         operating-points-v2 = <&bus_mscl_opp_table>;
 482         devfreq = <&bus_wcore>;
 483         status = "okay";
 484 };
 485
 486 &cpu0 {
 487         cpu-supply = <&buck6_reg>;
 488 };
 489
 490 &cpu4 {
 491         cpu-supply = <&buck2_reg>;
 492 };
 493
 494 &dmc {
 495         devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
 496                         <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
 497         device-handle = <&samsung_K3QF2F20DB>;
 498         operating-points-v2 = <&dmc_opp_table>;
 499         vdd-supply = <&buck1_reg>;
 500         status = "okay";
 501 };
 502
 503 &hsi2c_4 {
 504         status = "okay";
 505
 506         pmic@66 {
 507                 compatible = "samsung,s2mps11-pmic";
 508                 reg = <0x66>;
 509                 samsung,s2mps11-acokb-ground;
 510
 511                 interrupt-parent = <&gpx0>;
 512                 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
 513                 pinctrl-names = "default";
 514                 pinctrl-0 = <&s2mps11_irq>;
 515
 516                 s2mps11_osc: clocks {
 517                         compatible = "samsung,s2mps11-clk";
 518                         #clock-cells = <1>;
 519                         clock-output-names = "s2mps11_ap",
 520                                         "s2mps11_cp", "s2mps11_bt";
 521                 };
 522
 523                 regulators {
 524                         ldo1_reg: LDO1 {
 525                                 regulator-name = "vdd_ldo1";
 526                                 regulator-min-microvolt = <1000000>;
 527                                 regulator-max-microvolt = <1000000>;
 528                                 regulator-always-on;
 529                         };
 530
 531                         ldo2_reg: LDO2 {
 532                                 regulator-name = "vdd_ldo2";
 533                                 regulator-min-microvolt = <1800000>;
 534                                 regulator-max-microvolt = <1800000>;
 535                                 regulator-always-on;
 536                         };
 537
 538                         ldo3_reg: LDO3 {
 539                                 regulator-name = "vddq_mmc0";
 540                                 regulator-min-microvolt = <1800000>;
 541                                 regulator-max-microvolt = <1800000>;
 542                         };
 543
 544                         ldo4_reg: LDO4 {
 545                                 regulator-name = "vdd_adc";
 546                                 regulator-min-microvolt = <1800000>;
 547                                 regulator-max-microvolt = <1800000>;
 548
 549                                 regulator-state-mem {
 550                                         regulator-off-in-suspend;
 551                                 };
 552                         };
 553
 554                         ldo5_reg: LDO5 {
 555                                 regulator-name = "vdd_ldo5";
 556                                 regulator-min-microvolt = <1800000>;
 557                                 regulator-max-microvolt = <1800000>;
 558                                 regulator-always-on;
 559
 560                                 regulator-state-mem {
 561                                         regulator-off-in-suspend;
 562                                 };
 563                         };
 564
 565                         ldo6_reg: LDO6 {
 566                                 regulator-name = "vdd_ldo6";
 567                                 regulator-min-microvolt = <1000000>;
 568                                 regulator-max-microvolt = <1000000>;
 569                                 regulator-always-on;
 570
 571                                 regulator-state-mem {
 572                                         regulator-off-in-suspend;
 573                                 };
 574                         };
 575
 576                         ldo7_reg: LDO7 {
 577                                 regulator-name = "vdd_ldo7";
 578                                 regulator-min-microvolt = <1800000>;
 579                                 regulator-max-microvolt = <1800000>;
 580                                 regulator-always-on;
 581
 582                                 regulator-state-mem {
 583                                         regulator-off-in-suspend;
 584                                 };
 585                         };
 586
 587                         ldo8_reg: LDO8 {
 588                                 regulator-name = "vdd_ldo8";
 589                                 regulator-min-microvolt = <1800000>;
 590                                 regulator-max-microvolt = <1800000>;
 591                                 regulator-always-on;
 592
 593                                 regulator-state-mem {
 594                                         regulator-off-in-suspend;
 595                                 };
 596                         };
 597
 598                         ldo9_reg: LDO9 {
 599                                 regulator-name = "vdd_ldo9";
 600                                 regulator-min-microvolt = <3000000>;
 601                                 regulator-max-microvolt = <3000000>;
 602                                 regulator-always-on;
 603
 604                                 regulator-state-mem {
 605                                         regulator-off-in-suspend;
 606                                 };
 607                         };
 608
 609                         ldo10_reg: LDO10 {
 610                                 regulator-name = "vdd_ldo10";
 611                                 regulator-min-microvolt = <1800000>;
 612                                 regulator-max-microvolt = <1800000>;
 613                                 regulator-always-on;
 614
 615                                 regulator-state-mem {
 616                                         regulator-off-in-suspend;
 617                                 };
 618                         };
 619
 620                         ldo11_reg: LDO11 {
 621                                 regulator-name = "vdd_ldo11";
 622                                 regulator-min-microvolt = <1000000>;
 623                                 regulator-max-microvolt = <1000000>;
 624                                 regulator-always-on;
 625
 626                                 regulator-state-mem {
 627                                         regulator-off-in-suspend;
 628                                 };
 629                         };
 630
 631                         ldo12_reg: LDO12 {
 632                                 /* Unused */
 633                                 regulator-name = "vdd_ldo12";
 634                                 regulator-min-microvolt = <800000>;
 635                                 regulator-max-microvolt = <2375000>;
 636                         };
 637
 638                         ldo13_reg: LDO13 {
 639                                 regulator-name = "vddq_mmc2";
 640                                 regulator-min-microvolt = <1800000>;
 641                                 regulator-max-microvolt = <2800000>;
 642
 643                                 regulator-state-mem {
 644                                         regulator-off-in-suspend;
 645                                 };
 646                         };
 647
 648                         ldo14_reg: LDO14 {
 649                                 /* Unused */
 650                                 regulator-name = "vdd_ldo14";
 651                                 regulator-min-microvolt = <800000>;
 652                                 regulator-max-microvolt = <3950000>;
 653                         };
 654
 655                         ldo15_reg: LDO15 {
 656                                 regulator-name = "vdd_ldo15";
 657                                 regulator-min-microvolt = <3300000>;
 658                                 regulator-max-microvolt = <3300000>;
 659                                 regulator-always-on;
 660
 661                                 regulator-state-mem {
 662                                         regulator-off-in-suspend;
 663                                 };
 664                         };
 665
 666                         ldo16_reg: LDO16 {
 667                                 /* Unused */
 668                                 regulator-name = "vdd_ldo16";
 669                                 regulator-min-microvolt = <800000>;
 670                                 regulator-max-microvolt = <3950000>;
 671                         };
 672
 673                         ldo17_reg: LDO17 {
 674                                 regulator-name = "vdd_ldo17";
 675                                 regulator-min-microvolt = <3300000>;
 676                                 regulator-max-microvolt = <3300000>;
 677                                 regulator-always-on;
 678
 679                                 regulator-state-mem {
 680                                         regulator-off-in-suspend;
 681                                 };
 682                         };
 683
 684                         ldo18_reg: LDO18 {
 685                                 regulator-name = "vdd_emmc_1V8";
 686                                 regulator-min-microvolt = <1800000>;
 687                                 regulator-max-microvolt = <1800000>;
 688
 689                                 regulator-state-mem {
 690                                         regulator-off-in-suspend;
 691                                 };
 692                         };
 693
 694                         ldo19_reg: LDO19 {
 695                                 regulator-name = "vdd_sd";
 696                                 regulator-min-microvolt = <2800000>;
 697                                 regulator-max-microvolt = <2800000>;
 698
 699                                 regulator-state-mem {
 700                                         regulator-off-in-suspend;
 701                                 };
 702                         };
 703
 704                         ldo20_reg: LDO20 {
 705                                 /* Unused */
 706                                 regulator-name = "vdd_ldo20";
 707                                 regulator-min-microvolt = <800000>;
 708                                 regulator-max-microvolt = <3950000>;
 709                         };
 710
 711                         ldo21_reg: LDO21 {
 712                                 /* Unused */
 713                                 regulator-name = "vdd_ldo21";
 714                                 regulator-min-microvolt = <800000>;
 715                                 regulator-max-microvolt = <3950000>;
 716                         };
 717
 718                         ldo22_reg: LDO22 {
 719                                 /* Unused */
 720                                 regulator-name = "vdd_ldo22";
 721                                 regulator-min-microvolt = <800000>;
 722                                 regulator-max-microvolt = <2375000>;
 723                         };
 724
 725                         ldo23_reg: LDO23 {
 726                                 regulator-name = "vdd_mifs";
 727                                 regulator-min-microvolt = <1100000>;
 728                                 regulator-max-microvolt = <1100000>;
 729                                 regulator-always-on;
 730
 731                                 regulator-state-mem {
 732                                         regulator-off-in-suspend;
 733                                 };
 734                         };
 735
 736                         ldo24_reg: LDO24 {
 737                                 /* Unused */
 738                                 regulator-name = "vdd_ldo24";
 739                                 regulator-min-microvolt = <800000>;
 740                                 regulator-max-microvolt = <3950000>;
 741                         };
 742
 743                         ldo25_reg: LDO25 {
 744                                 /* Unused */
 745                                 regulator-name = "vdd_ldo25";
 746                                 regulator-min-microvolt = <800000>;
 747                                 regulator-max-microvolt = <3950000>;
 748                         };
 749
 750                         ldo26_reg: LDO26 {
 751                                 /* Used on XU3, XU3-Lite and XU4 */
 752                                 regulator-name = "vdd_ldo26";
 753                                 regulator-min-microvolt = <800000>;
 754                                 regulator-max-microvolt = <3950000>;
 755
 756                                 regulator-state-mem {
 757                                         regulator-off-in-suspend;
 758                                 };
 759                         };
 760
 761                         ldo27_reg: LDO27 {
 762                                 regulator-name = "vdd_g3ds";
 763                                 regulator-min-microvolt = <1000000>;
 764                                 regulator-max-microvolt = <1000000>;
 765                                 regulator-always-on;
 766
 767                                 regulator-state-mem {
 768                                         regulator-off-in-suspend;
 769                                 };
 770                         };
 771
 772                         ldo28_reg: LDO28 {
 773                                 /* Used on XU3 */
 774                                 regulator-name = "vdd_ldo28";
 775                                 regulator-min-microvolt = <800000>;
 776                                 regulator-max-microvolt = <3950000>;
 777
 778                                 regulator-state-mem {
 779                                         regulator-off-in-suspend;
 780                                 };
 781                         };
 782
 783                         ldo29_reg: LDO29 {
 784                                 /* Unused */
 785                                 regulator-name = "vdd_ldo29";
 786                                 regulator-min-microvolt = <800000>;
 787                                 regulator-max-microvolt = <3950000>;
 788                         };
 789
 790                         ldo30_reg: LDO30 {
 791                                 /* Unused */
 792                                 regulator-name = "vdd_ldo30";
 793                                 regulator-min-microvolt = <800000>;
 794                                 regulator-max-microvolt = <3950000>;
 795                         };
 796
 797                         ldo31_reg: LDO31 {
 798                                 /* Unused */
 799                                 regulator-name = "vdd_ldo31";
 800                                 regulator-min-microvolt = <800000>;
 801                                 regulator-max-microvolt = <3950000>;
 802                         };
 803
 804                         ldo32_reg: LDO32 {
 805                                 /* Unused */
 806                                 regulator-name = "vdd_ldo32";
 807                                 regulator-min-microvolt = <800000>;
 808                                 regulator-max-microvolt = <3950000>;
 809                         };
 810
 811                         ldo33_reg: LDO33 {
 812                                 /* Unused */
 813                                 regulator-name = "vdd_ldo33";
 814                                 regulator-min-microvolt = <800000>;
 815                                 regulator-max-microvolt = <3950000>;
 816                         };
 817
 818                         ldo34_reg: LDO34 {
 819                                 /* Unused */
 820                                 regulator-name = "vdd_ldo34";
 821                                 regulator-min-microvolt = <800000>;
 822                                 regulator-max-microvolt = <3950000>;
 823                         };
 824
 825                         ldo35_reg: LDO35 {
 826                                 /* Unused */
 827                                 regulator-name = "vdd_ldo35";
 828                                 regulator-min-microvolt = <800000>;
 829                                 regulator-max-microvolt = <2375000>;
 830                         };
 831
 832                         ldo36_reg: LDO36 {
 833                                 /* Unused */
 834                                 regulator-name = "vdd_ldo36";
 835                                 regulator-min-microvolt = <800000>;
 836                                 regulator-max-microvolt = <3950000>;
 837                         };
 838
 839                         ldo37_reg: LDO37 {
 840                                 /* Unused */
 841                                 regulator-name = "vdd_ldo37";
 842                                 regulator-min-microvolt = <800000>;
 843                                 regulator-max-microvolt = <3950000>;
 844                         };
 845
 846                         ldo38_reg: LDO38 {
 847                                 /* Unused */
 848                                 regulator-name = "vdd_ldo38";
 849                                 regulator-min-microvolt = <800000>;
 850                                 regulator-max-microvolt = <3950000>;
 851                         };
 852
 853                         buck1_reg: BUCK1 {
 854                                 regulator-name = "vdd_mif";
 855                                 regulator-min-microvolt = <800000>;
 856                                 regulator-max-microvolt = <1300000>;
 857                                 regulator-always-on;
 858                                 regulator-boot-on;
 859
 860                                 regulator-state-mem {
 861                                         regulator-off-in-suspend;
 862                                 };
 863                         };
 864
 865                         buck2_reg: BUCK2 {
 866                                 regulator-name = "vdd_arm";
 867                                 regulator-min-microvolt = <800000>;
 868                                 regulator-max-microvolt = <1500000>;
 869                                 regulator-always-on;
 870                                 regulator-boot-on;
 871                                 regulator-coupled-with = <&buck3_reg>;
 872                                 regulator-coupled-max-spread = <300000>;
 873
 874                                 regulator-state-mem {
 875                                         regulator-off-in-suspend;
 876                                 };
 877                         };
 878
 879                         buck3_reg: BUCK3 {
 880                                 regulator-name = "vdd_int";
 881                                 regulator-min-microvolt = <800000>;
 882                                 regulator-max-microvolt = <1400000>;
 883                                 regulator-always-on;
 884                                 regulator-boot-on;
 885                                 regulator-coupled-with = <&buck2_reg>;
 886                                 regulator-coupled-max-spread = <300000>;
 887
 888                                 regulator-state-mem {
 889                                         regulator-off-in-suspend;
 890                                 };
 891                         };
 892
 893                         buck4_reg: BUCK4 {
 894                                 regulator-name = "vdd_g3d";
 895                                 regulator-min-microvolt = <800000>;
 896                                 regulator-max-microvolt = <1400000>;
 897                                 regulator-boot-on;
 898                                 regulator-always-on;
 899
 900                                 regulator-state-mem {
 901                                         regulator-off-in-suspend;
 902                                 };
 903                         };
 904
 905                         buck5_reg: BUCK5 {
 906                                 regulator-name = "vdd_mem";
 907                                 regulator-min-microvolt = <800000>;
 908                                 regulator-max-microvolt = <1400000>;
 909                                 regulator-always-on;
 910                                 regulator-boot-on;
 911                         };
 912
 913                         buck6_reg: BUCK6 {
 914                                 regulator-name = "vdd_kfc";
 915                                 regulator-min-microvolt = <800000>;
 916                                 regulator-max-microvolt = <1500000>;
 917                                 regulator-always-on;
 918                                 regulator-boot-on;
 919
 920                                 regulator-state-mem {
 921                                         regulator-off-in-suspend;
 922                                 };
 923                         };
 924
 925                         buck7_reg: BUCK7 {
 926                                 regulator-name = "vdd_1.35v_ldo";
 927                                 regulator-min-microvolt = <1200000>;
 928                                 regulator-max-microvolt = <1500000>;
 929                                 regulator-always-on;
 930                                 regulator-boot-on;
 931                         };
 932
 933                         buck8_reg: BUCK8 {
 934                                 regulator-name = "vdd_2.0v_ldo";
 935                                 regulator-min-microvolt = <1800000>;
 936                                 regulator-max-microvolt = <2100000>;
 937                                 regulator-always-on;
 938                                 regulator-boot-on;
 939                         };
 940
 941                         buck9_reg: BUCK9 {
 942                                 regulator-name = "vdd_2.8v_ldo";
 943                                 regulator-min-microvolt = <3000000>;
 944                                 regulator-max-microvolt = <3750000>;
 945                                 regulator-always-on;
 946                                 regulator-boot-on;
 947
 948                                 regulator-state-mem {
 949                                         regulator-off-in-suspend;
 950                                 };
 951                         };
 952
 953                         buck10_reg: BUCK10 {
 954                                 regulator-name = "vdd_vmem";
 955                                 regulator-min-microvolt = <2850000>;
 956                                 regulator-max-microvolt = <2850000>;
 957
 958                                 regulator-state-mem {
 959                                         regulator-off-in-suspend;
 960                                 };
 961                         };
 962                 };
 963         };
 964 };
 965
 966 &mmc_2 {
 967         status = "okay";
 968         card-detect-delay = <200>;
 969         samsung,dw-mshc-ciu-div = <3>;
 970         samsung,dw-mshc-sdr-timing = <0 4>;
 971         samsung,dw-mshc-ddr-timing = <0 2>;
 972         pinctrl-names = "default";
 973         pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
 974         bus-width = <4>;
 975         cap-sd-highspeed;
 976         max-frequency = <200000000>;
 977         vmmc-supply = <&ldo19_reg>;
 978         vqmmc-supply = <&ldo13_reg>;
 979         sd-uhs-sdr50;
 980         sd-uhs-sdr104;
 981         sd-uhs-ddr50;
 982 };
 983
 984 &nocp_mem0_0 {
 985         status = "okay";
 986 };
 987
 988 &nocp_mem0_1 {
 989         status = "okay";
 990 };
 991
 992 &nocp_mem1_0 {
 993         status = "okay";
 994 };
 995
 996 &nocp_mem1_1 {
 997         status = "okay";
 998 };
 999
1000 &pinctrl_0 {
1001         s2mps11_irq: s2mps11-irq {
1002                 samsung,pins = "gpx0-4";
1003                 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
1004                 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1005                 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1006         };
1007 };
1008
1009 &ppmu_dmc0_0 {
1010         status = "okay";
1011 };
1012
1013 &ppmu_dmc0_1 {
1014         status = "okay";
1015 };
1016
1017 &ppmu_dmc1_0 {
1018         status = "okay";
1019 };
1020
1021 &ppmu_dmc1_1 {
1022         status = "okay";
1023 };
1024
1025 &tmu_cpu0 {
1026         vtmu-supply = <&ldo7_reg>;
1027 };
1028
1029 &tmu_cpu1 {
1030         vtmu-supply = <&ldo7_reg>;
1031 };
1032
1033 &tmu_cpu2 {
1034         vtmu-supply = <&ldo7_reg>;
1035 };
1036
1037 &tmu_cpu3 {
1038         vtmu-supply = <&ldo7_reg>;
1039 };
1040
1041 &tmu_gpu {
1042         vtmu-supply = <&ldo7_reg>;
1043 };
1044
1045 &gpu {
1046         mali-supply = <&buck4_reg>;
1047         status = "okay";
1048 };
1049
1050 &rtc {
1051         status = "okay";
1052         clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
1053         clock-names = "rtc", "rtc_src";
1054 };
1055
1056 &usbdrd_dwc3_0 {
1057         dr_mode = "host";
1058 };
1059
1060 /* usbdrd_dwc3_1 mode customized in each board */
1061
1062 &usbdrd3_0 {
1063         vdd33-supply = <&ldo9_reg>;
1064         vdd10-supply = <&ldo11_reg>;
1065 };
1066
1067 &usbdrd3_1 {
1068         vdd33-supply = <&ldo9_reg>;
1069         vdd10-supply = <&ldo11_reg>;
1070 };