arch/arm/boot/dts/exynos3250.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos3250 SoC device tree source
   4  *
   5  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   9  * based board files can include this file and provide values for board specfic
  10  * bindings.
  11  *
  12  * Note: This file does not include device nodes for all the controllers in
  13  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  14  * nodes can be added to this file.
  15  */
  16
  17 #include "exynos4-cpu-thermal.dtsi"
  18 #include <dt-bindings/clock/exynos3250.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/interrupt-controller/irq.h>
  21
  22 / {
  23         compatible = "samsung,exynos3250";
  24         interrupt-parent = <&gic>;
  25         #address-cells = <1>;
  26         #size-cells = <1>;
  27
  28         aliases {
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 mshc0 = &mshc_0;
  32                 mshc1 = &mshc_1;
  33                 mshc2 = &mshc_2;
  34                 spi0 = &spi_0;
  35                 spi1 = &spi_1;
  36                 i2c0 = &i2c_0;
  37                 i2c1 = &i2c_1;
  38                 i2c2 = &i2c_2;
  39                 i2c3 = &i2c_3;
  40                 i2c4 = &i2c_4;
  41                 i2c5 = &i2c_5;
  42                 i2c6 = &i2c_6;
  43                 i2c7 = &i2c_7;
  44                 serial0 = &serial_0;
  45                 serial1 = &serial_1;
  46                 serial2 = &serial_2;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu-map {
  54                         cluster0 {
  55                                 core0 {
  56                                         cpu = <&cpu0>;
  57                                 };
  58                                 core1 {
  59                                         cpu = <&cpu1>;
  60                                 };
  61                         };
  62                 };
  63
  64                 cpu0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         reg = <0>;
  68                         clock-frequency = <1000000000>;
  69                         clocks = <&cmu CLK_ARM_CLK>;
  70                         clock-names = "cpu";
  71                         #cooling-cells = <2>;
  72
  73                         operating-points = <
  74                                 1000000 1150000
  75                                 900000  1112500
  76                                 800000  1075000
  77                                 700000  1037500
  78                                 600000  1000000
  79                                 500000  962500
  80                                 400000  925000
  81                                 300000  887500
  82                                 200000  850000
  83                                 100000  850000
  84                         >;
  85                 };
  86
  87                 cpu1: cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a7";
  90                         reg = <1>;
  91                         clock-frequency = <1000000000>;
  92                         clocks = <&cmu CLK_ARM_CLK>;
  93                         clock-names = "cpu";
  94                         #cooling-cells = <2>;
  95
  96                         operating-points = <
  97                                 1000000 1150000
  98                                 900000  1112500
  99                                 800000  1075000
 100                                 700000  1037500
 101                                 600000  1000000
 102                                 500000  962500
 103                                 400000  925000
 104                                 300000  887500
 105                                 200000  850000
 106                                 100000  850000
 107                         >;
 108                 };
 109         };
 110
 111         xusbxti: clock-0 {
 112                 compatible = "fixed-clock";
 113                 clock-frequency = <0>;
 114                 #clock-cells = <0>;
 115                 clock-output-names = "xusbxti";
 116         };
 117
 118         xxti: clock-1 {
 119                 compatible = "fixed-clock";
 120                 clock-frequency = <0>;
 121                 #clock-cells = <0>;
 122                 clock-output-names = "xxti";
 123         };
 124
 125         xtcxo: clock-2 {
 126                 compatible = "fixed-clock";
 127                 clock-frequency = <0>;
 128                 #clock-cells = <0>;
 129                 clock-output-names = "xtcxo";
 130         };
 131
 132         pmu {
 133                 compatible = "arm,cortex-a7-pmu";
 134                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 135                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 136         };
 137
 138         soc: soc {
 139                 compatible = "simple-bus";
 140                 #address-cells = <1>;
 141                 #size-cells = <1>;
 142                 ranges;
 143
 144                 sram@2020000 {
 145                         compatible = "mmio-sram";
 146                         reg = <0x02020000 0x40000>;
 147                         #address-cells = <1>;
 148                         #size-cells = <1>;
 149                         ranges = <0 0x02020000 0x40000>;
 150
 151                         smp-sram@0 {
 152                                 compatible = "samsung,exynos4210-sysram";
 153                                 reg = <0x0 0x1000>;
 154                         };
 155
 156                         smp-sram@3f000 {
 157                                 compatible = "samsung,exynos4210-sysram-ns";
 158                                 reg = <0x3f000 0x1000>;
 159                         };
 160                 };
 161
 162                 chipid@10000000 {
 163                         compatible = "samsung,exynos4210-chipid";
 164                         reg = <0x10000000 0x100>;
 165                 };
 166
 167                 sys_reg: syscon@10010000 {
 168                         compatible = "samsung,exynos3-sysreg", "syscon";
 169                         reg = <0x10010000 0x400>;
 170                 };
 171
 172                 pmu_system_controller: system-controller@10020000 {
 173                         compatible = "samsung,exynos3250-pmu", "syscon";
 174                         reg = <0x10020000 0x4000>;
 175                         interrupt-controller;
 176                         #interrupt-cells = <3>;
 177                         interrupt-parent = <&gic>;
 178                         clock-names = "clkout8";
 179                         clocks = <&cmu CLK_FIN_PLL>;
 180                         #clock-cells = <1>;
 181                 };
 182
 183                 mipi_phy: video-phy {
 184                         compatible = "samsung,s5pv210-mipi-video-phy";
 185                         #phy-cells = <1>;
 186                         syscon = <&pmu_system_controller>;
 187                 };
 188
 189                 pd_cam: power-domain@10023c00 {
 190                         compatible = "samsung,exynos4210-pd";
 191                         reg = <0x10023C00 0x20>;
 192                         #power-domain-cells = <0>;
 193                         label = "CAM";
 194                 };
 195
 196                 pd_mfc: power-domain@10023c40 {
 197                         compatible = "samsung,exynos4210-pd";
 198                         reg = <0x10023C40 0x20>;
 199                         #power-domain-cells = <0>;
 200                         label = "MFC";
 201                 };
 202
 203                 pd_g3d: power-domain@10023c60 {
 204                         compatible = "samsung,exynos4210-pd";
 205                         reg = <0x10023C60 0x20>;
 206                         #power-domain-cells = <0>;
 207                         label = "G3D";
 208                 };
 209
 210                 pd_lcd0: power-domain@10023c80 {
 211                         compatible = "samsung,exynos4210-pd";
 212                         reg = <0x10023C80 0x20>;
 213                         #power-domain-cells = <0>;
 214                         label = "LCD0";
 215                 };
 216
 217                 pd_isp: power-domain@10023ca0 {
 218                         compatible = "samsung,exynos4210-pd";
 219                         reg = <0x10023CA0 0x20>;
 220                         #power-domain-cells = <0>;
 221                         label = "ISP";
 222                 };
 223
 224                 cmu: clock-controller@10030000 {
 225                         compatible = "samsung,exynos3250-cmu";
 226                         reg = <0x10030000 0x20000>;
 227                         #clock-cells = <1>;
 228                         assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
 229                                           <&cmu CLK_MOUT_ACLK_266_SUB>;
 230                         assigned-clock-parents = <&cmu CLK_FIN_PLL>,
 231                                                  <&cmu CLK_FIN_PLL>;
 232                 };
 233
 234                 cmu_dmc: clock-controller@105c0000 {
 235                         compatible = "samsung,exynos3250-cmu-dmc";
 236                         reg = <0x105C0000 0x2000>;
 237                         #clock-cells = <1>;
 238                 };
 239
 240                 rtc: rtc@10070000 {
 241                         compatible = "samsung,s3c6410-rtc";
 242                         reg = <0x10070000 0x100>;
 243                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 245                         interrupt-parent = <&pmu_system_controller>;
 246                         status = "disabled";
 247                 };
 248
 249                 tmu: tmu@100c0000 {
 250                         compatible = "samsung,exynos3250-tmu";
 251                         reg = <0x100C0000 0x100>;
 252                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&cmu CLK_TMU_APBIF>;
 254                         clock-names = "tmu_apbif";
 255                         #thermal-sensor-cells = <0>;
 256                         status = "disabled";
 257                 };
 258
 259                 gic: interrupt-controller@10481000 {
 260                         compatible = "arm,cortex-a15-gic";
 261                         #interrupt-cells = <3>;
 262                         interrupt-controller;
 263                         reg = <0x10481000 0x1000>,
 264                               <0x10482000 0x2000>,
 265                               <0x10484000 0x2000>,
 266                               <0x10486000 0x2000>;
 267                         interrupts = <GIC_PPI 9
 268                                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 269                 };
 270
 271                 timer@10050000 {
 272                         compatible = "samsung,exynos4210-mct";
 273                         reg = <0x10050000 0x800>;
 274                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 275                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 277                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
 278                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
 279                                      <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
 280                                      <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
 281                                      <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 282                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 283                         clock-names = "fin_pll", "mct";
 284                 };
 285
 286                 pinctrl_1: pinctrl@11000000 {
 287                         compatible = "samsung,exynos3250-pinctrl";
 288                         reg = <0x11000000 0x1000>;
 289                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 290
 291                         wakeup-interrupt-controller {
 292                                 compatible = "samsung,exynos4210-wakeup-eint";
 293                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 294                         };
 295                 };
 296
 297                 pinctrl_0: pinctrl@11400000 {
 298                         compatible = "samsung,exynos3250-pinctrl";
 299                         reg = <0x11400000 0x1000>;
 300                         interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 301                 };
 302
 303                 jpeg: codec@11830000 {
 304                         compatible = "samsung,exynos3250-jpeg";
 305                         reg = <0x11830000 0x1000>;
 306                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 307                         clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
 308                         clock-names = "jpeg", "sclk";
 309                         power-domains = <&pd_cam>;
 310                         assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
 311                         assigned-clock-rates = <0>, <150000000>;
 312                         assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
 313                         iommus = <&sysmmu_jpeg>;
 314                         status = "disabled";
 315                 };
 316
 317                 sysmmu_jpeg: sysmmu@11a60000 {
 318                         compatible = "samsung,exynos-sysmmu";
 319                         reg = <0x11a60000 0x1000>;
 320                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 321                         clock-names = "sysmmu", "master";
 322                         clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
 323                         power-domains = <&pd_cam>;
 324                         #iommu-cells = <0>;
 325                 };
 326
 327                 fimd: fimd@11c00000 {
 328                         compatible = "samsung,exynos3250-fimd";
 329                         reg = <0x11c00000 0x30000>;
 330                         interrupt-names = "fifo", "vsync", "lcd_sys";
 331                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 332                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 333                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 335                         clock-names = "sclk_fimd", "fimd";
 336                         power-domains = <&pd_lcd0>;
 337                         iommus = <&sysmmu_fimd0>;
 338                         samsung,sysreg = <&sys_reg>;
 339                         status = "disabled";
 340                 };
 341
 342                 dsi_0: dsi@11c80000 {
 343                         compatible = "samsung,exynos3250-mipi-dsi";
 344                         reg = <0x11C80000 0x10000>;
 345                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 346                         samsung,phy-type = <0>;
 347                         power-domains = <&pd_lcd0>;
 348                         phys = <&mipi_phy 1>;
 349                         phy-names = "dsim";
 350                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 351                         clock-names = "bus_clk", "pll_clk";
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354                         status = "disabled";
 355                 };
 356
 357                 sysmmu_fimd0: sysmmu@11e20000 {
 358                         compatible = "samsung,exynos-sysmmu";
 359                         reg = <0x11e20000 0x1000>;
 360                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 361                         clock-names = "sysmmu", "master";
 362                         clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
 363                         power-domains = <&pd_lcd0>;
 364                         #iommu-cells = <0>;
 365                 };
 366
 367                 hsotg: hsotg@12480000 {
 368                         compatible = "samsung,s3c6400-hsotg";
 369                         reg = <0x12480000 0x20000>;
 370                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 371                         clocks = <&cmu CLK_USBOTG>;
 372                         clock-names = "otg";
 373                         phys = <&exynos_usbphy 0>;
 374                         phy-names = "usb2-phy";
 375                         status = "disabled";
 376                 };
 377
 378                 mshc_0: mshc@12510000 {
 379                         compatible = "samsung,exynos5420-dw-mshc";
 380                         reg = <0x12510000 0x1000>;
 381                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 382                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 383                         clock-names = "biu", "ciu";
 384                         fifo-depth = <0x80>;
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                         status = "disabled";
 388                 };
 389
 390                 mshc_1: mshc@12520000 {
 391                         compatible = "samsung,exynos5420-dw-mshc";
 392                         reg = <0x12520000 0x1000>;
 393                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 395                         clock-names = "biu", "ciu";
 396                         fifo-depth = <0x80>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         status = "disabled";
 400                 };
 401
 402                 mshc_2: mshc@12530000 {
 403                         compatible = "samsung,exynos5250-dw-mshc";
 404                         reg = <0x12530000 0x1000>;
 405                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 406                         clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
 407                         clock-names = "biu", "ciu";
 408                         fifo-depth = <0x80>;
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411                         status = "disabled";
 412                 };
 413
 414                 exynos_usbphy: exynos-usbphy@125b0000 {
 415                         compatible = "samsung,exynos3250-usb2-phy";
 416                         reg = <0x125B0000 0x100>;
 417                         samsung,pmureg-phandle = <&pmu_system_controller>;
 418                         clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
 419                         clock-names = "phy", "ref";
 420                         #phy-cells = <1>;
 421                         status = "disabled";
 422                 };
 423
 424                 pdma0: pdma@12680000 {
 425                         compatible = "arm,pl330", "arm,primecell";
 426                         reg = <0x12680000 0x1000>;
 427                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 428                         clocks = <&cmu CLK_PDMA0>;
 429                         clock-names = "apb_pclk";
 430                         #dma-cells = <1>;
 431                         #dma-channels = <8>;
 432                         #dma-requests = <32>;
 433                 };
 434
 435                 pdma1: pdma@12690000 {
 436                         compatible = "arm,pl330", "arm,primecell";
 437                         reg = <0x12690000 0x1000>;
 438                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 439                         clocks = <&cmu CLK_PDMA1>;
 440                         clock-names = "apb_pclk";
 441                         #dma-cells = <1>;
 442                         #dma-channels = <8>;
 443                         #dma-requests = <32>;
 444                 };
 445
 446                 adc: adc@126c0000 {
 447                         compatible = "samsung,exynos3250-adc";
 448                         reg = <0x126C0000 0x100>;
 449                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 450                         clock-names = "adc", "sclk";
 451                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 452                         #io-channel-cells = <1>;
 453                         samsung,syscon-phandle = <&pmu_system_controller>;
 454                         status = "disabled";
 455                 };
 456
 457                 gpu: gpu@13000000 {
 458                         compatible = "samsung,exynos4210-mali", "arm,mali-400";
 459                         reg = <0x13000000 0x10000>;
 460                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 461                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 462                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 463                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 464                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 465                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 466                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 467                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
 468                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 469                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 470                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 471                         interrupt-names = "gp",
 472                                           "gpmmu",
 473                                           "pp0",
 474                                           "ppmmu0",
 475                                           "pp1",
 476                                           "ppmmu1",
 477                                           "pp2",
 478                                           "ppmmu2",
 479                                           "pp3",
 480                                           "ppmmu3",
 481                                           "pmu";
 482                         clocks = <&cmu CLK_G3D>,
 483                                  <&cmu CLK_SCLK_G3D>;
 484                         clock-names = "bus", "core";
 485                         power-domains = <&pd_g3d>;
 486                         status = "disabled";
 487                         /* TODO: operating points for DVFS, assigned clock as 134 MHz */
 488                 };
 489
 490                 mfc: codec@13400000 {
 491                         compatible = "samsung,mfc-v7";
 492                         reg = <0x13400000 0x10000>;
 493                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 494                         clock-names = "mfc", "sclk_mfc";
 495                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
 496                         power-domains = <&pd_mfc>;
 497                         iommus = <&sysmmu_mfc>;
 498                 };
 499
 500                 sysmmu_mfc: sysmmu@13620000 {
 501                         compatible = "samsung,exynos-sysmmu";
 502                         reg = <0x13620000 0x1000>;
 503                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 504                         clock-names = "sysmmu", "master";
 505                         clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
 506                         power-domains = <&pd_mfc>;
 507                         #iommu-cells = <0>;
 508                 };
 509
 510                 serial_0: serial@13800000 {
 511                         compatible = "samsung,exynos4210-uart";
 512                         reg = <0x13800000 0x100>;
 513                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 514                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 515                         clock-names = "uart", "clk_uart_baud0";
 516                         pinctrl-names = "default";
 517                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 518                         status = "disabled";
 519                 };
 520
 521                 serial_1: serial@13810000 {
 522                         compatible = "samsung,exynos4210-uart";
 523                         reg = <0x13810000 0x100>;
 524                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 526                         clock-names = "uart", "clk_uart_baud0";
 527                         pinctrl-names = "default";
 528                         pinctrl-0 = <&uart1_data>;
 529                         status = "disabled";
 530                 };
 531
 532                 serial_2: serial@13820000 {
 533                         compatible = "samsung,exynos4210-uart";
 534                         reg = <0x13820000 0x100>;
 535                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 536                         clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
 537                         clock-names = "uart", "clk_uart_baud0";
 538                         pinctrl-names = "default";
 539                         pinctrl-0 = <&uart2_data>;
 540                         status = "disabled";
 541                 };
 542
 543                 i2c_0: i2c@13860000 {
 544                         #address-cells = <1>;
 545                         #size-cells = <0>;
 546                         compatible = "samsung,s3c2440-i2c";
 547                         reg = <0x13860000 0x100>;
 548                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 549                         clocks = <&cmu CLK_I2C0>;
 550                         clock-names = "i2c";
 551                         pinctrl-names = "default";
 552                         pinctrl-0 = <&i2c0_bus>;
 553                         status = "disabled";
 554                 };
 555
 556                 i2c_1: i2c@13870000 {
 557                         #address-cells = <1>;
 558                         #size-cells = <0>;
 559                         compatible = "samsung,s3c2440-i2c";
 560                         reg = <0x13870000 0x100>;
 561                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&cmu CLK_I2C1>;
 563                         clock-names = "i2c";
 564                         pinctrl-names = "default";
 565                         pinctrl-0 = <&i2c1_bus>;
 566                         status = "disabled";
 567                 };
 568
 569                 i2c_2: i2c@13880000 {
 570                         #address-cells = <1>;
 571                         #size-cells = <0>;
 572                         compatible = "samsung,s3c2440-i2c";
 573                         reg = <0x13880000 0x100>;
 574                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 575                         clocks = <&cmu CLK_I2C2>;
 576                         clock-names = "i2c";
 577                         pinctrl-names = "default";
 578                         pinctrl-0 = <&i2c2_bus>;
 579                         status = "disabled";
 580                 };
 581
 582                 i2c_3: i2c@13890000 {
 583                         #address-cells = <1>;
 584                         #size-cells = <0>;
 585                         compatible = "samsung,s3c2440-i2c";
 586                         reg = <0x13890000 0x100>;
 587                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 588                         clocks = <&cmu CLK_I2C3>;
 589                         clock-names = "i2c";
 590                         pinctrl-names = "default";
 591                         pinctrl-0 = <&i2c3_bus>;
 592                         status = "disabled";
 593                 };
 594
 595                 i2c_4: i2c@138a0000 {
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                         compatible = "samsung,s3c2440-i2c";
 599                         reg = <0x138A0000 0x100>;
 600                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 601                         clocks = <&cmu CLK_I2C4>;
 602                         clock-names = "i2c";
 603                         pinctrl-names = "default";
 604                         pinctrl-0 = <&i2c4_bus>;
 605                         status = "disabled";
 606                 };
 607
 608                 i2c_5: i2c@138b0000 {
 609                         #address-cells = <1>;
 610                         #size-cells = <0>;
 611                         compatible = "samsung,s3c2440-i2c";
 612                         reg = <0x138B0000 0x100>;
 613                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 614                         clocks = <&cmu CLK_I2C5>;
 615                         clock-names = "i2c";
 616                         pinctrl-names = "default";
 617                         pinctrl-0 = <&i2c5_bus>;
 618                         status = "disabled";
 619                 };
 620
 621                 i2c_6: i2c@138c0000 {
 622                         #address-cells = <1>;
 623                         #size-cells = <0>;
 624                         compatible = "samsung,s3c2440-i2c";
 625                         reg = <0x138C0000 0x100>;
 626                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 627                         clocks = <&cmu CLK_I2C6>;
 628                         clock-names = "i2c";
 629                         pinctrl-names = "default";
 630                         pinctrl-0 = <&i2c6_bus>;
 631                         status = "disabled";
 632                 };
 633
 634                 i2c_7: i2c@138d0000 {
 635                         #address-cells = <1>;
 636                         #size-cells = <0>;
 637                         compatible = "samsung,s3c2440-i2c";
 638                         reg = <0x138D0000 0x100>;
 639                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 640                         clocks = <&cmu CLK_I2C7>;
 641                         clock-names = "i2c";
 642                         pinctrl-names = "default";
 643                         pinctrl-0 = <&i2c7_bus>;
 644                         status = "disabled";
 645                 };
 646
 647                 spi_0: spi@13920000 {
 648                         compatible = "samsung,exynos4210-spi";
 649                         reg = <0x13920000 0x100>;
 650                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 651                         dmas = <&pdma0 7>, <&pdma0 6>;
 652                         dma-names = "tx", "rx";
 653                         #address-cells = <1>;
 654                         #size-cells = <0>;
 655                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 656                         clock-names = "spi", "spi_busclk0";
 657                         samsung,spi-src-clk = <0>;
 658                         pinctrl-names = "default";
 659                         pinctrl-0 = <&spi0_bus>;
 660                         status = "disabled";
 661                 };
 662
 663                 spi_1: spi@13930000 {
 664                         compatible = "samsung,exynos4210-spi";
 665                         reg = <0x13930000 0x100>;
 666                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 667                         dmas = <&pdma1 7>, <&pdma1 6>;
 668                         dma-names = "tx", "rx";
 669                         #address-cells = <1>;
 670                         #size-cells = <0>;
 671                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 672                         clock-names = "spi", "spi_busclk0";
 673                         samsung,spi-src-clk = <0>;
 674                         pinctrl-names = "default";
 675                         pinctrl-0 = <&spi1_bus>;
 676                         status = "disabled";
 677                 };
 678
 679                 i2s2: i2s@13970000 {
 680                         compatible = "samsung,s3c6410-i2s";
 681                         reg = <0x13970000 0x100>;
 682                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 683                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 684                         clock-names = "iis", "i2s_opclk0";
 685                         dmas = <&pdma0 14>, <&pdma0 13>;
 686                         dma-names = "tx", "rx";
 687                         pinctrl-0 = <&i2s2_bus>;
 688                         pinctrl-names = "default";
 689                         status = "disabled";
 690                 };
 691
 692                 pwm: pwm@139d0000 {
 693                         compatible = "samsung,exynos4210-pwm";
 694                         reg = <0x139D0000 0x1000>;
 695                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 696                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 697                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 698                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 699                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 700                         #pwm-cells = <3>;
 701                         status = "disabled";
 702                 };
 703
 704                 ppmu_dmc0: ppmu@106a0000 {
 705                         compatible = "samsung,exynos-ppmu";
 706                         reg = <0x106a0000 0x2000>;
 707                         status = "disabled";
 708                 };
 709
 710                 ppmu_dmc1: ppmu@106b0000 {
 711                         compatible = "samsung,exynos-ppmu";
 712                         reg = <0x106b0000 0x2000>;
 713                         status = "disabled";
 714                 };
 715
 716                 ppmu_cpu: ppmu@106c0000 {
 717                         compatible = "samsung,exynos-ppmu";
 718                         reg = <0x106c0000 0x2000>;
 719                         status = "disabled";
 720                 };
 721
 722                 ppmu_rightbus: ppmu@112a0000 {
 723                         compatible = "samsung,exynos-ppmu";
 724                         reg = <0x112a0000 0x2000>;
 725                         clocks = <&cmu CLK_PPMURIGHT>;
 726                         clock-names = "ppmu";
 727                         status = "disabled";
 728                 };
 729
 730                 ppmu_leftbus: ppmu@116a0000 {
 731                         compatible = "samsung,exynos-ppmu";
 732                         reg = <0x116a0000 0x2000>;
 733                         clocks = <&cmu CLK_PPMULEFT>;
 734                         clock-names = "ppmu";
 735                         status = "disabled";
 736                 };
 737
 738                 ppmu_camif: ppmu@11ac0000 {
 739                         compatible = "samsung,exynos-ppmu";
 740                         reg = <0x11ac0000 0x2000>;
 741                         clocks = <&cmu CLK_PPMUCAMIF>;
 742                         clock-names = "ppmu";
 743                         status = "disabled";
 744                 };
 745
 746                 ppmu_lcd0: ppmu@11e40000 {
 747                         compatible = "samsung,exynos-ppmu";
 748                         reg = <0x11e40000 0x2000>;
 749                         clocks = <&cmu CLK_PPMULCD0>;
 750                         clock-names = "ppmu";
 751                         status = "disabled";
 752                 };
 753
 754                 ppmu_fsys: ppmu@12630000 {
 755                         compatible = "samsung,exynos-ppmu";
 756                         reg = <0x12630000 0x2000>;
 757                         clocks = <&cmu CLK_PPMUFILE>;
 758                         clock-names = "ppmu";
 759                         status = "disabled";
 760                 };
 761
 762                 ppmu_g3d: ppmu@13220000 {
 763                         compatible = "samsung,exynos-ppmu";
 764                         reg = <0x13220000 0x2000>;
 765                         clocks = <&cmu CLK_PPMUG3D>;
 766                         clock-names = "ppmu";
 767                         status = "disabled";
 768                 };
 769
 770                 ppmu_mfc: ppmu@13660000 {
 771                         compatible = "samsung,exynos-ppmu";
 772                         reg = <0x13660000 0x2000>;
 773                         clocks = <&cmu CLK_PPMUMFC_L>;
 774                         clock-names = "ppmu";
 775                         status = "disabled";
 776                 };
 777
 778                 bus_dmc: bus-dmc {
 779                         compatible = "samsung,exynos-bus";
 780                         clocks = <&cmu_dmc CLK_DIV_DMC>;
 781                         clock-names = "bus";
 782                         operating-points-v2 = <&bus_dmc_opp_table>;
 783                         status = "disabled";
 784                 };
 785
 786                 bus_dmc_opp_table: opp-table1 {
 787                         compatible = "operating-points-v2";
 788
 789                         opp-50000000 {
 790                                 opp-hz = /bits/ 64 <50000000>;
 791                                 opp-microvolt = <800000>;
 792                         };
 793                         opp-100000000 {
 794                                 opp-hz = /bits/ 64 <100000000>;
 795                                 opp-microvolt = <800000>;
 796                         };
 797                         opp-134000000 {
 798                                 opp-hz = /bits/ 64 <134000000>;
 799                                 opp-microvolt = <800000>;
 800                         };
 801                         opp-200000000 {
 802                                 opp-hz = /bits/ 64 <200000000>;
 803                                 opp-microvolt = <825000>;
 804                         };
 805                         opp-400000000 {
 806                                 opp-hz = /bits/ 64 <400000000>;
 807                                 opp-microvolt = <875000>;
 808                         };
 809                 };
 810
 811                 bus_leftbus: bus-leftbus {
 812                         compatible = "samsung,exynos-bus";
 813                         clocks = <&cmu CLK_DIV_GDL>;
 814                         clock-names = "bus";
 815                         operating-points-v2 = <&bus_leftbus_opp_table>;
 816                         status = "disabled";
 817                 };
 818
 819                 bus_rightbus: bus-rightbus {
 820                         compatible = "samsung,exynos-bus";
 821                         clocks = <&cmu CLK_DIV_GDR>;
 822                         clock-names = "bus";
 823                         operating-points-v2 = <&bus_leftbus_opp_table>;
 824                         status = "disabled";
 825                 };
 826
 827                 bus_lcd0: bus-lcd0 {
 828                         compatible = "samsung,exynos-bus";
 829                         clocks = <&cmu CLK_DIV_ACLK_160>;
 830                         clock-names = "bus";
 831                         operating-points-v2 = <&bus_leftbus_opp_table>;
 832                         status = "disabled";
 833                 };
 834
 835                 bus_fsys: bus-fsys {
 836                         compatible = "samsung,exynos-bus";
 837                         clocks = <&cmu CLK_DIV_ACLK_200>;
 838                         clock-names = "bus";
 839                         operating-points-v2 = <&bus_leftbus_opp_table>;
 840                         status = "disabled";
 841                 };
 842
 843                 bus_mcuisp: bus-mcuisp {
 844                         compatible = "samsung,exynos-bus";
 845                         clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
 846                         clock-names = "bus";
 847                         operating-points-v2 = <&bus_mcuisp_opp_table>;
 848                         status = "disabled";
 849                 };
 850
 851                 bus_isp: bus-isp {
 852                         compatible = "samsung,exynos-bus";
 853                         clocks = <&cmu CLK_DIV_ACLK_266>;
 854                         clock-names = "bus";
 855                         operating-points-v2 = <&bus_isp_opp_table>;
 856                         status = "disabled";
 857                 };
 858
 859                 bus_peril: bus-peril {
 860                         compatible = "samsung,exynos-bus";
 861                         clocks = <&cmu CLK_DIV_ACLK_100>;
 862                         clock-names = "bus";
 863                         operating-points-v2 = <&bus_peril_opp_table>;
 864                         status = "disabled";
 865                 };
 866
 867                 bus_mfc: bus-mfc {
 868                         compatible = "samsung,exynos-bus";
 869                         clocks = <&cmu CLK_SCLK_MFC>;
 870                         clock-names = "bus";
 871                         operating-points-v2 = <&bus_leftbus_opp_table>;
 872                         status = "disabled";
 873                 };
 874
 875                 bus_leftbus_opp_table: opp-table2 {
 876                         compatible = "operating-points-v2";
 877
 878                         opp-50000000 {
 879                                 opp-hz = /bits/ 64 <50000000>;
 880                                 opp-microvolt = <900000>;
 881                         };
 882                         opp-80000000 {
 883                                 opp-hz = /bits/ 64 <80000000>;
 884                                 opp-microvolt = <900000>;
 885                         };
 886                         opp-100000000 {
 887                                 opp-hz = /bits/ 64 <100000000>;
 888                                 opp-microvolt = <1000000>;
 889                         };
 890                         opp-134000000 {
 891                                 opp-hz = /bits/ 64 <134000000>;
 892                                 opp-microvolt = <1000000>;
 893                         };
 894                         opp-200000000 {
 895                                 opp-hz = /bits/ 64 <200000000>;
 896                                 opp-microvolt = <1000000>;
 897                         };
 898                 };
 899
 900                 bus_mcuisp_opp_table: opp-table3 {
 901                         compatible = "operating-points-v2";
 902
 903                         opp-50000000 {
 904                                 opp-hz = /bits/ 64 <50000000>;
 905                         };
 906                         opp-80000000 {
 907                                 opp-hz = /bits/ 64 <80000000>;
 908                         };
 909                         opp-100000000 {
 910                                 opp-hz = /bits/ 64 <100000000>;
 911                         };
 912                         opp-200000000 {
 913                                 opp-hz = /bits/ 64 <200000000>;
 914                         };
 915                         opp-400000000 {
 916                                 opp-hz = /bits/ 64 <400000000>;
 917                         };
 918                 };
 919
 920                 bus_isp_opp_table: opp-table4 {
 921                         compatible = "operating-points-v2";
 922
 923                         opp-50000000 {
 924                                 opp-hz = /bits/ 64 <50000000>;
 925                         };
 926                         opp-80000000 {
 927                                 opp-hz = /bits/ 64 <80000000>;
 928                         };
 929                         opp-100000000 {
 930                                 opp-hz = /bits/ 64 <100000000>;
 931                         };
 932                         opp-200000000 {
 933                                 opp-hz = /bits/ 64 <200000000>;
 934                         };
 935                         opp-300000000 {
 936                                 opp-hz = /bits/ 64 <300000000>;
 937                         };
 938                 };
 939
 940                 bus_peril_opp_table: opp-table5 {
 941                         compatible = "operating-points-v2";
 942
 943                         opp-50000000 {
 944                                 opp-hz = /bits/ 64 <50000000>;
 945                         };
 946                         opp-80000000 {
 947                                 opp-hz = /bits/ 64 <80000000>;
 948                         };
 949                         opp-100000000 {
 950                                 opp-hz = /bits/ 64 <100000000>;
 951                         };
 952                 };
 953         };
 954 };
 955
 956 #include "exynos3250-pinctrl.dtsi"
 957 #include "exynos-syscon-restart.dtsi"