arch/arm/boot/dts/bcm63138.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Broadcom BCM63138 DSL SoCs Device Tree
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         compatible = "brcm,bcm63138";
  13         model = "Broadcom BCM63138 DSL SoC";
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 uart0 = &serial0;
  18                 uart1 = &serial1;
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         next-level-cache = <&L2>;
  29                         reg = <0>;
  30                         enable-method = "brcm,bcm63138";
  31                 };
  32
  33                 cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a9";
  36                         next-level-cache = <&L2>;
  37                         reg = <1>;
  38                         enable-method = "brcm,bcm63138";
  39                         resets = <&pmb0 4 1>;
  40                 };
  41         };
  42
  43         clocks {
  44                 /* UBUS peripheral clock */
  45                 periph_clk: periph_clk {
  46                         #clock-cells = <0>;
  47                         compatible = "fixed-clock";
  48                         clock-frequency = <50000000>;
  49                         clock-output-names = "periph";
  50                 };
  51
  52                 /* peripheral clock for system timer */
  53                 axi_clk: axi_clk {
  54                         #clock-cells = <0>;
  55                         compatible = "fixed-factor-clock";
  56                         clocks = <&armpll>;
  57                         clock-div = <2>;
  58                         clock-mult = <1>;
  59                 };
  60
  61                 /* APB bus clock */
  62                 apb_clk: apb_clk {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-factor-clock";
  65                         clocks = <&armpll>;
  66                         clock-div = <4>;
  67                         clock-mult = <1>;
  68                 };
  69         };
  70
  71         /* ARM bus */
  72         axi@80000000 {
  73                 compatible = "simple-bus";
  74                 ranges = <0 0x80000000 0x784000>;
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77
  78                 L2: cache-controller@1d000 {
  79                         compatible = "arm,pl310-cache";
  80                         reg = <0x1d000 0x1000>;
  81                         cache-unified;
  82                         cache-level = <2>;
  83                         cache-size = <524288>;
  84                         cache-sets = <1024>;
  85                         cache-line-size = <32>;
  86                         interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
  87                 };
  88
  89                 scu: scu@1e000 {
  90                         compatible = "arm,cortex-a9-scu";
  91                         reg = <0x1e000 0x100>;
  92                 };
  93
  94                 gic: interrupt-controller@1f000 {
  95                         compatible = "arm,cortex-a9-gic";
  96                         reg = <0x1f000 0x1000
  97                                 0x1e100 0x100>;
  98                         #interrupt-cells = <3>;
  99                         #address-cells = <0>;
 100                         interrupt-controller;
 101                 };
 102
 103                 global_timer: timer@1e200 {
 104                         compatible = "arm,cortex-a9-global-timer";
 105                         reg = <0x1e200 0x20>;
 106                         interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
 107                         clocks = <&axi_clk>;
 108                 };
 109
 110                 local_timer: local-timer@1e600 {
 111                         compatible = "arm,cortex-a9-twd-timer";
 112                         reg = <0x1e600 0x20>;
 113                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 114                                                   IRQ_TYPE_EDGE_RISING)>;
 115                         clocks = <&axi_clk>;
 116                 };
 117
 118                 twd_watchdog: watchdog@1e620 {
 119                         compatible = "arm,cortex-a9-twd-wdt";
 120                         reg = <0x1e620 0x20>;
 121                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 122                                                   IRQ_TYPE_LEVEL_HIGH)>;
 123                 };
 124
 125                 armpll: armpll@20000 {
 126                         #clock-cells = <0>;
 127                         compatible = "brcm,bcm63138-armpll";
 128                         clocks = <&periph_clk>;
 129                         reg = <0x20000 0xf00>;
 130                 };
 131
 132                 pmb0: reset-controller@4800c0 {
 133                         compatible = "brcm,bcm63138-pmb";
 134                         reg = <0x4800c0 0x10>;
 135                         #reset-cells = <2>;
 136                 };
 137
 138                 pmb1: reset-controller@4800e0 {
 139                         compatible = "brcm,bcm63138-pmb";
 140                         reg = <0x4800e0 0x10>;
 141                         #reset-cells = <2>;
 142                 };
 143
 144                 ahci: sata@a000 {
 145                         compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
 146                         reg-names = "ahci", "top-ctrl";
 147                         reg = <0xa000 0x9ac>, <0x8040 0x24>;
 148                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         resets = <&pmb0 3 1>;
 152                         reset-names = "ahci";
 153                         status = "disabled";
 154
 155                         sata0: sata-port@0 {
 156                                 reg = <0>;
 157                                 phys = <&sata_phy0>;
 158                         };
 159                 };
 160
 161                 sata_phy: sata-phy@8100 {
 162                         compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
 163                         reg = <0x8100 0x1e00>;
 164                         reg-names = "phy";
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         status = "disabled";
 168
 169                         sata_phy0: sata-phy@0 {
 170                                 reg = <0>;
 171                                 #phy-cells = <0>;
 172                         };
 173                 };
 174         };
 175
 176         /* Legacy UBUS base */
 177         ubus@fffe8000 {
 178                 compatible = "simple-bus";
 179                 #address-cells = <1>;
 180                 #size-cells = <1>;
 181                 ranges = <0 0xfffe8000 0x8100>;
 182
 183                 timer: timer@80 {
 184                         compatible = "brcm,bcm6328-timer", "syscon";
 185                         reg = <0x80 0x3c>;
 186                 };
 187
 188                 serial0: serial@600 {
 189                         compatible = "brcm,bcm6345-uart";
 190                         reg = <0x600 0x1b>;
 191                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 192                         clocks = <&periph_clk>;
 193                         clock-names = "periph";
 194                         status = "disabled";
 195                 };
 196
 197                 serial1: serial@620 {
 198                         compatible = "brcm,bcm6345-uart";
 199                         reg = <0x620 0x1b>;
 200                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 201                         clocks = <&periph_clk>;
 202                         clock-names = "periph";
 203                         status = "disabled";
 204                 };
 205
 206                 nand_controller: nand-controller@2000 {
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
 210                         reg = <0x2000 0x600>, <0xf0 0x10>;
 211                         reg-names = "nand", "nand-int-base";
 212                         status = "disabled";
 213                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 214                         interrupt-names = "nand";
 215                 };
 216
 217                 bootlut: bootlut@8000 {
 218                         compatible = "brcm,bcm63138-bootlut";
 219                         reg = <0x8000 0x50>;
 220                 };
 221
 222                 reboot {
 223                         compatible = "syscon-reboot";
 224                         regmap = <&timer>;
 225                         offset = <0x34>;
 226                         mask = <1>;
 227                 };
 228         };
 229 };