arch/arm/boot/dts/aspeed-g5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <dt-bindings/clock/aspeed-clock.h>
   3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
   4
   5 / {
   6         model = "Aspeed BMC";
   7         compatible = "aspeed,ast2500";
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10         interrupt-parent = <&vic>;
  11
  12         aliases {
  13                 i2c0 = &i2c0;
  14                 i2c1 = &i2c1;
  15                 i2c2 = &i2c2;
  16                 i2c3 = &i2c3;
  17                 i2c4 = &i2c4;
  18                 i2c5 = &i2c5;
  19                 i2c6 = &i2c6;
  20                 i2c7 = &i2c7;
  21                 i2c8 = &i2c8;
  22                 i2c9 = &i2c9;
  23                 i2c10 = &i2c10;
  24                 i2c11 = &i2c11;
  25                 i2c12 = &i2c12;
  26                 i2c13 = &i2c13;
  27                 serial0 = &uart1;
  28                 serial1 = &uart2;
  29                 serial2 = &uart3;
  30                 serial3 = &uart4;
  31                 serial4 = &uart5;
  32                 serial5 = &vuart;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu@0 {
  40                         compatible = "arm,arm1176jzf-s";
  41                         device_type = "cpu";
  42                         reg = <0>;
  43                 };
  44         };
  45
  46         memory@80000000 {
  47                 device_type = "memory";
  48                 reg = <0x80000000 0>;
  49         };
  50
  51         ahb {
  52                 compatible = "simple-bus";
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 ranges;
  56
  57                 fmc: spi@1e620000 {
  58                         reg = < 0x1e620000 0xc4
  59                                 0x20000000 0x10000000 >;
  60                         #address-cells = <1>;
  61                         #size-cells = <0>;
  62                         compatible = "aspeed,ast2500-fmc";
  63                         clocks = <&syscon ASPEED_CLK_AHB>;
  64                         status = "disabled";
  65                         interrupts = <19>;
  66                         flash@0 {
  67                                 reg = < 0 >;
  68                                 compatible = "jedec,spi-nor";
  69                                 spi-max-frequency = <50000000>;
  70                                 status = "disabled";
  71                         };
  72                         flash@1 {
  73                                 reg = < 1 >;
  74                                 compatible = "jedec,spi-nor";
  75                                 spi-max-frequency = <50000000>;
  76                                 status = "disabled";
  77                         };
  78                         flash@2 {
  79                                 reg = < 2 >;
  80                                 compatible = "jedec,spi-nor";
  81                                 spi-max-frequency = <50000000>;
  82                                 status = "disabled";
  83                         };
  84                 };
  85
  86                 spi1: spi@1e630000 {
  87                         reg = < 0x1e630000 0xc4
  88                                 0x30000000 0x08000000 >;
  89                         #address-cells = <1>;
  90                         #size-cells = <0>;
  91                         compatible = "aspeed,ast2500-spi";
  92                         clocks = <&syscon ASPEED_CLK_AHB>;
  93                         status = "disabled";
  94                         flash@0 {
  95                                 reg = < 0 >;
  96                                 compatible = "jedec,spi-nor";
  97                                 spi-max-frequency = <50000000>;
  98                                 status = "disabled";
  99                         };
 100                         flash@1 {
 101                                 reg = < 1 >;
 102                                 compatible = "jedec,spi-nor";
 103                                 spi-max-frequency = <50000000>;
 104                                 status = "disabled";
 105                         };
 106                 };
 107
 108                 spi2: spi@1e631000 {
 109                         reg = < 0x1e631000 0xc4
 110                                 0x38000000 0x08000000 >;
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         compatible = "aspeed,ast2500-spi";
 114                         clocks = <&syscon ASPEED_CLK_AHB>;
 115                         status = "disabled";
 116                         flash@0 {
 117                                 reg = < 0 >;
 118                                 compatible = "jedec,spi-nor";
 119                                 spi-max-frequency = <50000000>;
 120                                 status = "disabled";
 121                         };
 122                         flash@1 {
 123                                 reg = < 1 >;
 124                                 compatible = "jedec,spi-nor";
 125                                 spi-max-frequency = <50000000>;
 126                                 status = "disabled";
 127                         };
 128                 };
 129
 130                 vic: interrupt-controller@1e6c0080 {
 131                         compatible = "aspeed,ast2400-vic";
 132                         interrupt-controller;
 133                         #interrupt-cells = <1>;
 134                         valid-sources = <0xfefff7ff 0x0807ffff>;
 135                         reg = <0x1e6c0080 0x80>;
 136                 };
 137
 138                 cvic: copro-interrupt-controller@1e6c2000 {
 139                         compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
 140                         valid-sources = <0xffffffff>;
 141                         copro-sw-interrupts = <1>;
 142                         reg = <0x1e6c2000 0x80>;
 143                 };
 144
 145                 mac0: ethernet@1e660000 {
 146                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
 147                         reg = <0x1e660000 0x180>;
 148                         interrupts = <2>;
 149                         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
 150                         status = "disabled";
 151                 };
 152
 153                 mac1: ethernet@1e680000 {
 154                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
 155                         reg = <0x1e680000 0x180>;
 156                         interrupts = <3>;
 157                         clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
 158                         status = "disabled";
 159                 };
 160
 161                 ehci0: usb@1e6a1000 {
 162                         compatible = "aspeed,ast2500-ehci", "generic-ehci";
 163                         reg = <0x1e6a1000 0x100>;
 164                         interrupts = <5>;
 165                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 166                         pinctrl-names = "default";
 167                         pinctrl-0 = <&pinctrl_usb2ah_default>;
 168                         status = "disabled";
 169                 };
 170
 171                 ehci1: usb@1e6a3000 {
 172                         compatible = "aspeed,ast2500-ehci", "generic-ehci";
 173                         reg = <0x1e6a3000 0x100>;
 174                         interrupts = <13>;
 175                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
 176                         pinctrl-names = "default";
 177                         pinctrl-0 = <&pinctrl_usb2bh_default>;
 178                         status = "disabled";
 179                 };
 180
 181                 uhci: usb@1e6b0000 {
 182                         compatible = "aspeed,ast2500-uhci", "generic-uhci";
 183                         reg = <0x1e6b0000 0x100>;
 184                         interrupts = <14>;
 185                         #ports = <2>;
 186                         clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
 187                         status = "disabled";
 188                         /*
 189                          * No default pinmux, it will follow EHCI, use an explicit pinmux
 190                          * override if you don't enable EHCI
 191                          */
 192                 };
 193
 194                 vhub: usb-vhub@1e6a0000 {
 195                         compatible = "aspeed,ast2500-usb-vhub";
 196                         reg = <0x1e6a0000 0x300>;
 197                         interrupts = <5>;
 198                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 199                         aspeed,vhub-downstream-ports = <5>;
 200                         aspeed,vhub-generic-endpoints = <15>;
 201                         pinctrl-names = "default";
 202                         pinctrl-0 = <&pinctrl_usb2ad_default>;
 203                         status = "disabled";
 204                 };
 205
 206                 apb {
 207                         compatible = "simple-bus";
 208                         #address-cells = <1>;
 209                         #size-cells = <1>;
 210                         ranges;
 211
 212                         edac: memory-controller@1e6e0000 {
 213                                 compatible = "aspeed,ast2500-sdram-edac";
 214                                 reg = <0x1e6e0000 0x174>;
 215                                 interrupts = <0>;
 216                                 status = "disabled";
 217                         };
 218
 219                         syscon: syscon@1e6e2000 {
 220                                 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
 221                                 reg = <0x1e6e2000 0x1a8>;
 222                                 #address-cells = <1>;
 223                                 #size-cells = <1>;
 224                                 ranges = <0 0x1e6e2000 0x1000>;
 225                                 #clock-cells = <1>;
 226                                 #reset-cells = <1>;
 227
 228                                 scu_ic: interrupt-controller@18 {
 229                                         #interrupt-cells = <1>;
 230                                         compatible = "aspeed,ast2500-scu-ic";
 231                                         reg = <0x18 0x4>;
 232                                         interrupts = <21>;
 233                                         interrupt-controller;
 234                                 };
 235
 236                                 p2a: p2a-control@2c {
 237                                         compatible = "aspeed,ast2500-p2a-ctrl";
 238                                         reg = <0x2c 0x4>;
 239                                         status = "disabled";
 240                                 };
 241
 242                                 silicon-id@7c {
 243                                         compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
 244                                         reg = <0x7c 0x4 0x150 0x8>;
 245                                 };
 246
 247                                 pinctrl: pinctrl@80 {
 248                                         compatible = "aspeed,ast2500-pinctrl";
 249                                         reg = <0x80 0x18>, <0xa0 0x10>;
 250                                         aspeed,external-nodes = <&gfx>, <&lhc>;
 251                                 };
 252                         };
 253
 254                         rng: hwrng@1e6e2078 {
 255                                 compatible = "timeriomem_rng";
 256                                 reg = <0x1e6e2078 0x4>;
 257                                 period = <1>;
 258                                 quality = <100>;
 259                         };
 260
 261                         gfx: display@1e6e6000 {
 262                                 compatible = "aspeed,ast2500-gfx", "syscon";
 263                                 reg = <0x1e6e6000 0x1000>;
 264                                 reg-io-width = <4>;
 265                                 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
 266                                 resets = <&syscon ASPEED_RESET_CRT1>;
 267                                 status = "disabled";
 268                                 interrupts = <0x19>;
 269                         };
 270
 271                         xdma: xdma@1e6e7000 {
 272                                 compatible = "aspeed,ast2500-xdma";
 273                                 reg = <0x1e6e7000 0x100>;
 274                                 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
 275                                 resets = <&syscon ASPEED_RESET_XDMA>;
 276                                 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
 277                                 aspeed,pcie-device = "bmc";
 278                                 aspeed,scu = <&syscon>;
 279                                 status = "disabled";
 280                         };
 281
 282                         adc: adc@1e6e9000 {
 283                                 compatible = "aspeed,ast2500-adc";
 284                                 reg = <0x1e6e9000 0xb0>;
 285                                 clocks = <&syscon ASPEED_CLK_APB>;
 286                                 resets = <&syscon ASPEED_RESET_ADC>;
 287                                 #io-channel-cells = <1>;
 288                                 status = "disabled";
 289                         };
 290
 291                         video: video@1e700000 {
 292                                 compatible = "aspeed,ast2500-video-engine";
 293                                 reg = <0x1e700000 0x1000>;
 294                                 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
 295                                          <&syscon ASPEED_CLK_GATE_ECLK>;
 296                                 clock-names = "vclk", "eclk";
 297                                 interrupts = <7>;
 298                                 status = "disabled";
 299                         };
 300
 301                         sram: sram@1e720000 {
 302                                 compatible = "mmio-sram";
 303                                 reg = <0x1e720000 0x9000>;      // 36K
 304                         };
 305
 306                         sdmmc: sd-controller@1e740000 {
 307                                 compatible = "aspeed,ast2500-sd-controller";
 308                                 reg = <0x1e740000 0x100>;
 309                                 #address-cells = <1>;
 310                                 #size-cells = <1>;
 311                                 ranges = <0 0x1e740000 0x10000>;
 312                                 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
 313                                 status = "disabled";
 314
 315                                 sdhci0: sdhci@100 {
 316                                         compatible = "aspeed,ast2500-sdhci";
 317                                         reg = <0x100 0x100>;
 318                                         interrupts = <26>;
 319                                         sdhci,auto-cmd12;
 320                                         clocks = <&syscon ASPEED_CLK_SDIO>;
 321                                         status = "disabled";
 322                                 };
 323
 324                                 sdhci1: sdhci@200 {
 325                                         compatible = "aspeed,ast2500-sdhci";
 326                                         reg = <0x200 0x100>;
 327                                         interrupts = <26>;
 328                                         sdhci,auto-cmd12;
 329                                         clocks = <&syscon ASPEED_CLK_SDIO>;
 330                                         status = "disabled";
 331                                 };
 332                         };
 333
 334                         gpio: gpio@1e780000 {
 335                                 #gpio-cells = <2>;
 336                                 gpio-controller;
 337                                 compatible = "aspeed,ast2500-gpio";
 338                                 reg = <0x1e780000 0x200>;
 339                                 interrupts = <20>;
 340                                 gpio-ranges = <&pinctrl 0 0 232>;
 341                                 clocks = <&syscon ASPEED_CLK_APB>;
 342                                 interrupt-controller;
 343                                 #interrupt-cells = <2>;
 344                         };
 345
 346                         sgpio: sgpio@1e780200 {
 347                                 #gpio-cells = <2>;
 348                                 compatible = "aspeed,ast2500-sgpio";
 349                                 gpio-controller;
 350                                 interrupts = <40>;
 351                                 reg = <0x1e780200 0x0100>;
 352                                 clocks = <&syscon ASPEED_CLK_APB>;
 353                                 interrupt-controller;
 354                                 ngpios = <8>;
 355                                 bus-frequency = <12000000>;
 356                                 pinctrl-names = "default";
 357                                 pinctrl-0 = <&pinctrl_sgpm_default>;
 358                                 status = "disabled";
 359                         };
 360
 361                         rtc: rtc@1e781000 {
 362                                 compatible = "aspeed,ast2500-rtc";
 363                                 reg = <0x1e781000 0x18>;
 364                                 status = "disabled";
 365                         };
 366
 367                         timer: timer@1e782000 {
 368                                 /* This timer is a Faraday FTTMR010 derivative */
 369                                 compatible = "aspeed,ast2400-timer";
 370                                 reg = <0x1e782000 0x90>;
 371                                 interrupts = <16 17 18 35 36 37 38 39>;
 372                                 clocks = <&syscon ASPEED_CLK_APB>;
 373                                 clock-names = "PCLK";
 374                         };
 375
 376                         uart1: serial@1e783000 {
 377                                 compatible = "ns16550a";
 378                                 reg = <0x1e783000 0x20>;
 379                                 reg-shift = <2>;
 380                                 interrupts = <9>;
 381                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
 382                                 resets = <&lpc_reset 4>;
 383                                 no-loopback-test;
 384                                 status = "disabled";
 385                         };
 386
 387                         uart5: serial@1e784000 {
 388                                 compatible = "ns16550a";
 389                                 reg = <0x1e784000 0x20>;
 390                                 reg-shift = <2>;
 391                                 interrupts = <10>;
 392                                 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
 393                                 no-loopback-test;
 394                                 status = "disabled";
 395                         };
 396
 397                         wdt1: watchdog@1e785000 {
 398                                 compatible = "aspeed,ast2500-wdt";
 399                                 reg = <0x1e785000 0x20>;
 400                                 clocks = <&syscon ASPEED_CLK_APB>;
 401                         };
 402
 403                         wdt2: watchdog@1e785020 {
 404                                 compatible = "aspeed,ast2500-wdt";
 405                                 reg = <0x1e785020 0x20>;
 406                                 clocks = <&syscon ASPEED_CLK_APB>;
 407                         };
 408
 409                         wdt3: watchdog@1e785040 {
 410                                 compatible = "aspeed,ast2500-wdt";
 411                                 reg = <0x1e785040 0x20>;
 412                                 clocks = <&syscon ASPEED_CLK_APB>;
 413                                 status = "disabled";
 414                         };
 415
 416                         pwm_tacho: pwm-tacho-controller@1e786000 {
 417                                 compatible = "aspeed,ast2500-pwm-tacho";
 418                                 #address-cells = <1>;
 419                                 #size-cells = <0>;
 420                                 reg = <0x1e786000 0x1000>;
 421                                 clocks = <&syscon ASPEED_CLK_24M>;
 422                                 resets = <&syscon ASPEED_RESET_PWM>;
 423                                 status = "disabled";
 424                         };
 425
 426                         vuart: serial@1e787000 {
 427                                 compatible = "aspeed,ast2500-vuart";
 428                                 reg = <0x1e787000 0x40>;
 429                                 reg-shift = <2>;
 430                                 interrupts = <8>;
 431                                 clocks = <&syscon ASPEED_CLK_APB>;
 432                                 no-loopback-test;
 433                                 status = "disabled";
 434                         };
 435
 436                         lpc: lpc@1e789000 {
 437                                 compatible = "aspeed,ast2500-lpc", "simple-mfd";
 438                                 reg = <0x1e789000 0x1000>;
 439
 440                                 #address-cells = <1>;
 441                                 #size-cells = <1>;
 442                                 ranges = <0x0 0x1e789000 0x1000>;
 443
 444                                 lpc_bmc: lpc-bmc@0 {
 445                                         compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
 446                                         reg = <0x0 0x80>;
 447                                         reg-io-width = <4>;
 448
 449                                         #address-cells = <1>;
 450                                         #size-cells = <1>;
 451                                         ranges = <0x0 0x0 0x80>;
 452
 453                                         kcs1: kcs@24 {
 454                                                 compatible = "aspeed,ast2500-kcs-bmc-v2";
 455                                                 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
 456                                                 interrupts = <8>;
 457                                                 status = "disabled";
 458                                         };
 459                                         kcs2: kcs@28 {
 460                                                 compatible = "aspeed,ast2500-kcs-bmc-v2";
 461                                                 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
 462                                                 interrupts = <8>;
 463                                                 status = "disabled";
 464                                         };
 465                                         kcs3: kcs@2c {
 466                                                 compatible = "aspeed,ast2500-kcs-bmc-v2";
 467                                                 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
 468                                                 interrupts = <8>;
 469                                                 status = "disabled";
 470                                         };
 471                                 };
 472
 473                                 lpc_host: lpc-host@80 {
 474                                         compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
 475                                         reg = <0x80 0x1e0>;
 476                                         reg-io-width = <4>;
 477
 478                                         #address-cells = <1>;
 479                                         #size-cells = <1>;
 480                                         ranges = <0x0 0x80 0x1e0>;
 481
 482                                         kcs4: kcs@94 {
 483                                                 compatible = "aspeed,ast2500-kcs-bmc-v2";
 484                                                 reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>;
 485                                                 interrupts = <8>;
 486                                                 status = "disabled";
 487                                         };
 488
 489                                         lpc_ctrl: lpc-ctrl@0 {
 490                                                 compatible = "aspeed,ast2500-lpc-ctrl";
 491                                                 reg = <0x0 0x10>;
 492                                                 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
 493                                                 status = "disabled";
 494                                         };
 495
 496                                         lpc_snoop: lpc-snoop@10 {
 497                                                 compatible = "aspeed,ast2500-lpc-snoop";
 498                                                 reg = <0x10 0x8>;
 499                                                 interrupts = <8>;
 500                                                 status = "disabled";
 501                                         };
 502
 503                                         lpc_reset: reset-controller@18 {
 504                                                 compatible = "aspeed,ast2500-lpc-reset";
 505                                                 reg = <0x18 0x4>;
 506                                                 #reset-cells = <1>;
 507                                         };
 508
 509                                         lhc: lhc@20 {
 510                                                 compatible = "aspeed,ast2500-lhc";
 511                                                 reg = <0x20 0x24 0x48 0x8>;
 512                                         };
 513
 514
 515                                         ibt: ibt@c0 {
 516                                                 compatible = "aspeed,ast2500-ibt-bmc";
 517                                                 reg = <0xc0 0x18>;
 518                                                 interrupts = <8>;
 519                                                 status = "disabled";
 520                                         };
 521                                 };
 522                         };
 523
 524                         uart2: serial@1e78d000 {
 525                                 compatible = "ns16550a";
 526                                 reg = <0x1e78d000 0x20>;
 527                                 reg-shift = <2>;
 528                                 interrupts = <32>;
 529                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
 530                                 resets = <&lpc_reset 5>;
 531                                 no-loopback-test;
 532                                 status = "disabled";
 533                         };
 534
 535                         uart3: serial@1e78e000 {
 536                                 compatible = "ns16550a";
 537                                 reg = <0x1e78e000 0x20>;
 538                                 reg-shift = <2>;
 539                                 interrupts = <33>;
 540                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
 541                                 resets = <&lpc_reset 6>;
 542                                 no-loopback-test;
 543                                 status = "disabled";
 544                         };
 545
 546                         uart4: serial@1e78f000 {
 547                                 compatible = "ns16550a";
 548                                 reg = <0x1e78f000 0x20>;
 549                                 reg-shift = <2>;
 550                                 interrupts = <34>;
 551                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
 552                                 resets = <&lpc_reset 7>;
 553                                 no-loopback-test;
 554                                 status = "disabled";
 555                         };
 556
 557                         i2c: bus@1e78a000 {
 558                                 compatible = "simple-bus";
 559                                 #address-cells = <1>;
 560                                 #size-cells = <1>;
 561                                 ranges = <0 0x1e78a000 0x1000>;
 562                         };
 563                 };
 564         };
 565 };
 566
 567 &i2c {
 568         i2c_ic: interrupt-controller@0 {
 569                 #interrupt-cells = <1>;
 570                 compatible = "aspeed,ast2500-i2c-ic";
 571                 reg = <0x0 0x40>;
 572                 interrupts = <12>;
 573                 interrupt-controller;
 574         };
 575
 576         i2c0: i2c-bus@40 {
 577                 #address-cells = <1>;
 578                 #size-cells = <0>;
 579                 #interrupt-cells = <1>;
 580
 581                 reg = <0x40 0x40>;
 582                 compatible = "aspeed,ast2500-i2c-bus";
 583                 clocks = <&syscon ASPEED_CLK_APB>;
 584                 resets = <&syscon ASPEED_RESET_I2C>;
 585                 bus-frequency = <100000>;
 586                 interrupts = <0>;
 587                 interrupt-parent = <&i2c_ic>;
 588                 status = "disabled";
 589                 /* Does not need pinctrl properties */
 590         };
 591
 592         i2c1: i2c-bus@80 {
 593                 #address-cells = <1>;
 594                 #size-cells = <0>;
 595                 #interrupt-cells = <1>;
 596
 597                 reg = <0x80 0x40>;
 598                 compatible = "aspeed,ast2500-i2c-bus";
 599                 clocks = <&syscon ASPEED_CLK_APB>;
 600                 resets = <&syscon ASPEED_RESET_I2C>;
 601                 bus-frequency = <100000>;
 602                 interrupts = <1>;
 603                 interrupt-parent = <&i2c_ic>;
 604                 status = "disabled";
 605                 /* Does not need pinctrl properties */
 606         };
 607
 608         i2c2: i2c-bus@c0 {
 609                 #address-cells = <1>;
 610                 #size-cells = <0>;
 611                 #interrupt-cells = <1>;
 612
 613                 reg = <0xc0 0x40>;
 614                 compatible = "aspeed,ast2500-i2c-bus";
 615                 clocks = <&syscon ASPEED_CLK_APB>;
 616                 resets = <&syscon ASPEED_RESET_I2C>;
 617                 bus-frequency = <100000>;
 618                 interrupts = <2>;
 619                 interrupt-parent = <&i2c_ic>;
 620                 pinctrl-names = "default";
 621                 pinctrl-0 = <&pinctrl_i2c3_default>;
 622                 status = "disabled";
 623         };
 624
 625         i2c3: i2c-bus@100 {
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 #interrupt-cells = <1>;
 629
 630                 reg = <0x100 0x40>;
 631                 compatible = "aspeed,ast2500-i2c-bus";
 632                 clocks = <&syscon ASPEED_CLK_APB>;
 633                 resets = <&syscon ASPEED_RESET_I2C>;
 634                 bus-frequency = <100000>;
 635                 interrupts = <3>;
 636                 interrupt-parent = <&i2c_ic>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&pinctrl_i2c4_default>;
 639                 status = "disabled";
 640         };
 641
 642         i2c4: i2c-bus@140 {
 643                 #address-cells = <1>;
 644                 #size-cells = <0>;
 645                 #interrupt-cells = <1>;
 646
 647                 reg = <0x140 0x40>;
 648                 compatible = "aspeed,ast2500-i2c-bus";
 649                 clocks = <&syscon ASPEED_CLK_APB>;
 650                 resets = <&syscon ASPEED_RESET_I2C>;
 651                 bus-frequency = <100000>;
 652                 interrupts = <4>;
 653                 interrupt-parent = <&i2c_ic>;
 654                 pinctrl-names = "default";
 655                 pinctrl-0 = <&pinctrl_i2c5_default>;
 656                 status = "disabled";
 657         };
 658
 659         i2c5: i2c-bus@180 {
 660                 #address-cells = <1>;
 661                 #size-cells = <0>;
 662                 #interrupt-cells = <1>;
 663
 664                 reg = <0x180 0x40>;
 665                 compatible = "aspeed,ast2500-i2c-bus";
 666                 clocks = <&syscon ASPEED_CLK_APB>;
 667                 resets = <&syscon ASPEED_RESET_I2C>;
 668                 bus-frequency = <100000>;
 669                 interrupts = <5>;
 670                 interrupt-parent = <&i2c_ic>;
 671                 pinctrl-names = "default";
 672                 pinctrl-0 = <&pinctrl_i2c6_default>;
 673                 status = "disabled";
 674         };
 675
 676         i2c6: i2c-bus@1c0 {
 677                 #address-cells = <1>;
 678                 #size-cells = <0>;
 679                 #interrupt-cells = <1>;
 680
 681                 reg = <0x1c0 0x40>;
 682                 compatible = "aspeed,ast2500-i2c-bus";
 683                 clocks = <&syscon ASPEED_CLK_APB>;
 684                 resets = <&syscon ASPEED_RESET_I2C>;
 685                 bus-frequency = <100000>;
 686                 interrupts = <6>;
 687                 interrupt-parent = <&i2c_ic>;
 688                 pinctrl-names = "default";
 689                 pinctrl-0 = <&pinctrl_i2c7_default>;
 690                 status = "disabled";
 691         };
 692
 693         i2c7: i2c-bus@300 {
 694                 #address-cells = <1>;
 695                 #size-cells = <0>;
 696                 #interrupt-cells = <1>;
 697
 698                 reg = <0x300 0x40>;
 699                 compatible = "aspeed,ast2500-i2c-bus";
 700                 clocks = <&syscon ASPEED_CLK_APB>;
 701                 resets = <&syscon ASPEED_RESET_I2C>;
 702                 bus-frequency = <100000>;
 703                 interrupts = <7>;
 704                 interrupt-parent = <&i2c_ic>;
 705                 pinctrl-names = "default";
 706                 pinctrl-0 = <&pinctrl_i2c8_default>;
 707                 status = "disabled";
 708         };
 709
 710         i2c8: i2c-bus@340 {
 711                 #address-cells = <1>;
 712                 #size-cells = <0>;
 713                 #interrupt-cells = <1>;
 714
 715                 reg = <0x340 0x40>;
 716                 compatible = "aspeed,ast2500-i2c-bus";
 717                 clocks = <&syscon ASPEED_CLK_APB>;
 718                 resets = <&syscon ASPEED_RESET_I2C>;
 719                 bus-frequency = <100000>;
 720                 interrupts = <8>;
 721                 interrupt-parent = <&i2c_ic>;
 722                 pinctrl-names = "default";
 723                 pinctrl-0 = <&pinctrl_i2c9_default>;
 724                 status = "disabled";
 725         };
 726
 727         i2c9: i2c-bus@380 {
 728                 #address-cells = <1>;
 729                 #size-cells = <0>;
 730                 #interrupt-cells = <1>;
 731
 732                 reg = <0x380 0x40>;
 733                 compatible = "aspeed,ast2500-i2c-bus";
 734                 clocks = <&syscon ASPEED_CLK_APB>;
 735                 resets = <&syscon ASPEED_RESET_I2C>;
 736                 bus-frequency = <100000>;
 737                 interrupts = <9>;
 738                 interrupt-parent = <&i2c_ic>;
 739                 pinctrl-names = "default";
 740                 pinctrl-0 = <&pinctrl_i2c10_default>;
 741                 status = "disabled";
 742         };
 743
 744         i2c10: i2c-bus@3c0 {
 745                 #address-cells = <1>;
 746                 #size-cells = <0>;
 747                 #interrupt-cells = <1>;
 748
 749                 reg = <0x3c0 0x40>;
 750                 compatible = "aspeed,ast2500-i2c-bus";
 751                 clocks = <&syscon ASPEED_CLK_APB>;
 752                 resets = <&syscon ASPEED_RESET_I2C>;
 753                 bus-frequency = <100000>;
 754                 interrupts = <10>;
 755                 interrupt-parent = <&i2c_ic>;
 756                 pinctrl-names = "default";
 757                 pinctrl-0 = <&pinctrl_i2c11_default>;
 758                 status = "disabled";
 759         };
 760
 761         i2c11: i2c-bus@400 {
 762                 #address-cells = <1>;
 763                 #size-cells = <0>;
 764                 #interrupt-cells = <1>;
 765
 766                 reg = <0x400 0x40>;
 767                 compatible = "aspeed,ast2500-i2c-bus";
 768                 clocks = <&syscon ASPEED_CLK_APB>;
 769                 resets = <&syscon ASPEED_RESET_I2C>;
 770                 bus-frequency = <100000>;
 771                 interrupts = <11>;
 772                 interrupt-parent = <&i2c_ic>;
 773                 pinctrl-names = "default";
 774                 pinctrl-0 = <&pinctrl_i2c12_default>;
 775                 status = "disabled";
 776         };
 777
 778         i2c12: i2c-bus@440 {
 779                 #address-cells = <1>;
 780                 #size-cells = <0>;
 781                 #interrupt-cells = <1>;
 782
 783                 reg = <0x440 0x40>;
 784                 compatible = "aspeed,ast2500-i2c-bus";
 785                 clocks = <&syscon ASPEED_CLK_APB>;
 786                 resets = <&syscon ASPEED_RESET_I2C>;
 787                 bus-frequency = <100000>;
 788                 interrupts = <12>;
 789                 interrupt-parent = <&i2c_ic>;
 790                 pinctrl-names = "default";
 791                 pinctrl-0 = <&pinctrl_i2c13_default>;
 792                 status = "disabled";
 793         };
 794
 795         i2c13: i2c-bus@480 {
 796                 #address-cells = <1>;
 797                 #size-cells = <0>;
 798                 #interrupt-cells = <1>;
 799
 800                 reg = <0x480 0x40>;
 801                 compatible = "aspeed,ast2500-i2c-bus";
 802                 clocks = <&syscon ASPEED_CLK_APB>;
 803                 resets = <&syscon ASPEED_RESET_I2C>;
 804                 bus-frequency = <100000>;
 805                 interrupts = <13>;
 806                 interrupt-parent = <&i2c_ic>;
 807                 pinctrl-names = "default";
 808                 pinctrl-0 = <&pinctrl_i2c14_default>;
 809                 status = "disabled";
 810         };
 811 };
 812
 813 &pinctrl {
 814         pinctrl_acpi_default: acpi_default {
 815                 function = "ACPI";
 816                 groups = "ACPI";
 817         };
 818
 819         pinctrl_adc0_default: adc0_default {
 820                 function = "ADC0";
 821                 groups = "ADC0";
 822         };
 823
 824         pinctrl_adc1_default: adc1_default {
 825                 function = "ADC1";
 826                 groups = "ADC1";
 827         };
 828
 829         pinctrl_adc10_default: adc10_default {
 830                 function = "ADC10";
 831                 groups = "ADC10";
 832         };
 833
 834         pinctrl_adc11_default: adc11_default {
 835                 function = "ADC11";
 836                 groups = "ADC11";
 837         };
 838
 839         pinctrl_adc12_default: adc12_default {
 840                 function = "ADC12";
 841                 groups = "ADC12";
 842         };
 843
 844         pinctrl_adc13_default: adc13_default {
 845                 function = "ADC13";
 846                 groups = "ADC13";
 847         };
 848
 849         pinctrl_adc14_default: adc14_default {
 850                 function = "ADC14";
 851                 groups = "ADC14";
 852         };
 853
 854         pinctrl_adc15_default: adc15_default {
 855                 function = "ADC15";
 856                 groups = "ADC15";
 857         };
 858
 859         pinctrl_adc2_default: adc2_default {
 860                 function = "ADC2";
 861                 groups = "ADC2";
 862         };
 863
 864         pinctrl_adc3_default: adc3_default {
 865                 function = "ADC3";
 866                 groups = "ADC3";
 867         };
 868
 869         pinctrl_adc4_default: adc4_default {
 870                 function = "ADC4";
 871                 groups = "ADC4";
 872         };
 873
 874         pinctrl_adc5_default: adc5_default {
 875                 function = "ADC5";
 876                 groups = "ADC5";
 877         };
 878
 879         pinctrl_adc6_default: adc6_default {
 880                 function = "ADC6";
 881                 groups = "ADC6";
 882         };
 883
 884         pinctrl_adc7_default: adc7_default {
 885                 function = "ADC7";
 886                 groups = "ADC7";
 887         };
 888
 889         pinctrl_adc8_default: adc8_default {
 890                 function = "ADC8";
 891                 groups = "ADC8";
 892         };
 893
 894         pinctrl_adc9_default: adc9_default {
 895                 function = "ADC9";
 896                 groups = "ADC9";
 897         };
 898
 899         pinctrl_bmcint_default: bmcint_default {
 900                 function = "BMCINT";
 901                 groups = "BMCINT";
 902         };
 903
 904         pinctrl_ddcclk_default: ddcclk_default {
 905                 function = "DDCCLK";
 906                 groups = "DDCCLK";
 907         };
 908
 909         pinctrl_ddcdat_default: ddcdat_default {
 910                 function = "DDCDAT";
 911                 groups = "DDCDAT";
 912         };
 913
 914         pinctrl_espi_default: espi_default {
 915                 function = "ESPI";
 916                 groups = "ESPI";
 917         };
 918
 919         pinctrl_fwspics1_default: fwspics1_default {
 920                 function = "FWSPICS1";
 921                 groups = "FWSPICS1";
 922         };
 923
 924         pinctrl_fwspics2_default: fwspics2_default {
 925                 function = "FWSPICS2";
 926                 groups = "FWSPICS2";
 927         };
 928
 929         pinctrl_gpid0_default: gpid0_default {
 930                 function = "GPID0";
 931                 groups = "GPID0";
 932         };
 933
 934         pinctrl_gpid2_default: gpid2_default {
 935                 function = "GPID2";
 936                 groups = "GPID2";
 937         };
 938
 939         pinctrl_gpid4_default: gpid4_default {
 940                 function = "GPID4";
 941                 groups = "GPID4";
 942         };
 943
 944         pinctrl_gpid6_default: gpid6_default {
 945                 function = "GPID6";
 946                 groups = "GPID6";
 947         };
 948
 949         pinctrl_gpie0_default: gpie0_default {
 950                 function = "GPIE0";
 951                 groups = "GPIE0";
 952         };
 953
 954         pinctrl_gpie2_default: gpie2_default {
 955                 function = "GPIE2";
 956                 groups = "GPIE2";
 957         };
 958
 959         pinctrl_gpie4_default: gpie4_default {
 960                 function = "GPIE4";
 961                 groups = "GPIE4";
 962         };
 963
 964         pinctrl_gpie6_default: gpie6_default {
 965                 function = "GPIE6";
 966                 groups = "GPIE6";
 967         };
 968
 969         pinctrl_i2c10_default: i2c10_default {
 970                 function = "I2C10";
 971                 groups = "I2C10";
 972         };
 973
 974         pinctrl_i2c11_default: i2c11_default {
 975                 function = "I2C11";
 976                 groups = "I2C11";
 977         };
 978
 979         pinctrl_i2c12_default: i2c12_default {
 980                 function = "I2C12";
 981                 groups = "I2C12";
 982         };
 983
 984         pinctrl_i2c13_default: i2c13_default {
 985                 function = "I2C13";
 986                 groups = "I2C13";
 987         };
 988
 989         pinctrl_i2c14_default: i2c14_default {
 990                 function = "I2C14";
 991                 groups = "I2C14";
 992         };
 993
 994         pinctrl_i2c3_default: i2c3_default {
 995                 function = "I2C3";
 996                 groups = "I2C3";
 997         };
 998
 999         pinctrl_i2c4_default: i2c4_default {
1000                 function = "I2C4";
1001                 groups = "I2C4";
1002         };
1003
1004         pinctrl_i2c5_default: i2c5_default {
1005                 function = "I2C5";
1006                 groups = "I2C5";
1007         };
1008
1009         pinctrl_i2c6_default: i2c6_default {
1010                 function = "I2C6";
1011                 groups = "I2C6";
1012         };
1013
1014         pinctrl_i2c7_default: i2c7_default {
1015                 function = "I2C7";
1016                 groups = "I2C7";
1017         };
1018
1019         pinctrl_i2c8_default: i2c8_default {
1020                 function = "I2C8";
1021                 groups = "I2C8";
1022         };
1023
1024         pinctrl_i2c9_default: i2c9_default {
1025                 function = "I2C9";
1026                 groups = "I2C9";
1027         };
1028
1029         pinctrl_lad0_default: lad0_default {
1030                 function = "LAD0";
1031                 groups = "LAD0";
1032         };
1033
1034         pinctrl_lad1_default: lad1_default {
1035                 function = "LAD1";
1036                 groups = "LAD1";
1037         };
1038
1039         pinctrl_lad2_default: lad2_default {
1040                 function = "LAD2";
1041                 groups = "LAD2";
1042         };
1043
1044         pinctrl_lad3_default: lad3_default {
1045                 function = "LAD3";
1046                 groups = "LAD3";
1047         };
1048
1049         pinctrl_lclk_default: lclk_default {
1050                 function = "LCLK";
1051                 groups = "LCLK";
1052         };
1053
1054         pinctrl_lframe_default: lframe_default {
1055                 function = "LFRAME";
1056                 groups = "LFRAME";
1057         };
1058
1059         pinctrl_lpchc_default: lpchc_default {
1060                 function = "LPCHC";
1061                 groups = "LPCHC";
1062         };
1063
1064         pinctrl_lpcpd_default: lpcpd_default {
1065                 function = "LPCPD";
1066                 groups = "LPCPD";
1067         };
1068
1069         pinctrl_lpcplus_default: lpcplus_default {
1070                 function = "LPCPLUS";
1071                 groups = "LPCPLUS";
1072         };
1073
1074         pinctrl_lpcpme_default: lpcpme_default {
1075                 function = "LPCPME";
1076                 groups = "LPCPME";
1077         };
1078
1079         pinctrl_lpcrst_default: lpcrst_default {
1080                 function = "LPCRST";
1081                 groups = "LPCRST";
1082         };
1083
1084         pinctrl_lpcsmi_default: lpcsmi_default {
1085                 function = "LPCSMI";
1086                 groups = "LPCSMI";
1087         };
1088
1089         pinctrl_lsirq_default: lsirq_default {
1090                 function = "LSIRQ";
1091                 groups = "LSIRQ";
1092         };
1093
1094         pinctrl_mac1link_default: mac1link_default {
1095                 function = "MAC1LINK";
1096                 groups = "MAC1LINK";
1097         };
1098
1099         pinctrl_mac2link_default: mac2link_default {
1100                 function = "MAC2LINK";
1101                 groups = "MAC2LINK";
1102         };
1103
1104         pinctrl_mdio1_default: mdio1_default {
1105                 function = "MDIO1";
1106                 groups = "MDIO1";
1107         };
1108
1109         pinctrl_mdio2_default: mdio2_default {
1110                 function = "MDIO2";
1111                 groups = "MDIO2";
1112         };
1113
1114         pinctrl_ncts1_default: ncts1_default {
1115                 function = "NCTS1";
1116                 groups = "NCTS1";
1117         };
1118
1119         pinctrl_ncts2_default: ncts2_default {
1120                 function = "NCTS2";
1121                 groups = "NCTS2";
1122         };
1123
1124         pinctrl_ncts3_default: ncts3_default {
1125                 function = "NCTS3";
1126                 groups = "NCTS3";
1127         };
1128
1129         pinctrl_ncts4_default: ncts4_default {
1130                 function = "NCTS4";
1131                 groups = "NCTS4";
1132         };
1133
1134         pinctrl_ndcd1_default: ndcd1_default {
1135                 function = "NDCD1";
1136                 groups = "NDCD1";
1137         };
1138
1139         pinctrl_ndcd2_default: ndcd2_default {
1140                 function = "NDCD2";
1141                 groups = "NDCD2";
1142         };
1143
1144         pinctrl_ndcd3_default: ndcd3_default {
1145                 function = "NDCD3";
1146                 groups = "NDCD3";
1147         };
1148
1149         pinctrl_ndcd4_default: ndcd4_default {
1150                 function = "NDCD4";
1151                 groups = "NDCD4";
1152         };
1153
1154         pinctrl_ndsr1_default: ndsr1_default {
1155                 function = "NDSR1";
1156                 groups = "NDSR1";
1157         };
1158
1159         pinctrl_ndsr2_default: ndsr2_default {
1160                 function = "NDSR2";
1161                 groups = "NDSR2";
1162         };
1163
1164         pinctrl_ndsr3_default: ndsr3_default {
1165                 function = "NDSR3";
1166                 groups = "NDSR3";
1167         };
1168
1169         pinctrl_ndsr4_default: ndsr4_default {
1170                 function = "NDSR4";
1171                 groups = "NDSR4";
1172         };
1173
1174         pinctrl_ndtr1_default: ndtr1_default {
1175                 function = "NDTR1";
1176                 groups = "NDTR1";
1177         };
1178
1179         pinctrl_ndtr2_default: ndtr2_default {
1180                 function = "NDTR2";
1181                 groups = "NDTR2";
1182         };
1183
1184         pinctrl_ndtr3_default: ndtr3_default {
1185                 function = "NDTR3";
1186                 groups = "NDTR3";
1187         };
1188
1189         pinctrl_ndtr4_default: ndtr4_default {
1190                 function = "NDTR4";
1191                 groups = "NDTR4";
1192         };
1193
1194         pinctrl_nri1_default: nri1_default {
1195                 function = "NRI1";
1196                 groups = "NRI1";
1197         };
1198
1199         pinctrl_nri2_default: nri2_default {
1200                 function = "NRI2";
1201                 groups = "NRI2";
1202         };
1203
1204         pinctrl_nri3_default: nri3_default {
1205                 function = "NRI3";
1206                 groups = "NRI3";
1207         };
1208
1209         pinctrl_nri4_default: nri4_default {
1210                 function = "NRI4";
1211                 groups = "NRI4";
1212         };
1213
1214         pinctrl_nrts1_default: nrts1_default {
1215                 function = "NRTS1";
1216                 groups = "NRTS1";
1217         };
1218
1219         pinctrl_nrts2_default: nrts2_default {
1220                 function = "NRTS2";
1221                 groups = "NRTS2";
1222         };
1223
1224         pinctrl_nrts3_default: nrts3_default {
1225                 function = "NRTS3";
1226                 groups = "NRTS3";
1227         };
1228
1229         pinctrl_nrts4_default: nrts4_default {
1230                 function = "NRTS4";
1231                 groups = "NRTS4";
1232         };
1233
1234         pinctrl_oscclk_default: oscclk_default {
1235                 function = "OSCCLK";
1236                 groups = "OSCCLK";
1237         };
1238
1239         pinctrl_pewake_default: pewake_default {
1240                 function = "PEWAKE";
1241                 groups = "PEWAKE";
1242         };
1243
1244         pinctrl_pnor_default: pnor_default {
1245                 function = "PNOR";
1246                 groups = "PNOR";
1247         };
1248
1249         pinctrl_pwm0_default: pwm0_default {
1250                 function = "PWM0";
1251                 groups = "PWM0";
1252         };
1253
1254         pinctrl_pwm1_default: pwm1_default {
1255                 function = "PWM1";
1256                 groups = "PWM1";
1257         };
1258
1259         pinctrl_pwm2_default: pwm2_default {
1260                 function = "PWM2";
1261                 groups = "PWM2";
1262         };
1263
1264         pinctrl_pwm3_default: pwm3_default {
1265                 function = "PWM3";
1266                 groups = "PWM3";
1267         };
1268
1269         pinctrl_pwm4_default: pwm4_default {
1270                 function = "PWM4";
1271                 groups = "PWM4";
1272         };
1273
1274         pinctrl_pwm5_default: pwm5_default {
1275                 function = "PWM5";
1276                 groups = "PWM5";
1277         };
1278
1279         pinctrl_pwm6_default: pwm6_default {
1280                 function = "PWM6";
1281                 groups = "PWM6";
1282         };
1283
1284         pinctrl_pwm7_default: pwm7_default {
1285                 function = "PWM7";
1286                 groups = "PWM7";
1287         };
1288
1289         pinctrl_rgmii1_default: rgmii1_default {
1290                 function = "RGMII1";
1291                 groups = "RGMII1";
1292         };
1293
1294         pinctrl_rgmii2_default: rgmii2_default {
1295                 function = "RGMII2";
1296                 groups = "RGMII2";
1297         };
1298
1299         pinctrl_rmii1_default: rmii1_default {
1300                 function = "RMII1";
1301                 groups = "RMII1";
1302         };
1303
1304         pinctrl_rmii2_default: rmii2_default {
1305                 function = "RMII2";
1306                 groups = "RMII2";
1307         };
1308
1309         pinctrl_rxd1_default: rxd1_default {
1310                 function = "RXD1";
1311                 groups = "RXD1";
1312         };
1313
1314         pinctrl_rxd2_default: rxd2_default {
1315                 function = "RXD2";
1316                 groups = "RXD2";
1317         };
1318
1319         pinctrl_rxd3_default: rxd3_default {
1320                 function = "RXD3";
1321                 groups = "RXD3";
1322         };
1323
1324         pinctrl_rxd4_default: rxd4_default {
1325                 function = "RXD4";
1326                 groups = "RXD4";
1327         };
1328
1329         pinctrl_salt1_default: salt1_default {
1330                 function = "SALT1";
1331                 groups = "SALT1";
1332         };
1333
1334         pinctrl_salt10_default: salt10_default {
1335                 function = "SALT10";
1336                 groups = "SALT10";
1337         };
1338
1339         pinctrl_salt11_default: salt11_default {
1340                 function = "SALT11";
1341                 groups = "SALT11";
1342         };
1343
1344         pinctrl_salt12_default: salt12_default {
1345                 function = "SALT12";
1346                 groups = "SALT12";
1347         };
1348
1349         pinctrl_salt13_default: salt13_default {
1350                 function = "SALT13";
1351                 groups = "SALT13";
1352         };
1353
1354         pinctrl_salt14_default: salt14_default {
1355                 function = "SALT14";
1356                 groups = "SALT14";
1357         };
1358
1359         pinctrl_salt2_default: salt2_default {
1360                 function = "SALT2";
1361                 groups = "SALT2";
1362         };
1363
1364         pinctrl_salt3_default: salt3_default {
1365                 function = "SALT3";
1366                 groups = "SALT3";
1367         };
1368
1369         pinctrl_salt4_default: salt4_default {
1370                 function = "SALT4";
1371                 groups = "SALT4";
1372         };
1373
1374         pinctrl_salt5_default: salt5_default {
1375                 function = "SALT5";
1376                 groups = "SALT5";
1377         };
1378
1379         pinctrl_salt6_default: salt6_default {
1380                 function = "SALT6";
1381                 groups = "SALT6";
1382         };
1383
1384         pinctrl_salt7_default: salt7_default {
1385                 function = "SALT7";
1386                 groups = "SALT7";
1387         };
1388
1389         pinctrl_salt8_default: salt8_default {
1390                 function = "SALT8";
1391                 groups = "SALT8";
1392         };
1393
1394         pinctrl_salt9_default: salt9_default {
1395                 function = "SALT9";
1396                 groups = "SALT9";
1397         };
1398
1399         pinctrl_scl1_default: scl1_default {
1400                 function = "SCL1";
1401                 groups = "SCL1";
1402         };
1403
1404         pinctrl_scl2_default: scl2_default {
1405                 function = "SCL2";
1406                 groups = "SCL2";
1407         };
1408
1409         pinctrl_sd1_default: sd1_default {
1410                 function = "SD1";
1411                 groups = "SD1";
1412         };
1413
1414         pinctrl_sd2_default: sd2_default {
1415                 function = "SD2";
1416                 groups = "SD2";
1417         };
1418
1419         pinctrl_sda1_default: sda1_default {
1420                 function = "SDA1";
1421                 groups = "SDA1";
1422         };
1423
1424         pinctrl_sda2_default: sda2_default {
1425                 function = "SDA2";
1426                 groups = "SDA2";
1427         };
1428
1429         pinctrl_sgpm_default: sgpm_default {
1430                 function = "SGPM";
1431                 groups = "SGPM";
1432         };
1433
1434         pinctrl_sgps1_default: sgps1_default {
1435                 function = "SGPS1";
1436                 groups = "SGPS1";
1437         };
1438
1439         pinctrl_sgps2_default: sgps2_default {
1440                 function = "SGPS2";
1441                 groups = "SGPS2";
1442         };
1443
1444         pinctrl_sioonctrl_default: sioonctrl_default {
1445                 function = "SIOONCTRL";
1446                 groups = "SIOONCTRL";
1447         };
1448
1449         pinctrl_siopbi_default: siopbi_default {
1450                 function = "SIOPBI";
1451                 groups = "SIOPBI";
1452         };
1453
1454         pinctrl_siopbo_default: siopbo_default {
1455                 function = "SIOPBO";
1456                 groups = "SIOPBO";
1457         };
1458
1459         pinctrl_siopwreq_default: siopwreq_default {
1460                 function = "SIOPWREQ";
1461                 groups = "SIOPWREQ";
1462         };
1463
1464         pinctrl_siopwrgd_default: siopwrgd_default {
1465                 function = "SIOPWRGD";
1466                 groups = "SIOPWRGD";
1467         };
1468
1469         pinctrl_sios3_default: sios3_default {
1470                 function = "SIOS3";
1471                 groups = "SIOS3";
1472         };
1473
1474         pinctrl_sios5_default: sios5_default {
1475                 function = "SIOS5";
1476                 groups = "SIOS5";
1477         };
1478
1479         pinctrl_siosci_default: siosci_default {
1480                 function = "SIOSCI";
1481                 groups = "SIOSCI";
1482         };
1483
1484         pinctrl_spi1_default: spi1_default {
1485                 function = "SPI1";
1486                 groups = "SPI1";
1487         };
1488
1489         pinctrl_spi1cs1_default: spi1cs1_default {
1490                 function = "SPI1CS1";
1491                 groups = "SPI1CS1";
1492         };
1493
1494         pinctrl_spi1debug_default: spi1debug_default {
1495                 function = "SPI1DEBUG";
1496                 groups = "SPI1DEBUG";
1497         };
1498
1499         pinctrl_spi1passthru_default: spi1passthru_default {
1500                 function = "SPI1PASSTHRU";
1501                 groups = "SPI1PASSTHRU";
1502         };
1503
1504         pinctrl_spi2ck_default: spi2ck_default {
1505                 function = "SPI2CK";
1506                 groups = "SPI2CK";
1507         };
1508
1509         pinctrl_spi2cs0_default: spi2cs0_default {
1510                 function = "SPI2CS0";
1511                 groups = "SPI2CS0";
1512         };
1513
1514         pinctrl_spi2cs1_default: spi2cs1_default {
1515                 function = "SPI2CS1";
1516                 groups = "SPI2CS1";
1517         };
1518
1519         pinctrl_spi2miso_default: spi2miso_default {
1520                 function = "SPI2MISO";
1521                 groups = "SPI2MISO";
1522         };
1523
1524         pinctrl_spi2mosi_default: spi2mosi_default {
1525                 function = "SPI2MOSI";
1526                 groups = "SPI2MOSI";
1527         };
1528
1529         pinctrl_timer3_default: timer3_default {
1530                 function = "TIMER3";
1531                 groups = "TIMER3";
1532         };
1533
1534         pinctrl_timer4_default: timer4_default {
1535                 function = "TIMER4";
1536                 groups = "TIMER4";
1537         };
1538
1539         pinctrl_timer5_default: timer5_default {
1540                 function = "TIMER5";
1541                 groups = "TIMER5";
1542         };
1543
1544         pinctrl_timer6_default: timer6_default {
1545                 function = "TIMER6";
1546                 groups = "TIMER6";
1547         };
1548
1549         pinctrl_timer7_default: timer7_default {
1550                 function = "TIMER7";
1551                 groups = "TIMER7";
1552         };
1553
1554         pinctrl_timer8_default: timer8_default {
1555                 function = "TIMER8";
1556                 groups = "TIMER8";
1557         };
1558
1559         pinctrl_txd1_default: txd1_default {
1560                 function = "TXD1";
1561                 groups = "TXD1";
1562         };
1563
1564         pinctrl_txd2_default: txd2_default {
1565                 function = "TXD2";
1566                 groups = "TXD2";
1567         };
1568
1569         pinctrl_txd3_default: txd3_default {
1570                 function = "TXD3";
1571                 groups = "TXD3";
1572         };
1573
1574         pinctrl_txd4_default: txd4_default {
1575                 function = "TXD4";
1576                 groups = "TXD4";
1577         };
1578
1579         pinctrl_uart6_default: uart6_default {
1580                 function = "UART6";
1581                 groups = "UART6";
1582         };
1583
1584         pinctrl_usbcki_default: usbcki_default {
1585                 function = "USBCKI";
1586                 groups = "USBCKI";
1587         };
1588
1589         pinctrl_usb2ah_default: usb2ah_default {
1590                 function = "USB2AH";
1591                 groups = "USB2AH";
1592         };
1593
1594         pinctrl_usb2ad_default: usb2ad_default {
1595                 function = "USB2AD";
1596                 groups = "USB2AD";
1597         };
1598
1599         pinctrl_usb11bhid_default: usb11bhid_default {
1600                 function = "USB11BHID";
1601                 groups = "USB11BHID";
1602         };
1603
1604         pinctrl_usb2bh_default: usb2bh_default {
1605                 function = "USB2BH";
1606                 groups = "USB2BH";
1607         };
1608
1609         pinctrl_vgabiosrom_default: vgabiosrom_default {
1610                 function = "VGABIOSROM";
1611                 groups = "VGABIOSROM";
1612         };
1613
1614         pinctrl_vgahs_default: vgahs_default {
1615                 function = "VGAHS";
1616                 groups = "VGAHS";
1617         };
1618
1619         pinctrl_vgavs_default: vgavs_default {
1620                 function = "VGAVS";
1621                 groups = "VGAVS";
1622         };
1623
1624         pinctrl_vpi24_default: vpi24_default {
1625                 function = "VPI24";
1626                 groups = "VPI24";
1627         };
1628
1629         pinctrl_vpo_default: vpo_default {
1630                 function = "VPO";
1631                 groups = "VPO";
1632         };
1633
1634         pinctrl_wdtrst1_default: wdtrst1_default {
1635                 function = "WDTRST1";
1636                 groups = "WDTRST1";
1637         };
1638
1639         pinctrl_wdtrst2_default: wdtrst2_default {
1640                 function = "WDTRST2";
1641                 groups = "WDTRST2";
1642         };
1643 };