arch/arm/boot/dts/aspeed-g4.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <dt-bindings/clock/aspeed-clock.h>
   3
   4 / {
   5         model = "Aspeed BMC";
   6         compatible = "aspeed,ast2400";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 i2c0 = &i2c0;
  13                 i2c1 = &i2c1;
  14                 i2c2 = &i2c2;
  15                 i2c3 = &i2c3;
  16                 i2c4 = &i2c4;
  17                 i2c5 = &i2c5;
  18                 i2c6 = &i2c6;
  19                 i2c7 = &i2c7;
  20                 i2c8 = &i2c8;
  21                 i2c9 = &i2c9;
  22                 i2c10 = &i2c10;
  23                 i2c11 = &i2c11;
  24                 i2c12 = &i2c12;
  25                 i2c13 = &i2c13;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 serial4 = &uart5;
  31                 serial5 = &vuart;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         compatible = "arm,arm926ej-s";
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                 };
  43         };
  44
  45         memory@40000000 {
  46                 device_type = "memory";
  47                 reg = <0x40000000 0>;
  48         };
  49
  50         ahb {
  51                 compatible = "simple-bus";
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges;
  55
  56                 fmc: spi@1e620000 {
  57                         reg = < 0x1e620000 0x94
  58                                 0x20000000 0x10000000 >;
  59                         #address-cells = <1>;
  60                         #size-cells = <0>;
  61                         compatible = "aspeed,ast2400-fmc";
  62                         clocks = <&syscon ASPEED_CLK_AHB>;
  63                         status = "disabled";
  64                         interrupts = <19>;
  65                         flash@0 {
  66                                 reg = < 0 >;
  67                                 compatible = "jedec,spi-nor";
  68                                 spi-max-frequency = <50000000>;
  69                                 status = "disabled";
  70                         };
  71                         flash@1 {
  72                                 reg = < 1 >;
  73                                 compatible = "jedec,spi-nor";
  74                                 status = "disabled";
  75                         };
  76                         flash@2 {
  77                                 reg = < 2 >;
  78                                 compatible = "jedec,spi-nor";
  79                                 status = "disabled";
  80                         };
  81                         flash@3 {
  82                                 reg = < 3 >;
  83                                 compatible = "jedec,spi-nor";
  84                                 status = "disabled";
  85                         };
  86                         flash@4 {
  87                                 reg = < 4 >;
  88                                 compatible = "jedec,spi-nor";
  89                                 status = "disabled";
  90                         };
  91                 };
  92
  93                 spi: spi@1e630000 {
  94                         reg = < 0x1e630000 0x18
  95                                 0x30000000 0x10000000 >;
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98                         compatible = "aspeed,ast2400-spi";
  99                         clocks = <&syscon ASPEED_CLK_AHB>;
 100                         status = "disabled";
 101                         flash@0 {
 102                                 reg = < 0 >;
 103                                 compatible = "jedec,spi-nor";
 104                                 spi-max-frequency = <50000000>;
 105                                 status = "disabled";
 106                         };
 107                 };
 108
 109                 vic: interrupt-controller@1e6c0080 {
 110                         compatible = "aspeed,ast2400-vic";
 111                         interrupt-controller;
 112                         #interrupt-cells = <1>;
 113                         valid-sources = <0xffffffff 0x0007ffff>;
 114                         reg = <0x1e6c0080 0x80>;
 115                 };
 116
 117                 cvic: copro-interrupt-controller@1e6c2000 {
 118                         compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
 119                         valid-sources = <0x7fffffff>;
 120                         reg = <0x1e6c2000 0x80>;
 121                 };
 122
 123                 mac0: ethernet@1e660000 {
 124                         compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
 125                         reg = <0x1e660000 0x180>;
 126                         interrupts = <2>;
 127                         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
 128                         status = "disabled";
 129                 };
 130
 131                 mac1: ethernet@1e680000 {
 132                         compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
 133                         reg = <0x1e680000 0x180>;
 134                         interrupts = <3>;
 135                         clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
 136                         status = "disabled";
 137                 };
 138
 139                 ehci0: usb@1e6a1000 {
 140                         compatible = "aspeed,ast2400-ehci", "generic-ehci";
 141                         reg = <0x1e6a1000 0x100>;
 142                         interrupts = <5>;
 143                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 144                         pinctrl-names = "default";
 145                         pinctrl-0 = <&pinctrl_usb2h_default>;
 146                         status = "disabled";
 147                 };
 148
 149                 uhci: usb@1e6b0000 {
 150                         compatible = "aspeed,ast2400-uhci", "generic-uhci";
 151                         reg = <0x1e6b0000 0x100>;
 152                         interrupts = <14>;
 153                         #ports = <3>;
 154                         clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
 155                         status = "disabled";
 156                         /*
 157                          * No default pinmux, it will follow EHCI, use an explicit pinmux
 158                          * override if you don't enable EHCI
 159                          */
 160                 };
 161
 162                 vhub: usb-vhub@1e6a0000 {
 163                         compatible = "aspeed,ast2400-usb-vhub";
 164                         reg = <0x1e6a0000 0x300>;
 165                         interrupts = <5>;
 166                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 167                         aspeed,vhub-downstream-ports = <5>;
 168                         aspeed,vhub-generic-endpoints = <15>;
 169                         pinctrl-names = "default";
 170                         pinctrl-0 = <&pinctrl_usb2d_default>;
 171                         status = "disabled";
 172                 };
 173
 174                 apb {
 175                         compatible = "simple-bus";
 176                         #address-cells = <1>;
 177                         #size-cells = <1>;
 178                         ranges;
 179
 180                         syscon: syscon@1e6e2000 {
 181                                 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
 182                                 reg = <0x1e6e2000 0x1a8>;
 183                                 #address-cells = <1>;
 184                                 #size-cells = <1>;
 185                                 ranges = <0 0x1e6e2000 0x1000>;
 186                                 #clock-cells = <1>;
 187                                 #reset-cells = <1>;
 188
 189                                 p2a: p2a-control@2c {
 190                                         reg = <0x2c 0x4>;
 191                                         compatible = "aspeed,ast2400-p2a-ctrl";
 192                                         status = "disabled";
 193                                 };
 194
 195                                 silicon-id@7c {
 196                                         compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id";
 197                                         reg = <0x7c 0x4>;
 198                                 };
 199
 200                                 pinctrl: pinctrl@80 {
 201                                         reg = <0x80 0x18>, <0xa0 0x10>;
 202                                         compatible = "aspeed,ast2400-pinctrl";
 203                                 };
 204                         };
 205
 206                         rng: hwrng@1e6e2078 {
 207                                 compatible = "timeriomem_rng";
 208                                 reg = <0x1e6e2078 0x4>;
 209                                 period = <1>;
 210                                 quality = <100>;
 211                         };
 212
 213                         adc: adc@1e6e9000 {
 214                                 compatible = "aspeed,ast2400-adc";
 215                                 reg = <0x1e6e9000 0xb0>;
 216                                 clocks = <&syscon ASPEED_CLK_APB>;
 217                                 resets = <&syscon ASPEED_RESET_ADC>;
 218                                 #io-channel-cells = <1>;
 219                                 status = "disabled";
 220                         };
 221
 222                         sram: sram@1e720000 {
 223                                 compatible = "mmio-sram";
 224                                 reg = <0x1e720000 0x8000>;      // 32K
 225                         };
 226
 227                         video: video@1e700000 {
 228                                 compatible = "aspeed,ast2400-video-engine";
 229                                 reg = <0x1e700000 0x1000>;
 230                                 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
 231                                          <&syscon ASPEED_CLK_GATE_ECLK>;
 232                                 clock-names = "vclk", "eclk";
 233                                 interrupts = <7>;
 234                                 status = "disabled";
 235                         };
 236
 237                         sdmmc: sd-controller@1e740000 {
 238                                 compatible = "aspeed,ast2400-sd-controller";
 239                                 reg = <0x1e740000 0x100>;
 240                                 #address-cells = <1>;
 241                                 #size-cells = <1>;
 242                                 ranges = <0 0x1e740000 0x10000>;
 243                                 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
 244                                 status = "disabled";
 245
 246                                 sdhci0: sdhci@100 {
 247                                         compatible = "aspeed,ast2400-sdhci";
 248                                         reg = <0x100 0x100>;
 249                                         interrupts = <26>;
 250                                         sdhci,auto-cmd12;
 251                                         clocks = <&syscon ASPEED_CLK_SDIO>;
 252                                         status = "disabled";
 253                                 };
 254
 255                                 sdhci1: sdhci@200 {
 256                                         compatible = "aspeed,ast2400-sdhci";
 257                                         reg = <0x200 0x100>;
 258                                         interrupts = <26>;
 259                                         sdhci,auto-cmd12;
 260                                         clocks = <&syscon ASPEED_CLK_SDIO>;
 261                                         status = "disabled";
 262                                 };
 263                         };
 264
 265                         gpio: gpio@1e780000 {
 266                                 #gpio-cells = <2>;
 267                                 gpio-controller;
 268                                 compatible = "aspeed,ast2400-gpio";
 269                                 reg = <0x1e780000 0x1000>;
 270                                 interrupts = <20>;
 271                                 gpio-ranges = <&pinctrl 0 0 220>;
 272                                 clocks = <&syscon ASPEED_CLK_APB>;
 273                                 interrupt-controller;
 274                                 #interrupt-cells = <2>;
 275                         };
 276
 277                         timer: timer@1e782000 {
 278                                 /* This timer is a Faraday FTTMR010 derivative */
 279                                 compatible = "aspeed,ast2400-timer";
 280                                 reg = <0x1e782000 0x90>;
 281                                 interrupts = <16 17 18 35 36 37 38 39>;
 282                                 clocks = <&syscon ASPEED_CLK_APB>;
 283                                 clock-names = "PCLK";
 284                         };
 285
 286                         rtc: rtc@1e781000 {
 287                                 compatible = "aspeed,ast2400-rtc";
 288                                 reg = <0x1e781000 0x18>;
 289                                 status = "disabled";
 290                         };
 291
 292                         uart1: serial@1e783000 {
 293                                 compatible = "ns16550a";
 294                                 reg = <0x1e783000 0x20>;
 295                                 reg-shift = <2>;
 296                                 interrupts = <9>;
 297                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
 298                                 resets = <&lpc_reset 4>;
 299                                 no-loopback-test;
 300                                 status = "disabled";
 301                         };
 302
 303                         uart5: serial@1e784000 {
 304                                 compatible = "ns16550a";
 305                                 reg = <0x1e784000 0x20>;
 306                                 reg-shift = <2>;
 307                                 interrupts = <10>;
 308                                 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
 309                                 no-loopback-test;
 310                                 status = "disabled";
 311                         };
 312
 313                         wdt1: watchdog@1e785000 {
 314                                 compatible = "aspeed,ast2400-wdt";
 315                                 reg = <0x1e785000 0x1c>;
 316                                 clocks = <&syscon ASPEED_CLK_APB>;
 317                         };
 318
 319                         wdt2: watchdog@1e785020 {
 320                                 compatible = "aspeed,ast2400-wdt";
 321                                 reg = <0x1e785020 0x1c>;
 322                                 clocks = <&syscon ASPEED_CLK_APB>;
 323                         };
 324
 325                         pwm_tacho: pwm-tacho-controller@1e786000 {
 326                                 compatible = "aspeed,ast2400-pwm-tacho";
 327                                 #address-cells = <1>;
 328                                 #size-cells = <0>;
 329                                 reg = <0x1e786000 0x1000>;
 330                                 clocks = <&syscon ASPEED_CLK_24M>;
 331                                 resets = <&syscon ASPEED_RESET_PWM>;
 332                                 status = "disabled";
 333                         };
 334
 335                         vuart: serial@1e787000 {
 336                                 compatible = "aspeed,ast2400-vuart";
 337                                 reg = <0x1e787000 0x40>;
 338                                 reg-shift = <2>;
 339                                 interrupts = <8>;
 340                                 clocks = <&syscon ASPEED_CLK_APB>;
 341                                 no-loopback-test;
 342                                 status = "disabled";
 343                         };
 344
 345                         lpc: lpc@1e789000 {
 346                                 compatible = "aspeed,ast2400-lpc", "simple-mfd";
 347                                 reg = <0x1e789000 0x1000>;
 348
 349                                 #address-cells = <1>;
 350                                 #size-cells = <1>;
 351                                 ranges = <0x0 0x1e789000 0x1000>;
 352
 353                                 lpc_bmc: lpc-bmc@0 {
 354                                         compatible = "aspeed,ast2400-lpc-bmc";
 355                                         reg = <0x0 0x80>;
 356                                 };
 357
 358                                 lpc_host: lpc-host@80 {
 359                                         compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
 360                                         reg = <0x80 0x1e0>;
 361                                         reg-io-width = <4>;
 362
 363                                         #address-cells = <1>;
 364                                         #size-cells = <1>;
 365                                         ranges = <0x0 0x80 0x1e0>;
 366
 367                                         lpc_ctrl: lpc-ctrl@0 {
 368                                                 compatible = "aspeed,ast2400-lpc-ctrl";
 369                                                 reg = <0x0 0x10>;
 370                                                 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
 371                                                 status = "disabled";
 372                                         };
 373
 374                                         lpc_snoop: lpc-snoop@10 {
 375                                                 compatible = "aspeed,ast2400-lpc-snoop";
 376                                                 reg = <0x10 0x8>;
 377                                                 interrupts = <8>;
 378                                                 status = "disabled";
 379                                         };
 380
 381                                         lhc: lhc@20 {
 382                                                 compatible = "aspeed,ast2400-lhc";
 383                                                 reg = <0x20 0x24 0x48 0x8>;
 384                                         };
 385
 386                                         lpc_reset: reset-controller@18 {
 387                                                 compatible = "aspeed,ast2400-lpc-reset";
 388                                                 reg = <0x18 0x4>;
 389                                                 #reset-cells = <1>;
 390                                         };
 391
 392                                         ibt: ibt@c0  {
 393                                                 compatible = "aspeed,ast2400-ibt-bmc";
 394                                                 reg = <0xc0 0x18>;
 395                                                 interrupts = <8>;
 396                                                 status = "disabled";
 397                                         };
 398                                 };
 399                         };
 400
 401                         uart2: serial@1e78d000 {
 402                                 compatible = "ns16550a";
 403                                 reg = <0x1e78d000 0x20>;
 404                                 reg-shift = <2>;
 405                                 interrupts = <32>;
 406                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
 407                                 resets = <&lpc_reset 5>;
 408                                 no-loopback-test;
 409                                 status = "disabled";
 410                         };
 411
 412                         uart3: serial@1e78e000 {
 413                                 compatible = "ns16550a";
 414                                 reg = <0x1e78e000 0x20>;
 415                                 reg-shift = <2>;
 416                                 interrupts = <33>;
 417                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
 418                                 resets = <&lpc_reset 6>;
 419                                 no-loopback-test;
 420                                 status = "disabled";
 421                         };
 422
 423                         uart4: serial@1e78f000 {
 424                                 compatible = "ns16550a";
 425                                 reg = <0x1e78f000 0x20>;
 426                                 reg-shift = <2>;
 427                                 interrupts = <34>;
 428                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
 429                                 resets = <&lpc_reset 7>;
 430                                 no-loopback-test;
 431                                 status = "disabled";
 432                         };
 433
 434                         i2c: bus@1e78a000 {
 435                                 compatible = "simple-bus";
 436                                 #address-cells = <1>;
 437                                 #size-cells = <1>;
 438                                 ranges = <0 0x1e78a000 0x1000>;
 439                         };
 440                 };
 441         };
 442 };
 443
 444 &i2c {
 445         i2c_ic: interrupt-controller@0 {
 446                 #interrupt-cells = <1>;
 447                 compatible = "aspeed,ast2400-i2c-ic";
 448                 reg = <0x0 0x40>;
 449                 interrupts = <12>;
 450                 interrupt-controller;
 451         };
 452
 453         i2c0: i2c-bus@40 {
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 #interrupt-cells = <1>;
 457
 458                 reg = <0x40 0x40>;
 459                 compatible = "aspeed,ast2400-i2c-bus";
 460                 clocks = <&syscon ASPEED_CLK_APB>;
 461                 resets = <&syscon ASPEED_RESET_I2C>;
 462                 bus-frequency = <100000>;
 463                 interrupts = <0>;
 464                 interrupt-parent = <&i2c_ic>;
 465                 status = "disabled";
 466                 /* Does not need pinctrl properties */
 467         };
 468
 469         i2c1: i2c-bus@80 {
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 #interrupt-cells = <1>;
 473
 474                 reg = <0x80 0x40>;
 475                 compatible = "aspeed,ast2400-i2c-bus";
 476                 clocks = <&syscon ASPEED_CLK_APB>;
 477                 resets = <&syscon ASPEED_RESET_I2C>;
 478                 bus-frequency = <100000>;
 479                 interrupts = <1>;
 480                 interrupt-parent = <&i2c_ic>;
 481                 status = "disabled";
 482                 /* Does not need pinctrl properties */
 483         };
 484
 485         i2c2: i2c-bus@c0 {
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 #interrupt-cells = <1>;
 489
 490                 reg = <0xc0 0x40>;
 491                 compatible = "aspeed,ast2400-i2c-bus";
 492                 clocks = <&syscon ASPEED_CLK_APB>;
 493                 resets = <&syscon ASPEED_RESET_I2C>;
 494                 bus-frequency = <100000>;
 495                 interrupts = <2>;
 496                 interrupt-parent = <&i2c_ic>;
 497                 pinctrl-names = "default";
 498                 pinctrl-0 = <&pinctrl_i2c3_default>;
 499                 status = "disabled";
 500         };
 501
 502         i2c3: i2c-bus@100 {
 503                 #address-cells = <1>;
 504                 #size-cells = <0>;
 505                 #interrupt-cells = <1>;
 506
 507                 reg = <0x100 0x40>;
 508                 compatible = "aspeed,ast2400-i2c-bus";
 509                 clocks = <&syscon ASPEED_CLK_APB>;
 510                 resets = <&syscon ASPEED_RESET_I2C>;
 511                 bus-frequency = <100000>;
 512                 interrupts = <3>;
 513                 interrupt-parent = <&i2c_ic>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&pinctrl_i2c4_default>;
 516                 status = "disabled";
 517         };
 518
 519         i2c4: i2c-bus@140 {
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 #interrupt-cells = <1>;
 523
 524                 reg = <0x140 0x40>;
 525                 compatible = "aspeed,ast2400-i2c-bus";
 526                 clocks = <&syscon ASPEED_CLK_APB>;
 527                 resets = <&syscon ASPEED_RESET_I2C>;
 528                 bus-frequency = <100000>;
 529                 interrupts = <4>;
 530                 interrupt-parent = <&i2c_ic>;
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&pinctrl_i2c5_default>;
 533                 status = "disabled";
 534         };
 535
 536         i2c5: i2c-bus@180 {
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 #interrupt-cells = <1>;
 540
 541                 reg = <0x180 0x40>;
 542                 compatible = "aspeed,ast2400-i2c-bus";
 543                 clocks = <&syscon ASPEED_CLK_APB>;
 544                 resets = <&syscon ASPEED_RESET_I2C>;
 545                 bus-frequency = <100000>;
 546                 interrupts = <5>;
 547                 interrupt-parent = <&i2c_ic>;
 548                 pinctrl-names = "default";
 549                 pinctrl-0 = <&pinctrl_i2c6_default>;
 550                 status = "disabled";
 551         };
 552
 553         i2c6: i2c-bus@1c0 {
 554                 #address-cells = <1>;
 555                 #size-cells = <0>;
 556                 #interrupt-cells = <1>;
 557
 558                 reg = <0x1c0 0x40>;
 559                 compatible = "aspeed,ast2400-i2c-bus";
 560                 clocks = <&syscon ASPEED_CLK_APB>;
 561                 resets = <&syscon ASPEED_RESET_I2C>;
 562                 bus-frequency = <100000>;
 563                 interrupts = <6>;
 564                 interrupt-parent = <&i2c_ic>;
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&pinctrl_i2c7_default>;
 567                 status = "disabled";
 568         };
 569
 570         i2c7: i2c-bus@300 {
 571                 #address-cells = <1>;
 572                 #size-cells = <0>;
 573                 #interrupt-cells = <1>;
 574
 575                 reg = <0x300 0x40>;
 576                 compatible = "aspeed,ast2400-i2c-bus";
 577                 clocks = <&syscon ASPEED_CLK_APB>;
 578                 resets = <&syscon ASPEED_RESET_I2C>;
 579                 bus-frequency = <100000>;
 580                 interrupts = <7>;
 581                 interrupt-parent = <&i2c_ic>;
 582                 pinctrl-names = "default";
 583                 pinctrl-0 = <&pinctrl_i2c8_default>;
 584                 status = "disabled";
 585         };
 586
 587         i2c8: i2c-bus@340 {
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590                 #interrupt-cells = <1>;
 591
 592                 reg = <0x340 0x40>;
 593                 compatible = "aspeed,ast2400-i2c-bus";
 594                 clocks = <&syscon ASPEED_CLK_APB>;
 595                 resets = <&syscon ASPEED_RESET_I2C>;
 596                 bus-frequency = <100000>;
 597                 interrupts = <8>;
 598                 interrupt-parent = <&i2c_ic>;
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&pinctrl_i2c9_default>;
 601                 status = "disabled";
 602         };
 603
 604         i2c9: i2c-bus@380 {
 605                 #address-cells = <1>;
 606                 #size-cells = <0>;
 607                 #interrupt-cells = <1>;
 608
 609                 reg = <0x380 0x40>;
 610                 compatible = "aspeed,ast2400-i2c-bus";
 611                 clocks = <&syscon ASPEED_CLK_APB>;
 612                 resets = <&syscon ASPEED_RESET_I2C>;
 613                 bus-frequency = <100000>;
 614                 interrupts = <9>;
 615                 interrupt-parent = <&i2c_ic>;
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&pinctrl_i2c10_default>;
 618                 status = "disabled";
 619         };
 620
 621         i2c10: i2c-bus@3c0 {
 622                 #address-cells = <1>;
 623                 #size-cells = <0>;
 624                 #interrupt-cells = <1>;
 625
 626                 reg = <0x3c0 0x40>;
 627                 compatible = "aspeed,ast2400-i2c-bus";
 628                 clocks = <&syscon ASPEED_CLK_APB>;
 629                 resets = <&syscon ASPEED_RESET_I2C>;
 630                 bus-frequency = <100000>;
 631                 interrupts = <10>;
 632                 interrupt-parent = <&i2c_ic>;
 633                 pinctrl-names = "default";
 634                 pinctrl-0 = <&pinctrl_i2c11_default>;
 635                 status = "disabled";
 636         };
 637
 638         i2c11: i2c-bus@400 {
 639                 #address-cells = <1>;
 640                 #size-cells = <0>;
 641                 #interrupt-cells = <1>;
 642
 643                 reg = <0x400 0x40>;
 644                 compatible = "aspeed,ast2400-i2c-bus";
 645                 clocks = <&syscon ASPEED_CLK_APB>;
 646                 resets = <&syscon ASPEED_RESET_I2C>;
 647                 bus-frequency = <100000>;
 648                 interrupts = <11>;
 649                 interrupt-parent = <&i2c_ic>;
 650                 pinctrl-names = "default";
 651                 pinctrl-0 = <&pinctrl_i2c12_default>;
 652                 status = "disabled";
 653         };
 654
 655         i2c12: i2c-bus@440 {
 656                 #address-cells = <1>;
 657                 #size-cells = <0>;
 658                 #interrupt-cells = <1>;
 659
 660                 reg = <0x440 0x40>;
 661                 compatible = "aspeed,ast2400-i2c-bus";
 662                 clocks = <&syscon ASPEED_CLK_APB>;
 663                 resets = <&syscon ASPEED_RESET_I2C>;
 664                 bus-frequency = <100000>;
 665                 interrupts = <12>;
 666                 interrupt-parent = <&i2c_ic>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&pinctrl_i2c13_default>;
 669                 status = "disabled";
 670         };
 671
 672         i2c13: i2c-bus@480 {
 673                 #address-cells = <1>;
 674                 #size-cells = <0>;
 675                 #interrupt-cells = <1>;
 676
 677                 reg = <0x480 0x40>;
 678                 compatible = "aspeed,ast2400-i2c-bus";
 679                 clocks = <&syscon ASPEED_CLK_APB>;
 680                 resets = <&syscon ASPEED_RESET_I2C>;
 681                 bus-frequency = <100000>;
 682                 interrupts = <13>;
 683                 interrupt-parent = <&i2c_ic>;
 684                 pinctrl-names = "default";
 685                 pinctrl-0 = <&pinctrl_i2c14_default>;
 686                 status = "disabled";
 687         };
 688 };
 689
 690 &pinctrl {
 691         pinctrl_acpi_default: acpi_default {
 692                 function = "ACPI";
 693                 groups = "ACPI";
 694         };
 695
 696         pinctrl_adc0_default: adc0_default {
 697                 function = "ADC0";
 698                 groups = "ADC0";
 699         };
 700
 701         pinctrl_adc1_default: adc1_default {
 702                 function = "ADC1";
 703                 groups = "ADC1";
 704         };
 705
 706         pinctrl_adc10_default: adc10_default {
 707                 function = "ADC10";
 708                 groups = "ADC10";
 709         };
 710
 711         pinctrl_adc11_default: adc11_default {
 712                 function = "ADC11";
 713                 groups = "ADC11";
 714         };
 715
 716         pinctrl_adc12_default: adc12_default {
 717                 function = "ADC12";
 718                 groups = "ADC12";
 719         };
 720
 721         pinctrl_adc13_default: adc13_default {
 722                 function = "ADC13";
 723                 groups = "ADC13";
 724         };
 725
 726         pinctrl_adc14_default: adc14_default {
 727                 function = "ADC14";
 728                 groups = "ADC14";
 729         };
 730
 731         pinctrl_adc15_default: adc15_default {
 732                 function = "ADC15";
 733                 groups = "ADC15";
 734         };
 735
 736         pinctrl_adc2_default: adc2_default {
 737                 function = "ADC2";
 738                 groups = "ADC2";
 739         };
 740
 741         pinctrl_adc3_default: adc3_default {
 742                 function = "ADC3";
 743                 groups = "ADC3";
 744         };
 745
 746         pinctrl_adc4_default: adc4_default {
 747                 function = "ADC4";
 748                 groups = "ADC4";
 749         };
 750
 751         pinctrl_adc5_default: adc5_default {
 752                 function = "ADC5";
 753                 groups = "ADC5";
 754         };
 755
 756         pinctrl_adc6_default: adc6_default {
 757                 function = "ADC6";
 758                 groups = "ADC6";
 759         };
 760
 761         pinctrl_adc7_default: adc7_default {
 762                 function = "ADC7";
 763                 groups = "ADC7";
 764         };
 765
 766         pinctrl_adc8_default: adc8_default {
 767                 function = "ADC8";
 768                 groups = "ADC8";
 769         };
 770
 771         pinctrl_adc9_default: adc9_default {
 772                 function = "ADC9";
 773                 groups = "ADC9";
 774         };
 775
 776         pinctrl_bmcint_default: bmcint_default {
 777                 function = "BMCINT";
 778                 groups = "BMCINT";
 779         };
 780
 781         pinctrl_ddcclk_default: ddcclk_default {
 782                 function = "DDCCLK";
 783                 groups = "DDCCLK";
 784         };
 785
 786         pinctrl_ddcdat_default: ddcdat_default {
 787                 function = "DDCDAT";
 788                 groups = "DDCDAT";
 789         };
 790
 791         pinctrl_extrst_default: extrst_default {
 792                 function = "EXTRST";
 793                 groups = "EXTRST";
 794         };
 795
 796         pinctrl_flack_default: flack_default {
 797                 function = "FLACK";
 798                 groups = "FLACK";
 799         };
 800
 801         pinctrl_flbusy_default: flbusy_default {
 802                 function = "FLBUSY";
 803                 groups = "FLBUSY";
 804         };
 805
 806         pinctrl_flwp_default: flwp_default {
 807                 function = "FLWP";
 808                 groups = "FLWP";
 809         };
 810
 811         pinctrl_gpid_default: gpid_default {
 812                 function = "GPID";
 813                 groups = "GPID";
 814         };
 815
 816         pinctrl_gpid0_default: gpid0_default {
 817                 function = "GPID0";
 818                 groups = "GPID0";
 819         };
 820
 821         pinctrl_gpid2_default: gpid2_default {
 822                 function = "GPID2";
 823                 groups = "GPID2";
 824         };
 825
 826         pinctrl_gpid4_default: gpid4_default {
 827                 function = "GPID4";
 828                 groups = "GPID4";
 829         };
 830
 831         pinctrl_gpid6_default: gpid6_default {
 832                 function = "GPID6";
 833                 groups = "GPID6";
 834         };
 835
 836         pinctrl_gpie0_default: gpie0_default {
 837                 function = "GPIE0";
 838                 groups = "GPIE0";
 839         };
 840
 841         pinctrl_gpie2_default: gpie2_default {
 842                 function = "GPIE2";
 843                 groups = "GPIE2";
 844         };
 845
 846         pinctrl_gpie4_default: gpie4_default {
 847                 function = "GPIE4";
 848                 groups = "GPIE4";
 849         };
 850
 851         pinctrl_gpie6_default: gpie6_default {
 852                 function = "GPIE6";
 853                 groups = "GPIE6";
 854         };
 855
 856         pinctrl_i2c10_default: i2c10_default {
 857                 function = "I2C10";
 858                 groups = "I2C10";
 859         };
 860
 861         pinctrl_i2c11_default: i2c11_default {
 862                 function = "I2C11";
 863                 groups = "I2C11";
 864         };
 865
 866         pinctrl_i2c12_default: i2c12_default {
 867                 function = "I2C12";
 868                 groups = "I2C12";
 869         };
 870
 871         pinctrl_i2c13_default: i2c13_default {
 872                 function = "I2C13";
 873                 groups = "I2C13";
 874         };
 875
 876         pinctrl_i2c14_default: i2c14_default {
 877                 function = "I2C14";
 878                 groups = "I2C14";
 879         };
 880
 881         pinctrl_i2c3_default: i2c3_default {
 882                 function = "I2C3";
 883                 groups = "I2C3";
 884         };
 885
 886         pinctrl_i2c4_default: i2c4_default {
 887                 function = "I2C4";
 888                 groups = "I2C4";
 889         };
 890
 891         pinctrl_i2c5_default: i2c5_default {
 892                 function = "I2C5";
 893                 groups = "I2C5";
 894         };
 895
 896         pinctrl_i2c6_default: i2c6_default {
 897                 function = "I2C6";
 898                 groups = "I2C6";
 899         };
 900
 901         pinctrl_i2c7_default: i2c7_default {
 902                 function = "I2C7";
 903                 groups = "I2C7";
 904         };
 905
 906         pinctrl_i2c8_default: i2c8_default {
 907                 function = "I2C8";
 908                 groups = "I2C8";
 909         };
 910
 911         pinctrl_i2c9_default: i2c9_default {
 912                 function = "I2C9";
 913                 groups = "I2C9";
 914         };
 915
 916         pinctrl_lpcpd_default: lpcpd_default {
 917                 function = "LPCPD";
 918                 groups = "LPCPD";
 919         };
 920
 921         pinctrl_lpcpme_default: lpcpme_default {
 922                 function = "LPCPME";
 923                 groups = "LPCPME";
 924         };
 925
 926         pinctrl_lpcrst_default: lpcrst_default {
 927                 function = "LPCRST";
 928                 groups = "LPCRST";
 929         };
 930
 931         pinctrl_lpcsmi_default: lpcsmi_default {
 932                 function = "LPCSMI";
 933                 groups = "LPCSMI";
 934         };
 935
 936         pinctrl_mac1link_default: mac1link_default {
 937                 function = "MAC1LINK";
 938                 groups = "MAC1LINK";
 939         };
 940
 941         pinctrl_mac2link_default: mac2link_default {
 942                 function = "MAC2LINK";
 943                 groups = "MAC2LINK";
 944         };
 945
 946         pinctrl_mdio1_default: mdio1_default {
 947                 function = "MDIO1";
 948                 groups = "MDIO1";
 949         };
 950
 951         pinctrl_mdio2_default: mdio2_default {
 952                 function = "MDIO2";
 953                 groups = "MDIO2";
 954         };
 955
 956         pinctrl_ncts1_default: ncts1_default {
 957                 function = "NCTS1";
 958                 groups = "NCTS1";
 959         };
 960
 961         pinctrl_ncts2_default: ncts2_default {
 962                 function = "NCTS2";
 963                 groups = "NCTS2";
 964         };
 965
 966         pinctrl_ncts3_default: ncts3_default {
 967                 function = "NCTS3";
 968                 groups = "NCTS3";
 969         };
 970
 971         pinctrl_ncts4_default: ncts4_default {
 972                 function = "NCTS4";
 973                 groups = "NCTS4";
 974         };
 975
 976         pinctrl_ndcd1_default: ndcd1_default {
 977                 function = "NDCD1";
 978                 groups = "NDCD1";
 979         };
 980
 981         pinctrl_ndcd2_default: ndcd2_default {
 982                 function = "NDCD2";
 983                 groups = "NDCD2";
 984         };
 985
 986         pinctrl_ndcd3_default: ndcd3_default {
 987                 function = "NDCD3";
 988                 groups = "NDCD3";
 989         };
 990
 991         pinctrl_ndcd4_default: ndcd4_default {
 992                 function = "NDCD4";
 993                 groups = "NDCD4";
 994         };
 995
 996         pinctrl_ndsr1_default: ndsr1_default {
 997                 function = "NDSR1";
 998                 groups = "NDSR1";
 999         };
1000
1001         pinctrl_ndsr2_default: ndsr2_default {
1002                 function = "NDSR2";
1003                 groups = "NDSR2";
1004         };
1005
1006         pinctrl_ndsr3_default: ndsr3_default {
1007                 function = "NDSR3";
1008                 groups = "NDSR3";
1009         };
1010
1011         pinctrl_ndsr4_default: ndsr4_default {
1012                 function = "NDSR4";
1013                 groups = "NDSR4";
1014         };
1015
1016         pinctrl_ndtr1_default: ndtr1_default {
1017                 function = "NDTR1";
1018                 groups = "NDTR1";
1019         };
1020
1021         pinctrl_ndtr2_default: ndtr2_default {
1022                 function = "NDTR2";
1023                 groups = "NDTR2";
1024         };
1025
1026         pinctrl_ndtr3_default: ndtr3_default {
1027                 function = "NDTR3";
1028                 groups = "NDTR3";
1029         };
1030
1031         pinctrl_ndtr4_default: ndtr4_default {
1032                 function = "NDTR4";
1033                 groups = "NDTR4";
1034         };
1035
1036         pinctrl_ndts4_default: ndts4_default {
1037                 function = "NDTS4";
1038                 groups = "NDTS4";
1039         };
1040
1041         pinctrl_nri1_default: nri1_default {
1042                 function = "NRI1";
1043                 groups = "NRI1";
1044         };
1045
1046         pinctrl_nri2_default: nri2_default {
1047                 function = "NRI2";
1048                 groups = "NRI2";
1049         };
1050
1051         pinctrl_nri3_default: nri3_default {
1052                 function = "NRI3";
1053                 groups = "NRI3";
1054         };
1055
1056         pinctrl_nri4_default: nri4_default {
1057                 function = "NRI4";
1058                 groups = "NRI4";
1059         };
1060
1061         pinctrl_nrts1_default: nrts1_default {
1062                 function = "NRTS1";
1063                 groups = "NRTS1";
1064         };
1065
1066         pinctrl_nrts2_default: nrts2_default {
1067                 function = "NRTS2";
1068                 groups = "NRTS2";
1069         };
1070
1071         pinctrl_nrts3_default: nrts3_default {
1072                 function = "NRTS3";
1073                 groups = "NRTS3";
1074         };
1075
1076         pinctrl_oscclk_default: oscclk_default {
1077                 function = "OSCCLK";
1078                 groups = "OSCCLK";
1079         };
1080
1081         pinctrl_pwm0_default: pwm0_default {
1082                 function = "PWM0";
1083                 groups = "PWM0";
1084         };
1085
1086         pinctrl_pwm1_default: pwm1_default {
1087                 function = "PWM1";
1088                 groups = "PWM1";
1089         };
1090
1091         pinctrl_pwm2_default: pwm2_default {
1092                 function = "PWM2";
1093                 groups = "PWM2";
1094         };
1095
1096         pinctrl_pwm3_default: pwm3_default {
1097                 function = "PWM3";
1098                 groups = "PWM3";
1099         };
1100
1101         pinctrl_pwm4_default: pwm4_default {
1102                 function = "PWM4";
1103                 groups = "PWM4";
1104         };
1105
1106         pinctrl_pwm5_default: pwm5_default {
1107                 function = "PWM5";
1108                 groups = "PWM5";
1109         };
1110
1111         pinctrl_pwm6_default: pwm6_default {
1112                 function = "PWM6";
1113                 groups = "PWM6";
1114         };
1115
1116         pinctrl_pwm7_default: pwm7_default {
1117                 function = "PWM7";
1118                 groups = "PWM7";
1119         };
1120
1121         pinctrl_rgmii1_default: rgmii1_default {
1122                 function = "RGMII1";
1123                 groups = "RGMII1";
1124         };
1125
1126         pinctrl_rgmii2_default: rgmii2_default {
1127                 function = "RGMII2";
1128                 groups = "RGMII2";
1129         };
1130
1131         pinctrl_rmii1_default: rmii1_default {
1132                 function = "RMII1";
1133                 groups = "RMII1";
1134         };
1135
1136         pinctrl_rmii2_default: rmii2_default {
1137                 function = "RMII2";
1138                 groups = "RMII2";
1139         };
1140
1141         pinctrl_rom16_default: rom16_default {
1142                 function = "ROM16";
1143                 groups = "ROM16";
1144         };
1145
1146         pinctrl_rom8_default: rom8_default {
1147                 function = "ROM8";
1148                 groups = "ROM8";
1149         };
1150
1151         pinctrl_romcs1_default: romcs1_default {
1152                 function = "ROMCS1";
1153                 groups = "ROMCS1";
1154         };
1155
1156         pinctrl_romcs2_default: romcs2_default {
1157                 function = "ROMCS2";
1158                 groups = "ROMCS2";
1159         };
1160
1161         pinctrl_romcs3_default: romcs3_default {
1162                 function = "ROMCS3";
1163                 groups = "ROMCS3";
1164         };
1165
1166         pinctrl_romcs4_default: romcs4_default {
1167                 function = "ROMCS4";
1168                 groups = "ROMCS4";
1169         };
1170
1171         pinctrl_rxd1_default: rxd1_default {
1172                 function = "RXD1";
1173                 groups = "RXD1";
1174         };
1175
1176         pinctrl_rxd2_default: rxd2_default {
1177                 function = "RXD2";
1178                 groups = "RXD2";
1179         };
1180
1181         pinctrl_rxd3_default: rxd3_default {
1182                 function = "RXD3";
1183                 groups = "RXD3";
1184         };
1185
1186         pinctrl_rxd4_default: rxd4_default {
1187                 function = "RXD4";
1188                 groups = "RXD4";
1189         };
1190
1191         pinctrl_salt1_default: salt1_default {
1192                 function = "SALT1";
1193                 groups = "SALT1";
1194         };
1195
1196         pinctrl_salt2_default: salt2_default {
1197                 function = "SALT2";
1198                 groups = "SALT2";
1199         };
1200
1201         pinctrl_salt3_default: salt3_default {
1202                 function = "SALT3";
1203                 groups = "SALT3";
1204         };
1205
1206         pinctrl_salt4_default: salt4_default {
1207                 function = "SALT4";
1208                 groups = "SALT4";
1209         };
1210
1211         pinctrl_sd1_default: sd1_default {
1212                 function = "SD1";
1213                 groups = "SD1";
1214         };
1215
1216         pinctrl_sd2_default: sd2_default {
1217                 function = "SD2";
1218                 groups = "SD2";
1219         };
1220
1221         pinctrl_sgpmck_default: sgpmck_default {
1222                 function = "SGPMCK";
1223                 groups = "SGPMCK";
1224         };
1225
1226         pinctrl_sgpmi_default: sgpmi_default {
1227                 function = "SGPMI";
1228                 groups = "SGPMI";
1229         };
1230
1231         pinctrl_sgpmld_default: sgpmld_default {
1232                 function = "SGPMLD";
1233                 groups = "SGPMLD";
1234         };
1235
1236         pinctrl_sgpmo_default: sgpmo_default {
1237                 function = "SGPMO";
1238                 groups = "SGPMO";
1239         };
1240
1241         pinctrl_sgpsck_default: sgpsck_default {
1242                 function = "SGPSCK";
1243                 groups = "SGPSCK";
1244         };
1245
1246         pinctrl_sgpsi0_default: sgpsi0_default {
1247                 function = "SGPSI0";
1248                 groups = "SGPSI0";
1249         };
1250
1251         pinctrl_sgpsi1_default: sgpsi1_default {
1252                 function = "SGPSI1";
1253                 groups = "SGPSI1";
1254         };
1255
1256         pinctrl_sgpsld_default: sgpsld_default {
1257                 function = "SGPSLD";
1258                 groups = "SGPSLD";
1259         };
1260
1261         pinctrl_sioonctrl_default: sioonctrl_default {
1262                 function = "SIOONCTRL";
1263                 groups = "SIOONCTRL";
1264         };
1265
1266         pinctrl_siopbi_default: siopbi_default {
1267                 function = "SIOPBI";
1268                 groups = "SIOPBI";
1269         };
1270
1271         pinctrl_siopbo_default: siopbo_default {
1272                 function = "SIOPBO";
1273                 groups = "SIOPBO";
1274         };
1275
1276         pinctrl_siopwreq_default: siopwreq_default {
1277                 function = "SIOPWREQ";
1278                 groups = "SIOPWREQ";
1279         };
1280
1281         pinctrl_siopwrgd_default: siopwrgd_default {
1282                 function = "SIOPWRGD";
1283                 groups = "SIOPWRGD";
1284         };
1285
1286         pinctrl_sios3_default: sios3_default {
1287                 function = "SIOS3";
1288                 groups = "SIOS3";
1289         };
1290
1291         pinctrl_sios5_default: sios5_default {
1292                 function = "SIOS5";
1293                 groups = "SIOS5";
1294         };
1295
1296         pinctrl_siosci_default: siosci_default {
1297                 function = "SIOSCI";
1298                 groups = "SIOSCI";
1299         };
1300
1301         pinctrl_spi1_default: spi1_default {
1302                 function = "SPI1";
1303                 groups = "SPI1";
1304         };
1305
1306         pinctrl_spi1debug_default: spi1debug_default {
1307                 function = "SPI1DEBUG";
1308                 groups = "SPI1DEBUG";
1309         };
1310
1311         pinctrl_spi1passthru_default: spi1passthru_default {
1312                 function = "SPI1PASSTHRU";
1313                 groups = "SPI1PASSTHRU";
1314         };
1315
1316         pinctrl_spics1_default: spics1_default {
1317                 function = "SPICS1";
1318                 groups = "SPICS1";
1319         };
1320
1321         pinctrl_timer3_default: timer3_default {
1322                 function = "TIMER3";
1323                 groups = "TIMER3";
1324         };
1325
1326         pinctrl_timer4_default: timer4_default {
1327                 function = "TIMER4";
1328                 groups = "TIMER4";
1329         };
1330
1331         pinctrl_timer5_default: timer5_default {
1332                 function = "TIMER5";
1333                 groups = "TIMER5";
1334         };
1335
1336         pinctrl_timer6_default: timer6_default {
1337                 function = "TIMER6";
1338                 groups = "TIMER6";
1339         };
1340
1341         pinctrl_timer7_default: timer7_default {
1342                 function = "TIMER7";
1343                 groups = "TIMER7";
1344         };
1345
1346         pinctrl_timer8_default: timer8_default {
1347                 function = "TIMER8";
1348                 groups = "TIMER8";
1349         };
1350
1351         pinctrl_txd1_default: txd1_default {
1352                 function = "TXD1";
1353                 groups = "TXD1";
1354         };
1355
1356         pinctrl_txd2_default: txd2_default {
1357                 function = "TXD2";
1358                 groups = "TXD2";
1359         };
1360
1361         pinctrl_txd3_default: txd3_default {
1362                 function = "TXD3";
1363                 groups = "TXD3";
1364         };
1365
1366         pinctrl_txd4_default: txd4_default {
1367                 function = "TXD4";
1368                 groups = "TXD4";
1369         };
1370
1371         pinctrl_uart6_default: uart6_default {
1372                 function = "UART6";
1373                 groups = "UART6";
1374         };
1375
1376         pinctrl_usbcki_default: usbcki_default {
1377                 function = "USBCKI";
1378                 groups = "USBCKI";
1379         };
1380
1381         pinctrl_usb2h_default: usb2h_default {
1382                 function = "USB2H1";
1383                 groups = "USB2H1";
1384         };
1385
1386         pinctrl_usb2d_default: usb2d_default {
1387                 function = "USB2D1";
1388                 groups = "USB2D1";
1389         };
1390
1391         pinctrl_vgabios_rom_default: vgabios_rom_default {
1392                 function = "VGABIOS_ROM";
1393                 groups = "VGABIOS_ROM";
1394         };
1395
1396         pinctrl_vgahs_default: vgahs_default {
1397                 function = "VGAHS";
1398                 groups = "VGAHS";
1399         };
1400
1401         pinctrl_vgavs_default: vgavs_default {
1402                 function = "VGAVS";
1403                 groups = "VGAVS";
1404         };
1405
1406         pinctrl_vpi18_default: vpi18_default {
1407                 function = "VPI18";
1408                 groups = "VPI18";
1409         };
1410
1411         pinctrl_vpi24_default: vpi24_default {
1412                 function = "VPI24";
1413                 groups = "VPI24";
1414         };
1415
1416         pinctrl_vpi30_default: vpi30_default {
1417                 function = "VPI30";
1418                 groups = "VPI30";
1419         };
1420
1421         pinctrl_vpo12_default: vpo12_default {
1422                 function = "VPO12";
1423                 groups = "VPO12";
1424         };
1425
1426         pinctrl_vpo24_default: vpo24_default {
1427                 function = "VPO24";
1428                 groups = "VPO24";
1429         };
1430
1431         pinctrl_wdtrst1_default: wdtrst1_default {
1432                 function = "WDTRST1";
1433                 groups = "WDTRST1";
1434         };
1435
1436         pinctrl_wdtrst2_default: wdtrst2_default {
1437                 function = "WDTRST2";
1438                 groups = "WDTRST2";
1439         };
1440 };