arch/arm/boot/dts/armada-385-turris-omnia.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Device Tree file for the Turris Omnia
   4  *
   5  * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
   6  * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
   7  *
   8  * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
   9  */
  10
  11 /dts-v1/;
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/leds/common.h>
  16 #include "armada-385.dtsi"
  17
  18 / {
  19         model = "Turris Omnia";
  20         compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
  21
  22         chosen {
  23                 stdout-path = &uart0;
  24         };
  25
  26         memory {
  27                 device_type = "memory";
  28                 reg = <0x00000000 0x40000000>; /* 1024 MB */
  29         };
  30
  31         soc {
  32                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  33                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  34                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
  35                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
  36
  37                 internal-regs {
  38
  39                         /* USB part of the PCIe2/USB 2.0 port */
  40                         usb@58000 {
  41                                 status = "okay";
  42                         };
  43
  44                         sata@a8000 {
  45                                 status = "okay";
  46                         };
  47
  48                         sdhci@d8000 {
  49                                 pinctrl-names = "default";
  50                                 pinctrl-0 = <&sdhci_pins>;
  51                                 status = "okay";
  52
  53                                 bus-width = <8>;
  54                                 no-1-8-v;
  55                                 non-removable;
  56                         };
  57
  58                         usb3@f0000 {
  59                                 status = "okay";
  60                         };
  61
  62                         usb3@f8000 {
  63                                 status = "okay";
  64                         };
  65                 };
  66
  67                 pcie {
  68                         status = "okay";
  69
  70                         pcie@1,0 {
  71                                 /* Port 0, Lane 0 */
  72                                 status = "okay";
  73                         };
  74
  75                         pcie@2,0 {
  76                                 /* Port 1, Lane 0 */
  77                                 status = "okay";
  78                         };
  79
  80                         pcie@3,0 {
  81                                 /* Port 2, Lane 0 */
  82                                 status = "okay";
  83                         };
  84                 };
  85         };
  86
  87         sfp: sfp {
  88                 compatible = "sff,sfp";
  89                 i2c-bus = <&sfp_i2c>;
  90                 tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
  91                 tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
  92                 rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
  93                 los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
  94                 mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
  95                 maximum-power-milliwatt = <3000>;
  96
  97                 /*
  98                  * For now this has to be enabled at boot time by U-Boot when
  99                  * a SFP module is present. Read more in the comment in the
 100                  * eth2 node below.
 101                  */
 102                 status = "disabled";
 103         };
 104 };
 105
 106 &bm {
 107         status = "okay";
 108 };
 109
 110 &bm_bppi {
 111         status = "okay";
 112 };
 113
 114 /* Connected to 88E6176 switch, port 6 */
 115 &eth0 {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&ge0_rgmii_pins>;
 118         status = "okay";
 119         phy-mode = "rgmii";
 120         buffer-manager = <&bm>;
 121         bm,pool-long = <0>;
 122         bm,pool-short = <3>;
 123
 124         fixed-link {
 125                 speed = <1000>;
 126                 full-duplex;
 127         };
 128 };
 129
 130 /* Connected to 88E6176 switch, port 5 */
 131 &eth1 {
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&ge1_rgmii_pins>;
 134         status = "okay";
 135         phy-mode = "rgmii";
 136         buffer-manager = <&bm>;
 137         bm,pool-long = <1>;
 138         bm,pool-short = <3>;
 139
 140         fixed-link {
 141                 speed = <1000>;
 142                 full-duplex;
 143         };
 144 };
 145
 146 /* WAN port */
 147 &eth2 {
 148         /*
 149          * eth2 is connected via a multiplexor to both the SFP cage and to
 150          * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
 151          * a SFP module is present, as determined by the mode-def0 GPIO.
 152          *
 153          * Until kernel supports this configuration properly, in case SFP module
 154          * is present, U-Boot has to enable the sfp node above, remove phy
 155          * handle and add managed = "in-band-status" property.
 156          */
 157         status = "okay";
 158         phy-mode = "sgmii";
 159         phy-handle = <&phy1>;
 160         phys = <&comphy5 2>;
 161         sfp = <&sfp>;
 162         buffer-manager = <&bm>;
 163         bm,pool-long = <2>;
 164         bm,pool-short = <3>;
 165 };
 166
 167 &i2c0 {
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&i2c0_pins>;
 170         status = "okay";
 171
 172         i2cmux@70 {
 173                 compatible = "nxp,pca9547";
 174                 #address-cells = <1>;
 175                 #size-cells = <0>;
 176                 reg = <0x70>;
 177
 178                 i2c@0 {
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         reg = <0>;
 182
 183                         /* STM32F0 command interface at address 0x2a */
 184
 185                         led-controller@2b {
 186                                 compatible = "cznic,turris-omnia-leds";
 187                                 reg = <0x2b>;
 188                                 #address-cells = <1>;
 189                                 #size-cells = <0>;
 190
 191                                 /*
 192                                  * LEDs are controlled by MCU (STM32F0) at
 193                                  * address 0x2b.
 194                                  *
 195                                  * The driver does not support HW control mode
 196                                  * for the LEDs yet. Disable the LEDs for now.
 197                                  *
 198                                  * Also LED functions are not stable yet:
 199                                  * - there are 3 LEDs connected via MCU to PCIe
 200                                  *   ports. One of these ports supports mSATA.
 201                                  *   There is no mSATA nor PCIe function.
 202                                  *   For now we use LED_FUNCTION_WLAN, since
 203                                  *   in most cases users have wifi cards in
 204                                  *   these slots
 205                                  * - there are 2 LEDs dedicated for user: A and
 206                                  *   B. Again there is no such function defined.
 207                                  *   For now we use LED_FUNCTION_INDICATOR
 208                                  */
 209                                 status = "disabled";
 210
 211                                 multi-led@0 {
 212                                         reg = <0x0>;
 213                                         color = <LED_COLOR_ID_RGB>;
 214                                         function = LED_FUNCTION_INDICATOR;
 215                                         function-enumerator = <2>;
 216                                 };
 217
 218                                 multi-led@1 {
 219                                         reg = <0x1>;
 220                                         color = <LED_COLOR_ID_RGB>;
 221                                         function = LED_FUNCTION_INDICATOR;
 222                                         function-enumerator = <1>;
 223                                 };
 224
 225                                 multi-led@2 {
 226                                         reg = <0x2>;
 227                                         color = <LED_COLOR_ID_RGB>;
 228                                         function = LED_FUNCTION_WLAN;
 229                                         function-enumerator = <3>;
 230                                 };
 231
 232                                 multi-led@3 {
 233                                         reg = <0x3>;
 234                                         color = <LED_COLOR_ID_RGB>;
 235                                         function = LED_FUNCTION_WLAN;
 236                                         function-enumerator = <2>;
 237                                 };
 238
 239                                 multi-led@4 {
 240                                         reg = <0x4>;
 241                                         color = <LED_COLOR_ID_RGB>;
 242                                         function = LED_FUNCTION_WLAN;
 243                                         function-enumerator = <1>;
 244                                 };
 245
 246                                 multi-led@5 {
 247                                         reg = <0x5>;
 248                                         color = <LED_COLOR_ID_RGB>;
 249                                         function = LED_FUNCTION_WAN;
 250                                 };
 251
 252                                 multi-led@6 {
 253                                         reg = <0x6>;
 254                                         color = <LED_COLOR_ID_RGB>;
 255                                         function = LED_FUNCTION_LAN;
 256                                         function-enumerator = <4>;
 257                                 };
 258
 259                                 multi-led@7 {
 260                                         reg = <0x7>;
 261                                         color = <LED_COLOR_ID_RGB>;
 262                                         function = LED_FUNCTION_LAN;
 263                                         function-enumerator = <3>;
 264                                 };
 265
 266                                 multi-led@8 {
 267                                         reg = <0x8>;
 268                                         color = <LED_COLOR_ID_RGB>;
 269                                         function = LED_FUNCTION_LAN;
 270                                         function-enumerator = <2>;
 271                                 };
 272
 273                                 multi-led@9 {
 274                                         reg = <0x9>;
 275                                         color = <LED_COLOR_ID_RGB>;
 276                                         function = LED_FUNCTION_LAN;
 277                                         function-enumerator = <1>;
 278                                 };
 279
 280                                 multi-led@a {
 281                                         reg = <0xa>;
 282                                         color = <LED_COLOR_ID_RGB>;
 283                                         function = LED_FUNCTION_LAN;
 284                                         function-enumerator = <0>;
 285                                 };
 286
 287                                 multi-led@b {
 288                                         reg = <0xb>;
 289                                         color = <LED_COLOR_ID_RGB>;
 290                                         function = LED_FUNCTION_POWER;
 291                                 };
 292                         };
 293
 294                         eeprom@54 {
 295                                 compatible = "atmel,24c64";
 296                                 reg = <0x54>;
 297
 298                                 /* The EEPROM contains data for bootloader.
 299                                  * Contents:
 300                                  *      struct omnia_eeprom {
 301                                  *              u32 magic; (=0x0341a034 in LE)
 302                                  *              u32 ramsize; (in GiB)
 303                                  *              char regdomain[4];
 304                                  *              u32 crc32;
 305                                  *      };
 306                                  */
 307                         };
 308                 };
 309
 310                 i2c@1 {
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         reg = <1>;
 314
 315                         /* routed to PCIe0/mSATA connector (CN7A) */
 316                 };
 317
 318                 i2c@2 {
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321                         reg = <2>;
 322
 323                         /* routed to PCIe1/USB2 connector (CN61A) */
 324                 };
 325
 326                 i2c@3 {
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                         reg = <3>;
 330
 331                         /* routed to PCIe2 connector (CN62A) */
 332                 };
 333
 334                 sfp_i2c: i2c@4 {
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         reg = <4>;
 338
 339                         /* routed to SFP+ */
 340                 };
 341
 342                 i2c@5 {
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         reg = <5>;
 346
 347                         /* ATSHA204A at address 0x64 */
 348                 };
 349
 350                 i2c@6 {
 351                         #address-cells = <1>;
 352                         #size-cells = <0>;
 353                         reg = <6>;
 354
 355                         /* exposed on pin header */
 356                 };
 357
 358                 i2c@7 {
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         reg = <7>;
 362
 363                         pcawan: gpio@71 {
 364                                 /*
 365                                  * GPIO expander for SFP+ signals and
 366                                  * and phy irq
 367                                  */
 368                                 compatible = "nxp,pca9538";
 369                                 reg = <0x71>;
 370
 371                                 pinctrl-names = "default";
 372                                 pinctrl-0 = <&pcawan_pins>;
 373
 374                                 interrupt-parent = <&gpio1>;
 375                                 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
 376
 377                                 gpio-controller;
 378                                 #gpio-cells = <2>;
 379                         };
 380                 };
 381         };
 382 };
 383
 384 &mdio {
 385         pinctrl-names = "default";
 386         pinctrl-0 = <&mdio_pins>;
 387         status = "okay";
 388
 389         phy1: ethernet-phy@1 {
 390                 compatible = "ethernet-phy-ieee802.3-c22";
 391                 reg = <1>;
 392
 393                 /* irq is connected to &pcawan pin 7 */
 394         };
 395
 396         /* Switch MV88E6176 at address 0x10 */
 397         switch@10 {
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&swint_pins>;
 400                 compatible = "marvell,mv88e6085";
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403
 404                 dsa,member = <0 0>;
 405                 reg = <0x10>;
 406
 407                 interrupt-parent = <&gpio1>;
 408                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 409
 410                 ports {
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413
 414                         ports@0 {
 415                                 reg = <0>;
 416                                 label = "lan0";
 417                         };
 418
 419                         ports@1 {
 420                                 reg = <1>;
 421                                 label = "lan1";
 422                         };
 423
 424                         ports@2 {
 425                                 reg = <2>;
 426                                 label = "lan2";
 427                         };
 428
 429                         ports@3 {
 430                                 reg = <3>;
 431                                 label = "lan3";
 432                         };
 433
 434                         ports@4 {
 435                                 reg = <4>;
 436                                 label = "lan4";
 437                         };
 438
 439                         ports@5 {
 440                                 reg = <5>;
 441                                 label = "cpu";
 442                                 ethernet = <&eth1>;
 443                                 phy-mode = "rgmii-id";
 444
 445                                 fixed-link {
 446                                         speed = <1000>;
 447                                         full-duplex;
 448                                 };
 449                         };
 450
 451                         /* port 6 is connected to eth0 */
 452                 };
 453         };
 454 };
 455
 456 &pinctrl {
 457         pcawan_pins: pcawan-pins {
 458                 marvell,pins = "mpp46";
 459                 marvell,function = "gpio";
 460         };
 461
 462         swint_pins: swint-pins {
 463                 marvell,pins = "mpp45";
 464                 marvell,function = "gpio";
 465         };
 466
 467         spi0cs0_pins: spi0cs0-pins {
 468                 marvell,pins = "mpp25";
 469                 marvell,function = "spi0";
 470         };
 471
 472         spi0cs1_pins: spi0cs1-pins {
 473                 marvell,pins = "mpp26";
 474                 marvell,function = "spi0";
 475         };
 476 };
 477
 478 &spi0 {
 479         pinctrl-names = "default";
 480         pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
 481         status = "okay";
 482
 483         spi-nor@0 {
 484                 compatible = "spansion,s25fl164k", "jedec,spi-nor";
 485                 #address-cells = <1>;
 486                 #size-cells = <1>;
 487                 reg = <0>;
 488                 spi-max-frequency = <40000000>;
 489
 490                 partitions {
 491                         compatible = "fixed-partitions";
 492                         #address-cells = <1>;
 493                         #size-cells = <1>;
 494
 495                         partition@0 {
 496                                 reg = <0x0 0x00100000>;
 497                                 label = "U-Boot";
 498                         };
 499
 500                         partition@100000 {
 501                                 reg = <0x00100000 0x00700000>;
 502                                 label = "Rescue system";
 503                         };
 504                 };
 505         };
 506
 507         /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
 508 };
 509
 510 &uart0 {
 511         /* Pin header CN10 */
 512         pinctrl-names = "default";
 513         pinctrl-0 = <&uart0_pins>;
 514         status = "okay";
 515 };
 516
 517 &uart1 {
 518         /* Pin header CN11 */
 519         pinctrl-names = "default";
 520         pinctrl-0 = <&uart1_pins>;
 521         status = "okay";
 522 };