arch/arm/boot/dts/am33xx-clocks.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Device Tree Source for AM33xx clock data
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  */
   7 &scm_clocks {
   8         sys_clkin_ck: sys_clkin_ck@40 {
   9                 #clock-cells = <0>;
  10                 compatible = "ti,mux-clock";
  11                 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
  12                 ti,bit-shift = <22>;
  13                 reg = <0x0040>;
  14         };
  15
  16         adc_tsc_fck: adc_tsc_fck {
  17                 #clock-cells = <0>;
  18                 compatible = "fixed-factor-clock";
  19                 clocks = <&sys_clkin_ck>;
  20                 clock-mult = <1>;
  21                 clock-div = <1>;
  22         };
  23
  24         dcan0_fck: dcan0_fck {
  25                 #clock-cells = <0>;
  26                 compatible = "fixed-factor-clock";
  27                 clocks = <&sys_clkin_ck>;
  28                 clock-mult = <1>;
  29                 clock-div = <1>;
  30         };
  31
  32         dcan1_fck: dcan1_fck {
  33                 #clock-cells = <0>;
  34                 compatible = "fixed-factor-clock";
  35                 clocks = <&sys_clkin_ck>;
  36                 clock-mult = <1>;
  37                 clock-div = <1>;
  38         };
  39
  40         mcasp0_fck: mcasp0_fck {
  41                 #clock-cells = <0>;
  42                 compatible = "fixed-factor-clock";
  43                 clocks = <&sys_clkin_ck>;
  44                 clock-mult = <1>;
  45                 clock-div = <1>;
  46         };
  47
  48         mcasp1_fck: mcasp1_fck {
  49                 #clock-cells = <0>;
  50                 compatible = "fixed-factor-clock";
  51                 clocks = <&sys_clkin_ck>;
  52                 clock-mult = <1>;
  53                 clock-div = <1>;
  54         };
  55
  56         smartreflex0_fck: smartreflex0_fck {
  57                 #clock-cells = <0>;
  58                 compatible = "fixed-factor-clock";
  59                 clocks = <&sys_clkin_ck>;
  60                 clock-mult = <1>;
  61                 clock-div = <1>;
  62         };
  63
  64         smartreflex1_fck: smartreflex1_fck {
  65                 #clock-cells = <0>;
  66                 compatible = "fixed-factor-clock";
  67                 clocks = <&sys_clkin_ck>;
  68                 clock-mult = <1>;
  69                 clock-div = <1>;
  70         };
  71
  72         sha0_fck: sha0_fck {
  73                 #clock-cells = <0>;
  74                 compatible = "fixed-factor-clock";
  75                 clocks = <&sys_clkin_ck>;
  76                 clock-mult = <1>;
  77                 clock-div = <1>;
  78         };
  79
  80         aes0_fck: aes0_fck {
  81                 #clock-cells = <0>;
  82                 compatible = "fixed-factor-clock";
  83                 clocks = <&sys_clkin_ck>;
  84                 clock-mult = <1>;
  85                 clock-div = <1>;
  86         };
  87
  88         rng_fck: rng_fck {
  89                 #clock-cells = <0>;
  90                 compatible = "fixed-factor-clock";
  91                 clocks = <&sys_clkin_ck>;
  92                 clock-mult = <1>;
  93                 clock-div = <1>;
  94         };
  95
  96         ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
  97                 #clock-cells = <0>;
  98                 compatible = "ti,gate-clock";
  99                 clocks = <&l4ls_gclk>;
 100                 ti,bit-shift = <0>;
 101                 reg = <0x0664>;
 102         };
 103
 104         ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
 105                 #clock-cells = <0>;
 106                 compatible = "ti,gate-clock";
 107                 clocks = <&l4ls_gclk>;
 108                 ti,bit-shift = <1>;
 109                 reg = <0x0664>;
 110         };
 111
 112         ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
 113                 #clock-cells = <0>;
 114                 compatible = "ti,gate-clock";
 115                 clocks = <&l4ls_gclk>;
 116                 ti,bit-shift = <2>;
 117                 reg = <0x0664>;
 118         };
 119 };
 120 &prcm_clocks {
 121         clk_32768_ck: clk_32768_ck {
 122                 #clock-cells = <0>;
 123                 compatible = "fixed-clock";
 124                 clock-frequency = <32768>;
 125         };
 126
 127         clk_rc32k_ck: clk_rc32k_ck {
 128                 #clock-cells = <0>;
 129                 compatible = "fixed-clock";
 130                 clock-frequency = <32000>;
 131         };
 132
 133         virt_19200000_ck: virt_19200000_ck {
 134                 #clock-cells = <0>;
 135                 compatible = "fixed-clock";
 136                 clock-frequency = <19200000>;
 137         };
 138
 139         virt_24000000_ck: virt_24000000_ck {
 140                 #clock-cells = <0>;
 141                 compatible = "fixed-clock";
 142                 clock-frequency = <24000000>;
 143         };
 144
 145         virt_25000000_ck: virt_25000000_ck {
 146                 #clock-cells = <0>;
 147                 compatible = "fixed-clock";
 148                 clock-frequency = <25000000>;
 149         };
 150
 151         virt_26000000_ck: virt_26000000_ck {
 152                 #clock-cells = <0>;
 153                 compatible = "fixed-clock";
 154                 clock-frequency = <26000000>;
 155         };
 156
 157         tclkin_ck: tclkin_ck {
 158                 #clock-cells = <0>;
 159                 compatible = "fixed-clock";
 160                 clock-frequency = <12000000>;
 161         };
 162
 163         dpll_core_ck: dpll_core_ck@490 {
 164                 #clock-cells = <0>;
 165                 compatible = "ti,am3-dpll-core-clock";
 166                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 167                 reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
 168         };
 169
 170         dpll_core_x2_ck: dpll_core_x2_ck {
 171                 #clock-cells = <0>;
 172                 compatible = "ti,am3-dpll-x2-clock";
 173                 clocks = <&dpll_core_ck>;
 174         };
 175
 176         dpll_core_m4_ck: dpll_core_m4_ck@480 {
 177                 #clock-cells = <0>;
 178                 compatible = "ti,divider-clock";
 179                 clocks = <&dpll_core_x2_ck>;
 180                 ti,max-div = <31>;
 181                 reg = <0x0480>;
 182                 ti,index-starts-at-one;
 183         };
 184
 185         dpll_core_m5_ck: dpll_core_m5_ck@484 {
 186                 #clock-cells = <0>;
 187                 compatible = "ti,divider-clock";
 188                 clocks = <&dpll_core_x2_ck>;
 189                 ti,max-div = <31>;
 190                 reg = <0x0484>;
 191                 ti,index-starts-at-one;
 192         };
 193
 194         dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
 195                 #clock-cells = <0>;
 196                 compatible = "ti,divider-clock";
 197                 clocks = <&dpll_core_x2_ck>;
 198                 ti,max-div = <31>;
 199                 reg = <0x04d8>;
 200                 ti,index-starts-at-one;
 201         };
 202
 203         dpll_mpu_ck: dpll_mpu_ck@488 {
 204                 #clock-cells = <0>;
 205                 compatible = "ti,am3-dpll-clock";
 206                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 207                 reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
 208         };
 209
 210         dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
 211                 #clock-cells = <0>;
 212                 compatible = "ti,divider-clock";
 213                 clocks = <&dpll_mpu_ck>;
 214                 ti,max-div = <31>;
 215                 reg = <0x04a8>;
 216                 ti,index-starts-at-one;
 217         };
 218
 219         dpll_ddr_ck: dpll_ddr_ck@494 {
 220                 #clock-cells = <0>;
 221                 compatible = "ti,am3-dpll-no-gate-clock";
 222                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 223                 reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
 224         };
 225
 226         dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
 227                 #clock-cells = <0>;
 228                 compatible = "ti,divider-clock";
 229                 clocks = <&dpll_ddr_ck>;
 230                 ti,max-div = <31>;
 231                 reg = <0x04a0>;
 232                 ti,index-starts-at-one;
 233         };
 234
 235         dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
 236                 #clock-cells = <0>;
 237                 compatible = "fixed-factor-clock";
 238                 clocks = <&dpll_ddr_m2_ck>;
 239                 clock-mult = <1>;
 240                 clock-div = <2>;
 241         };
 242
 243         dpll_disp_ck: dpll_disp_ck@498 {
 244                 #clock-cells = <0>;
 245                 compatible = "ti,am3-dpll-no-gate-clock";
 246                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 247                 reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
 248         };
 249
 250         dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
 251                 #clock-cells = <0>;
 252                 compatible = "ti,divider-clock";
 253                 clocks = <&dpll_disp_ck>;
 254                 ti,max-div = <31>;
 255                 reg = <0x04a4>;
 256                 ti,index-starts-at-one;
 257                 ti,set-rate-parent;
 258         };
 259
 260         dpll_per_ck: dpll_per_ck@48c {
 261                 #clock-cells = <0>;
 262                 compatible = "ti,am3-dpll-no-gate-j-type-clock";
 263                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 264                 reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
 265         };
 266
 267         dpll_per_m2_ck: dpll_per_m2_ck@4ac {
 268                 #clock-cells = <0>;
 269                 compatible = "ti,divider-clock";
 270                 clocks = <&dpll_per_ck>;
 271                 ti,max-div = <31>;
 272                 reg = <0x04ac>;
 273                 ti,index-starts-at-one;
 274         };
 275
 276         dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
 277                 #clock-cells = <0>;
 278                 compatible = "fixed-factor-clock";
 279                 clocks = <&dpll_per_m2_ck>;
 280                 clock-mult = <1>;
 281                 clock-div = <4>;
 282         };
 283
 284         dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
 285                 #clock-cells = <0>;
 286                 compatible = "fixed-factor-clock";
 287                 clocks = <&dpll_per_m2_ck>;
 288                 clock-mult = <1>;
 289                 clock-div = <4>;
 290         };
 291
 292         clk_24mhz: clk_24mhz {
 293                 #clock-cells = <0>;
 294                 compatible = "fixed-factor-clock";
 295                 clocks = <&dpll_per_m2_ck>;
 296                 clock-mult = <1>;
 297                 clock-div = <8>;
 298         };
 299
 300         clkdiv32k_ck: clkdiv32k_ck {
 301                 #clock-cells = <0>;
 302                 compatible = "fixed-factor-clock";
 303                 clocks = <&clk_24mhz>;
 304                 clock-mult = <1>;
 305                 clock-div = <732>;
 306         };
 307
 308         l3_gclk: l3_gclk {
 309                 #clock-cells = <0>;
 310                 compatible = "fixed-factor-clock";
 311                 clocks = <&dpll_core_m4_ck>;
 312                 clock-mult = <1>;
 313                 clock-div = <1>;
 314         };
 315
 316         pruss_ocp_gclk: pruss_ocp_gclk@530 {
 317                 #clock-cells = <0>;
 318                 compatible = "ti,mux-clock";
 319                 clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
 320                 reg = <0x0530>;
 321         };
 322
 323         mmu_fck: mmu_fck@914 {
 324                 #clock-cells = <0>;
 325                 compatible = "ti,gate-clock";
 326                 clocks = <&dpll_core_m4_ck>;
 327                 ti,bit-shift = <1>;
 328                 reg = <0x0914>;
 329         };
 330
 331         timer1_fck: timer1_fck@528 {
 332                 #clock-cells = <0>;
 333                 compatible = "ti,mux-clock";
 334                 clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
 335                 reg = <0x0528>;
 336         };
 337
 338         timer2_fck: timer2_fck@508 {
 339                 #clock-cells = <0>;
 340                 compatible = "ti,mux-clock";
 341                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 342                 reg = <0x0508>;
 343         };
 344
 345         timer3_fck: timer3_fck@50c {
 346                 #clock-cells = <0>;
 347                 compatible = "ti,mux-clock";
 348                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 349                 reg = <0x050c>;
 350         };
 351
 352         timer4_fck: timer4_fck@510 {
 353                 #clock-cells = <0>;
 354                 compatible = "ti,mux-clock";
 355                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 356                 reg = <0x0510>;
 357         };
 358
 359         timer5_fck: timer5_fck@518 {
 360                 #clock-cells = <0>;
 361                 compatible = "ti,mux-clock";
 362                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 363                 reg = <0x0518>;
 364         };
 365
 366         timer6_fck: timer6_fck@51c {
 367                 #clock-cells = <0>;
 368                 compatible = "ti,mux-clock";
 369                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 370                 reg = <0x051c>;
 371         };
 372
 373         timer7_fck: timer7_fck@504 {
 374                 #clock-cells = <0>;
 375                 compatible = "ti,mux-clock";
 376                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 377                 reg = <0x0504>;
 378         };
 379
 380         usbotg_fck: usbotg_fck@47c {
 381                 #clock-cells = <0>;
 382                 compatible = "ti,gate-clock";
 383                 clocks = <&dpll_per_ck>;
 384                 ti,bit-shift = <8>;
 385                 reg = <0x047c>;
 386         };
 387
 388         dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
 389                 #clock-cells = <0>;
 390                 compatible = "fixed-factor-clock";
 391                 clocks = <&dpll_core_m4_ck>;
 392                 clock-mult = <1>;
 393                 clock-div = <2>;
 394         };
 395
 396         ieee5000_fck: ieee5000_fck@e4 {
 397                 #clock-cells = <0>;
 398                 compatible = "ti,gate-clock";
 399                 clocks = <&dpll_core_m4_div2_ck>;
 400                 ti,bit-shift = <1>;
 401                 reg = <0x00e4>;
 402         };
 403
 404         wdt1_fck: wdt1_fck@538 {
 405                 #clock-cells = <0>;
 406                 compatible = "ti,mux-clock";
 407                 clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 408                 reg = <0x0538>;
 409         };
 410
 411         l4_rtc_gclk: l4_rtc_gclk {
 412                 #clock-cells = <0>;
 413                 compatible = "fixed-factor-clock";
 414                 clocks = <&dpll_core_m4_ck>;
 415                 clock-mult = <1>;
 416                 clock-div = <2>;
 417         };
 418
 419         l4hs_gclk: l4hs_gclk {
 420                 #clock-cells = <0>;
 421                 compatible = "fixed-factor-clock";
 422                 clocks = <&dpll_core_m4_ck>;
 423                 clock-mult = <1>;
 424                 clock-div = <1>;
 425         };
 426
 427         l3s_gclk: l3s_gclk {
 428                 #clock-cells = <0>;
 429                 compatible = "fixed-factor-clock";
 430                 clocks = <&dpll_core_m4_div2_ck>;
 431                 clock-mult = <1>;
 432                 clock-div = <1>;
 433         };
 434
 435         l4fw_gclk: l4fw_gclk {
 436                 #clock-cells = <0>;
 437                 compatible = "fixed-factor-clock";
 438                 clocks = <&dpll_core_m4_div2_ck>;
 439                 clock-mult = <1>;
 440                 clock-div = <1>;
 441         };
 442
 443         l4ls_gclk: l4ls_gclk {
 444                 #clock-cells = <0>;
 445                 compatible = "fixed-factor-clock";
 446                 clocks = <&dpll_core_m4_div2_ck>;
 447                 clock-mult = <1>;
 448                 clock-div = <1>;
 449         };
 450
 451         sysclk_div_ck: sysclk_div_ck {
 452                 #clock-cells = <0>;
 453                 compatible = "fixed-factor-clock";
 454                 clocks = <&dpll_core_m4_ck>;
 455                 clock-mult = <1>;
 456                 clock-div = <1>;
 457         };
 458
 459         cpsw_125mhz_gclk: cpsw_125mhz_gclk {
 460                 #clock-cells = <0>;
 461                 compatible = "fixed-factor-clock";
 462                 clocks = <&dpll_core_m5_ck>;
 463                 clock-mult = <1>;
 464                 clock-div = <2>;
 465         };
 466
 467         cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
 468                 #clock-cells = <0>;
 469                 compatible = "ti,mux-clock";
 470                 clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
 471                 reg = <0x0520>;
 472         };
 473
 474         gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
 475                 #clock-cells = <0>;
 476                 compatible = "ti,mux-clock";
 477                 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 478                 reg = <0x053c>;
 479         };
 480
 481         lcd_gclk: lcd_gclk@534 {
 482                 #clock-cells = <0>;
 483                 compatible = "ti,mux-clock";
 484                 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
 485                 reg = <0x0534>;
 486                 ti,set-rate-parent;
 487         };
 488
 489         mmc_clk: mmc_clk {
 490                 #clock-cells = <0>;
 491                 compatible = "fixed-factor-clock";
 492                 clocks = <&dpll_per_m2_ck>;
 493                 clock-mult = <1>;
 494                 clock-div = <2>;
 495         };
 496
 497         gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
 498                 #clock-cells = <0>;
 499                 compatible = "ti,mux-clock";
 500                 clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
 501                 ti,bit-shift = <1>;
 502                 reg = <0x052c>;
 503         };
 504
 505         gfx_fck_div_ck: gfx_fck_div_ck@52c {
 506                 #clock-cells = <0>;
 507                 compatible = "ti,divider-clock";
 508                 clocks = <&gfx_fclk_clksel_ck>;
 509                 reg = <0x052c>;
 510                 ti,max-div = <2>;
 511         };
 512
 513         sysclkout_pre_ck: sysclkout_pre_ck@700 {
 514                 #clock-cells = <0>;
 515                 compatible = "ti,mux-clock";
 516                 clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
 517                 reg = <0x0700>;
 518         };
 519
 520         clkout2_div_ck: clkout2_div_ck@700 {
 521                 #clock-cells = <0>;
 522                 compatible = "ti,divider-clock";
 523                 clocks = <&sysclkout_pre_ck>;
 524                 ti,bit-shift = <3>;
 525                 ti,max-div = <8>;
 526                 reg = <0x0700>;
 527         };
 528
 529         clkout2_ck: clkout2_ck@700 {
 530                 #clock-cells = <0>;
 531                 compatible = "ti,gate-clock";
 532                 clocks = <&clkout2_div_ck>;
 533                 ti,bit-shift = <7>;
 534                 reg = <0x0700>;
 535         };
 536 };
 537
 538 &prcm {
 539         per_cm: per-cm@0 {
 540                 compatible = "ti,omap4-cm";
 541                 reg = <0x0 0x400>;
 542                 #address-cells = <1>;
 543                 #size-cells = <1>;
 544                 ranges = <0 0x0 0x400>;
 545
 546                 l4ls_clkctrl: l4ls-clkctrl@38 {
 547                         compatible = "ti,clkctrl";
 548                         reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
 549                         #clock-cells = <2>;
 550                 };
 551
 552                 l3s_clkctrl: l3s-clkctrl@1c {
 553                         compatible = "ti,clkctrl";
 554                         reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
 555                         #clock-cells = <2>;
 556                 };
 557
 558                 l3_clkctrl: l3-clkctrl@24 {
 559                         compatible = "ti,clkctrl";
 560                         reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
 561                         #clock-cells = <2>;
 562                 };
 563
 564                 l4hs_clkctrl: l4hs-clkctrl@120 {
 565                         compatible = "ti,clkctrl";
 566                         reg = <0x120 0x4>;
 567                         #clock-cells = <2>;
 568                 };
 569
 570                 pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
 571                         compatible = "ti,clkctrl";
 572                         reg = <0xe8 0x4>;
 573                         #clock-cells = <2>;
 574                 };
 575
 576                 cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
 577                         compatible = "ti,clkctrl";
 578                         reg = <0x0 0x18>;
 579                         #clock-cells = <2>;
 580                 };
 581
 582                 lcdc_clkctrl: lcdc-clkctrl@18 {
 583                         compatible = "ti,clkctrl";
 584                         reg = <0x18 0x4>;
 585                         #clock-cells = <2>;
 586                 };
 587
 588                 clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
 589                         compatible = "ti,clkctrl";
 590                         reg = <0x14c 0x4>;
 591                         #clock-cells = <2>;
 592                 };
 593         };
 594
 595         wkup_cm: wkup-cm@400 {
 596                 compatible = "ti,omap4-cm";
 597                 reg = <0x400 0x100>;
 598                 #address-cells = <1>;
 599                 #size-cells = <1>;
 600                 ranges = <0 0x400 0x100>;
 601
 602                 l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
 603                         compatible = "ti,clkctrl";
 604                         reg = <0x0 0x10>, <0xb4 0x24>;
 605                         #clock-cells = <2>;
 606                 };
 607
 608                 l3_aon_clkctrl: l3-aon-clkctrl@14 {
 609                         compatible = "ti,clkctrl";
 610                         reg = <0x14 0x4>;
 611                         #clock-cells = <2>;
 612                 };
 613
 614                 l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
 615                         compatible = "ti,clkctrl";
 616                         reg = <0xb0 0x4>;
 617                         #clock-cells = <2>;
 618                 };
 619         };
 620
 621         mpu_cm: mpu-cm@600 {
 622                 compatible = "ti,omap4-cm";
 623                 reg = <0x600 0x100>;
 624                 #address-cells = <1>;
 625                 #size-cells = <1>;
 626                 ranges = <0 0x600 0x100>;
 627
 628                 mpu_clkctrl: mpu-clkctrl@0 {
 629                         compatible = "ti,clkctrl";
 630                         reg = <0x0 0x8>;
 631                         #clock-cells = <2>;
 632                 };
 633         };
 634
 635         l4_rtc_cm: l4-rtc-cm@800 {
 636                 compatible = "ti,omap4-cm";
 637                 reg = <0x800 0x100>;
 638                 #address-cells = <1>;
 639                 #size-cells = <1>;
 640                 ranges = <0 0x800 0x100>;
 641
 642                 l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
 643                         compatible = "ti,clkctrl";
 644                         reg = <0x0 0x4>;
 645                         #clock-cells = <2>;
 646                 };
 647         };
 648
 649         gfx_l3_cm: gfx-l3-cm@900 {
 650                 compatible = "ti,omap4-cm";
 651                 reg = <0x900 0x100>;
 652                 #address-cells = <1>;
 653                 #size-cells = <1>;
 654                 ranges = <0 0x900 0x100>;
 655
 656                 gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
 657                         compatible = "ti,clkctrl";
 658                         reg = <0x0 0x8>;
 659                         #clock-cells = <2>;
 660                 };
 661         };
 662
 663         l4_cefuse_cm: l4-cefuse-cm@a00 {
 664                 compatible = "ti,omap4-cm";
 665                 reg = <0xa00 0x100>;
 666                 #address-cells = <1>;
 667                 #size-cells = <1>;
 668                 ranges = <0 0xa00 0x100>;
 669
 670                 l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
 671                         compatible = "ti,clkctrl";
 672                         reg = <0x0 0x24>;
 673                         #clock-cells = <2>;
 674                 };
 675         };
 676 };