arch/arm/boot/dts/am335x-sl50.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/
   4  */
   5 /dts-v1/;
   6
   7 #include "am33xx.dtsi"
   8 #include <dt-bindings/pwm/pwm.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10
  11 / {
  12         model = "Toby Churchill SL50 Series";
  13         compatible = "tcl,am335x-sl50", "ti,am33xx";
  14
  15         cpus {
  16                 cpu@0 {
  17                         cpu0-supply = <&dcdc2_reg>;
  18                 };
  19         };
  20
  21         memory@80000000 {
  22                 device_type = "memory";
  23                 reg = <0x80000000 0x20000000>; /* 512 MB */
  24         };
  25
  26         chosen {
  27                 stdout-path = &uart0;
  28         };
  29
  30         leds {
  31                 compatible = "gpio-leds";
  32                 pinctrl-names = "default";
  33                 pinctrl-0 = <&led_pins>;
  34
  35                 led0 {
  36                         label = "sl50:red:usr0";
  37                         gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
  38                         default-state = "off";
  39                 };
  40
  41                 led1 {
  42                         label = "sl50:green:usr1";
  43                         gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
  44                         default-state = "off";
  45                 };
  46
  47                 led2 {
  48                         label = "sl50:red:usr2";
  49                         gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
  50                         default-state = "off";
  51                 };
  52
  53                 led3 {
  54                         label = "sl50:green:usr3";
  55                         gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
  56                         default-state = "off";
  57                 };
  58         };
  59
  60         backlight0: disp0 {
  61                 compatible = "pwm-backlight";
  62                 pinctrl-names = "default";
  63                 pinctrl-0 = <&backlight0_pins>;
  64                 pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>;
  65                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  66                                      10 11 12 13 14 15 16 17 18 19
  67                                      20 21 22 23 24 25 26 27 28 29
  68                                      30 31 32 33 34 35 36 37 38 39
  69                                      40 41 42 43 44 45 46 47 48 49
  70                                      50 51 52 53 54 55 56 57 58 59
  71                                      60 61 62 63 64 65 66 67 68 69
  72                                      70 71 72 73 74 75 76 77 78 79
  73                                      80 81 82 83 84 85 86 87 88 89
  74                                      90 91 92 93 94 95 96 97 98 99
  75                                     100>;
  76                 default-brightness-level = <50>;
  77                 enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
  78                 power-supply = <&vdd_sys_reg>;
  79         };
  80
  81         backlight1: disp1 {
  82                 compatible = "pwm-backlight";
  83                 pinctrl-names = "default";
  84                 pinctrl-0 = <&backlight1_pins>;
  85                 pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>;
  86                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  87                                      10 11 12 13 14 15 16 17 18 19
  88                                      20 21 22 23 24 25 26 27 28 29
  89                                      30 31 32 33 34 35 36 37 38 39
  90                                      40 41 42 43 44 45 46 47 48 49
  91                                      50 51 52 53 54 55 56 57 58 59
  92                                      60 61 62 63 64 65 66 67 68 69
  93                                      70 71 72 73 74 75 76 77 78 79
  94                                      80 81 82 83 84 85 86 87 88 89
  95                                      90 91 92 93 94 95 96 97 98 99
  96                                     100>;
  97                 default-brightness-level = <50>;
  98                 enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
  99                 power-supply = <&vdd_sys_reg>;
 100         };
 101
 102         clocks {
 103                 compatible = "simple-bus";
 104                 #address-cells = <1>;
 105                 #size-cells = <0>;
 106
 107                 /* audio external oscillator */
 108                 audio_mclk_fixed: oscillator@0 {
 109                         compatible = "fixed-clock";
 110                         #clock-cells = <0>;
 111                         clock-frequency  = <24576000>;  /* 24.576MHz */
 112                 };
 113
 114                 audio_mclk: audio_mclk_gate@0 {
 115                         compatible = "gpio-gate-clock";
 116                         #clock-cells = <0>;
 117                         pinctrl-names = "default";
 118                         pinctrl-0 = <&audio_mclk_pins>;
 119                         clocks = <&audio_mclk_fixed>;
 120                         enable-gpios = <&gpio1 27 0>;
 121                 };
 122         };
 123
 124         panel: lcd_panel {
 125                 compatible = "ti,tilcdc,panel";
 126                 pinctrl-names = "default";
 127                 pinctrl-0 = <&lcd_pins>;
 128
 129                 panel-info {
 130                         ac-bias = <255>;
 131                         ac-bias-intrpt = <0>;
 132                         dma-burst-sz = <16>;
 133                         bpp = <16>;
 134                         fdd = <0x80>;
 135                         tft-alt-mode = <0>;
 136                         mono-8bit-mode = <0>;
 137                         sync-edge = <0>;
 138                         sync-ctrl = <1>;
 139                         raster-order = <0>;
 140                         fifo-th = <0>;
 141                 };
 142
 143                 display-timings {
 144                         native-mode = <&timing0>;
 145                         timing0: 960x128 {
 146                                 clock-frequency = <18000000>;
 147                                 hactive = <960>;
 148                                 vactive = <272>;
 149
 150                                 hback-porch = <40>;
 151                                 hfront-porch = <16>;
 152                                 hsync-len = <24>;
 153                                 hsync-active = <0>;
 154
 155                                 vback-porch = <3>;
 156                                 vfront-porch = <8>;
 157                                 vsync-len = <4>;
 158                                 vsync-active = <0>;
 159                         };
 160                 };
 161         };
 162
 163         sound {
 164                 compatible = "audio-graph-card";
 165                 label = "sound-card";
 166                 pinctrl-names = "default";
 167                 pinctrl-0 = <&audio_pa_pins>;
 168
 169                 widgets = "Headphone", "Headphone Jack",
 170                           "Speaker", "Speaker External",
 171                           "Line", "Line In",
 172                           "Microphone", "Microphone Jack";
 173
 174                 routing = "Headphone Jack",     "HPLOUT",
 175                           "Headphone Jack",     "HPROUT",
 176                           "Amplifier",          "MONO_LOUT",
 177                           "Speaker External",   "Amplifier",
 178                           "LINE1R",             "Line In",
 179                           "LINE1L",             "Line In",
 180                           "MIC3L",              "Microphone Jack",
 181                           "MIC3R",              "Microphone Jack",
 182                           "Microphone Jack",    "Mic Bias";
 183
 184                 dais = <&cpu_port>;
 185
 186                 pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
 187         };
 188
 189         emmc_pwrseq: pwrseq@0 {
 190                 compatible = "mmc-pwrseq-emmc";
 191                 pinctrl-names = "default";
 192                 pinctrl-0 = <&emmc_pwrseq_pins>;
 193                 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
 194         };
 195
 196         vdd_sys_reg: regulator@0 {
 197                 compatible = "regulator-fixed";
 198                 regulator-name = "vdd_sys_reg";
 199                 regulator-min-microvolt = <5000000>;
 200                 regulator-max-microvolt = <5000000>;
 201                 regulator-always-on;
 202         };
 203
 204         vmmcsd_fixed: fixedregulator0 {
 205                 compatible = "regulator-fixed";
 206                 regulator-name = "vmmcsd_fixed";
 207                 regulator-min-microvolt = <3300000>;
 208                 regulator-max-microvolt = <3300000>;
 209         };
 210 };
 211
 212 &am33xx_pinmux {
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&lwb_pins>;
 215
 216         audio_pins: pinmux_audio_pins {
 217                 pinctrl-single,pins = <
 218                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
 219                         AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
 220                         AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
 221                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
 222                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
 223                 >;
 224         };
 225
 226         audio_pa_pins: pinmux_audio_pa_pins {
 227                 pinctrl-single,pins = <
 228                         AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7)  /* SoundPA_en - mcasp0_aclkr.gpio3_18 */
 229                 >;
 230         };
 231
 232         audio_mclk_pins: pinmux_audio_mclk_pins {
 233                 pinctrl-single,pins = <
 234                         AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a11.gpio1_27 */
 235                 >;
 236         };
 237
 238         backlight0_pins: pinmux_backlight0_pins {
 239                 pinctrl-single,pins = <
 240                         AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)      /* gpmc_wen.gpio2_4 */
 241                 >;
 242         };
 243
 244         backlight1_pins: pinmux_backlight1_pins {
 245                 pinctrl-single,pins = <
 246                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)     /* gpmc_ad10.gpio0_26 */
 247                 >;
 248         };
 249
 250         lcd_pins: pinmux_lcd_pins {
 251                 pinctrl-single,pins = <
 252                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
 253                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
 254                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
 255                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
 256                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
 257                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
 258                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
 259                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
 260                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
 261                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
 262                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
 263                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
 264                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
 265                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
 266                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
 267                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
 268                         AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 269                         AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 270                         AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 271                         AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 272                 >;
 273         };
 274
 275         led_pins: pinmux_led_pins {
 276                 pinctrl-single,pins = <
 277                         AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a5.gpio1_21 */
 278                         AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a6.gpio1_22 */
 279                         AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a7.gpio1_23 */
 280                         AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)       /* gpmc_a8.gpio1_24 */
 281                 >;
 282         };
 283
 284         uart0_pins: pinmux_uart0_pins {
 285                 pinctrl-single,pins = <
 286                         AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
 287                         AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 288                 >;
 289         };
 290
 291         uart1_pins: pinmux_uart1_pins {
 292                 pinctrl-single,pins = <
 293                         AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
 294                         AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 295                 >;
 296         };
 297
 298         uart4_pins: pinmux_uart4_pins {
 299                 pinctrl-single,pins = <
 300                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)      /* gpmc_wait0.uart4_rxd */
 301                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)     /* gpmc_wpn.uart4_txd */
 302                 >;
 303         };
 304
 305         i2c0_pins: pinmux_i2c0_pins {
 306                 pinctrl-single,pins = <
 307                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
 308                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
 309                 >;
 310         };
 311
 312         i2c2_pins: pinmux_i2c2_pins {
 313                 pinctrl-single,pins = <
 314                         AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart1_ctsn.i2c2_sda */
 315                         AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)      /* uart1_rtsn.i2c2_scl */
 316                 >;
 317         };
 318
 319         cpsw_default: cpsw_default {
 320                 pinctrl-single,pins = <
 321                         /* Slave 1 */
 322                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)
 323                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 324                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)
 325                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 326                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 327                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 328                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 329                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
 330                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
 331                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)
 332                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)
 333                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)
 334                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)
 335                 >;
 336         };
 337
 338         cpsw_sleep: cpsw_sleep {
 339                 pinctrl-single,pins = <
 340                         /* Slave 1 reset value */
 341                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
 342                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 343                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
 344                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
 345                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
 346                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 347                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 348                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 349                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 350                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
 351                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
 352                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 353                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 354                 >;
 355         };
 356
 357         davinci_mdio_default: davinci_mdio_default {
 358                 pinctrl-single,pins = <
 359                         /* MDIO */
 360                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
 361                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 362                         /* Ethernet */
 363                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7)       /* Ethernet_nRST - gpmc_ad14.gpio1_14 */
 364                 >;
 365         };
 366
 367         davinci_mdio_sleep: davinci_mdio_sleep {
 368                 pinctrl-single,pins = <
 369                         /* MDIO reset value */
 370                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
 371                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 372                 >;
 373         };
 374
 375         mmc1_pins: pinmux_mmc1_pins {
 376                 pinctrl-single,pins = <
 377                         AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7)             /* uart0_rtsn.gpio1_9 */
 378                 >;
 379         };
 380
 381         emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
 382                 pinctrl-single,pins = <
 383                         AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7)        /* gpmc_a4.gpio1_20 */
 384                 >;
 385         };
 386
 387         emmc_pins: pinmux_emmc_pins {
 388                 pinctrl-single,pins = <
 389                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
 390                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
 391                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad0.mmc1_dat0 */
 392                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad1.mmc1_dat1 */
 393                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad2.mmc1_dat2 */
 394                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad3.mmc1_dat3 */
 395                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad4.mmc1_dat4 */
 396                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad5.mmc1_dat5 */
 397                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad6.mmc1_dat6 */
 398                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad7.mmc1_dat7 */
 399                 >;
 400         };
 401
 402         ehrpwm1_pins: pinmux_ehrpwm1a_pins {
 403                 pinctrl-single,pins = <
 404                         AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6)       /* gpmc_a2.ehrpwm1a */
 405                         AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6)       /* gpmc_a3.ehrpwm1b */
 406                 >;
 407         };
 408
 409         rtc0_irq_pins: pinmux_rtc0_irq_pins {
 410                 pinctrl-single,pins = <
 411                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7)     /* gpmc_ad9.gpio0_23 */
 412                 >;
 413         };
 414
 415         spi0_pins: pinmux_spi0_pins {
 416                 pinctrl-single,pins = <
 417                         AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */
 418                         AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */
 419                         AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
 420                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)        /* SPI0_CS0 (NBATTSS) */
 421                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0)        /* SPI0_CS1 (FPGA_FLASH_NCS) */
 422                 >;
 423         };
 424
 425         lwb_pins: pinmux_lwb_pins {
 426                 pinctrl-single,pins = <
 427                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)       /* nKbdInt - gpmc_ad12.gpio1_12 */
 428                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)       /* nKbdReset - gpmc_ad13.gpio1_13 */
 429                         AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */
 430                         /* PDI Bus - Battery system */
 431                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset  gpmc_a0.gpio1_16 */
 432                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)       /* BattPDIData gpmc_ad15.gpio1_15 */
 433                         /* FPGA */
 434                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7)        /* FPGA_DONE - gpmc_ad8.gpio0_22 */
 435                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */
 436                         AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* FPGA_RUN - gpmc_a1.gpio1_17 */
 437                         AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */
 438                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */
 439                 >;
 440         };
 441 };
 442
 443 &i2c0 {
 444         status = "okay";
 445         pinctrl-names = "default";
 446         pinctrl-0 = <&i2c0_pins>;
 447
 448         clock-frequency = <400000>;
 449
 450         tps: tps@24 {
 451                 reg = <0x24>;
 452         };
 453
 454         rtc0: rtc@68 {
 455                 compatible = "dallas,ds1339";
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&rtc0_irq_pins>;
 458                 interrupt-parent = <&gpio0>;
 459                 interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */
 460                 wakeup-source;
 461                 trickle-resistor-ohms = <2000>;
 462                 reg = <0x68>;
 463         };
 464
 465         eeprom: eeprom@50 {
 466                 compatible = "atmel,24c256";
 467                 reg = <0x50>;
 468         };
 469
 470         gpio_exp: mcp23017@20 {
 471                 compatible = "microchip,mcp23017";
 472                 reg = <0x20>;
 473         };
 474
 475 };
 476
 477 &i2c2 {
 478         status = "okay";
 479         pinctrl-names = "default";
 480         pinctrl-0 = <&i2c2_pins>;
 481
 482         clock-frequency = <400000>;
 483
 484         audio_codec: tlv320aic3106@1b {
 485                 status = "okay";
 486                 compatible = "ti,tlv320aic3106";
 487                 #sound-dai-cells = <0>;
 488                 reg = <0x1b>;
 489                 ai3x-micbias-vg = <2>;  /* 2.5V */
 490
 491                 AVDD-supply = <&ldo4_reg>;
 492                 IOVDD-supply = <&ldo4_reg>;
 493                 DRVDD-supply = <&ldo4_reg>;
 494                 DVDD-supply = <&ldo3_reg>;
 495
 496                 codec_port: port {
 497                         codec_endpoint: endpoint {
 498                                 remote-endpoint = <&cpu_endpoint>;
 499                                 clocks = <&audio_mclk>;
 500                         };
 501                 };
 502         };
 503
 504         /* Ambient Light Sensor */
 505         als: isl29023@44 {
 506                 compatible = "isil,isl29023";
 507                 reg = <0x44>;
 508         };
 509 };
 510
 511 &rtc {
 512         status = "disabled";
 513 };
 514
 515 &usb0 {
 516         dr_mode = "otg";
 517 };
 518
 519 &usb1 {
 520         dr_mode = "host";
 521 };
 522
 523 &mmc1 {
 524         status = "okay";
 525         pinctrl-names = "default";
 526         pinctrl-0 = <&mmc1_pins>;
 527         bus-width = <4>;
 528         cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 529         vmmc-supply = <&vmmcsd_fixed>;
 530 };
 531
 532 &mmc2 {
 533         status = "okay";
 534         pinctrl-names = "default";
 535         pinctrl-0 = <&emmc_pins>;
 536         bus-width = <8>;
 537         vmmc-supply = <&vmmcsd_fixed>;
 538         mmc-pwrseq = <&emmc_pwrseq>;
 539 };
 540
 541 &mcasp0 {
 542         status = "okay";
 543         pinctrl-names = "default";
 544         pinctrl-0 = <&audio_pins>;
 545         #sound-dai-cells = <0>;
 546         op-mode = <0>;  /* MCASP_ISS_MODE */
 547         tdm-slots = <2>;
 548         /* 4 serializers */
 549         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 550                 0 0 1 2
 551         >;
 552         tx-num-evt = <32>;
 553         rx-num-evt = <32>;
 554
 555         cpu_port: port {
 556                 cpu_endpoint: endpoint {
 557                         remote-endpoint = <&codec_endpoint>;
 558
 559                         dai-format = "dsp_b";
 560                         bitclock-master = <&codec_port>;
 561                         frame-master = <&codec_port>;
 562                         bitclock-inversion;
 563                         clocks = <&audio_mclk>;
 564                 };
 565         };
 566 };
 567
 568 &uart0 {
 569         status = "okay";
 570         pinctrl-names = "default";
 571         pinctrl-0 = <&uart0_pins>;
 572 };
 573
 574 &uart1 {
 575         status = "okay";
 576         pinctrl-names = "default";
 577         pinctrl-0 = <&uart1_pins>;
 578 };
 579
 580 &uart4 {
 581         status = "okay";
 582         pinctrl-names = "default";
 583         pinctrl-0 = <&uart4_pins>;
 584 };
 585
 586 &spi0 {
 587         status = "okay";
 588         pinctrl-names = "default";
 589         pinctrl-0 = <&spi0_pins>;
 590
 591         flash: n25q032@1 {
 592                 #address-cells = <1>;
 593                 #size-cells = <1>;
 594                 compatible = "micron,n25q032";
 595                 reg = <1>;
 596                 spi-max-frequency = <5000000>;
 597         };
 598 };
 599
 600 #include "tps65217.dtsi"
 601
 602 &tps {
 603         ti,pmic-shutdown-controller;
 604
 605         interrupt-parent = <&intc>;
 606         interrupts = <7>;       /* NNMI */
 607
 608         regulators {
 609                 dcdc1_reg: regulator@0 {
 610                         /* VDDS_DDR */
 611                         regulator-min-microvolt = <1500000>;
 612                         regulator-max-microvolt = <1500000>;
 613                         regulator-always-on;
 614                 };
 615
 616                 dcdc2_reg: regulator@1 {
 617                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 618                         regulator-name = "vdd_mpu";
 619                         regulator-min-microvolt = <925000>;
 620                         regulator-max-microvolt = <1325000>;
 621                         regulator-boot-on;
 622                         regulator-always-on;
 623                 };
 624
 625                 dcdc3_reg: regulator@2 {
 626                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 627                         regulator-name = "vdd_core";
 628                         regulator-min-microvolt = <925000>;
 629                         regulator-max-microvolt = <1150000>;
 630                         regulator-boot-on;
 631                         regulator-always-on;
 632                 };
 633
 634                 ldo1_reg: regulator@3 {
 635                         /* VRTC / VIO / VDDS*/
 636                         regulator-always-on;
 637                         regulator-min-microvolt = <1800000>;
 638                         regulator-max-microvolt = <1800000>;
 639                 };
 640
 641                 ldo2_reg: regulator@4 {
 642                         /* VDD_3V3AUX */
 643                         regulator-always-on;
 644                         regulator-min-microvolt = <3300000>;
 645                         regulator-max-microvolt = <3300000>;
 646                 };
 647
 648                 ldo3_reg: regulator@5 {
 649                         /* VDD_1V8 */
 650                         regulator-min-microvolt = <1800000>;
 651                         regulator-max-microvolt = <1800000>;
 652                         regulator-always-on;
 653                 };
 654
 655                 ldo4_reg: regulator@6 {
 656                         /* VDD_3V3A */
 657                         regulator-min-microvolt = <3300000>;
 658                         regulator-max-microvolt = <3300000>;
 659                         regulator-always-on;
 660                 };
 661         };
 662 };
 663
 664 &cpsw_port1 {
 665         phy-mode = "mii";
 666         phy-handle = <&ethphy0>;
 667         ti,dual-emac-pvid = <1>;
 668 };
 669
 670 &cpsw_port2 {
 671         status = "disabled";
 672 };
 673
 674 &mac_sw {
 675         status = "okay";
 676         pinctrl-names = "default", "sleep";
 677         pinctrl-0 = <&cpsw_default>;
 678         pinctrl-1 = <&cpsw_sleep>;
 679 };
 680
 681 &davinci_mdio_sw {
 682         pinctrl-names = "default", "sleep";
 683         pinctrl-0 = <&davinci_mdio_default>;
 684         pinctrl-1 = <&davinci_mdio_sleep>;
 685         reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 686         reset-delay-us = <100>;   /* PHY datasheet states 100us min */
 687
 688         ethphy0: ethernet-phy@0 {
 689                 reg = <0>;
 690         };
 691 };
 692
 693 &sham {
 694         status = "okay";
 695 };
 696
 697 &aes {
 698         status = "okay";
 699 };
 700
 701 &epwmss1 {
 702         status = "okay";
 703 };
 704
 705 &ehrpwm1 {
 706         status = "okay";
 707         pinctrl-names = "default";
 708         pinctrl-0 = <&ehrpwm1_pins>;
 709 };
 710
 711 &lcdc {
 712         status = "okay";
 713 };
 714
 715 &tscadc {
 716         status = "okay";
 717 };
 718
 719 &am335x_adc {
 720         ti,adc-channels = <0 1 2 3 4 5 6 7>;
 721 };