arch/arm/boot/dts/am335x-shc.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * support for the bosch am335x based shc c3 board
   4  *
   5  * Copyright, C) 2015 Heiko Schocher <hs@denx.de>
   6  *
   7  */
   8 /dts-v1/;
   9
  10 #include "am33xx.dtsi"
  11 #include <dt-bindings/input/input.h>
  12
  13 / {
  14         model = "Bosch SHC";
  15         compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx";
  16
  17         aliases {
  18                 mmcblk0 = &mmc1;
  19                 mmcblk1 = &mmc2;
  20         };
  21
  22         cpus {
  23                 cpu@0 {
  24                         /*
  25                          * To consider voltage drop between PMIC and SoC,
  26                          * tolerance value is reduced to 2% from 4% and
  27                          * voltage value is increased as a precaution.
  28                          */
  29                         operating-points = <
  30                                 /* kHz    uV */
  31                                 594000  1225000
  32                                 294000  1125000
  33                         >;
  34                         voltage-tolerance = <2>; /* 2 percentage */
  35                         cpu0-supply = <&dcdc2_reg>;
  36                 };
  37         };
  38
  39         gpio_keys {
  40                 compatible = "gpio-keys";
  41
  42                 back_button {
  43                         label = "Back Button";
  44                         gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  45                         linux,code = <KEY_BACK>;
  46                         debounce-interval = <1000>;
  47                         wakeup-source;
  48                 };
  49
  50                 front_button {
  51                         label = "Front Button";
  52                         gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
  53                         linux,code = <KEY_FRONT>;
  54                         debounce-interval = <1000>;
  55                         wakeup-source;
  56                 };
  57         };
  58
  59         leds {
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&user_leds_s0>;
  62
  63                 compatible = "gpio-leds";
  64
  65                 led1 {
  66                         label = "shc:power:red";
  67                         gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
  68                         default-state = "off";
  69                 };
  70
  71                 led2 {
  72                         label = "shc:power:bl";
  73                         gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
  74                         linux,default-trigger = "timer";
  75                         default-state = "on";
  76                 };
  77
  78                 led3 {
  79                         label = "shc:lan:red";
  80                         gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
  81                         default-state = "off";
  82                 };
  83
  84                 led4 {
  85                         label = "shc:lan:bl";
  86                         gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
  87                         default-state = "off";
  88                 };
  89
  90                 led5 {
  91                         label = "shc:cloud:red";
  92                         gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
  93                         default-state = "off";
  94                 };
  95
  96                 led6 {
  97                         label = "shc:cloud:bl";
  98                         gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
  99                         default-state = "off";
 100                 };
 101         };
 102
 103         memory@80000000 {
 104                 device_type = "memory";
 105                 reg = <0x80000000 0x20000000>; /* 512 MB */
 106         };
 107
 108         vmmcsd_fixed: fixedregulator0 {
 109                 compatible = "regulator-fixed";
 110                 regulator-name = "vmmcsd_fixed";
 111                 regulator-min-microvolt = <3300000>;
 112                 regulator-max-microvolt = <3300000>;
 113         };
 114 };
 115
 116 &aes {
 117         status = "okay";
 118 };
 119
 120 &davinci_mdio {
 121         pinctrl-names = "default", "sleep";
 122         pinctrl-0 = <&davinci_mdio_default>;
 123         pinctrl-1 = <&davinci_mdio_sleep>;
 124         status = "okay";
 125
 126         ethernetphy0: ethernet-phy@0 {
 127                 reg = <0>;
 128                 smsc,disable-energy-detect;
 129         };
 130 };
 131
 132 &epwmss1 {
 133         status = "okay";
 134
 135         ehrpwm1: pwm@200 {
 136                 pinctrl-names = "default";
 137                 pinctrl-0 = <&ehrpwm1_pins>;
 138                 status = "okay";
 139         };
 140 };
 141
 142 &gpio1 {
 143         hmtc-rst-hog {
 144                 gpio-hog;
 145                 gpios = <24 GPIO_ACTIVE_LOW>;
 146                 output-high;
 147                 line-name = "homematic_reset";
 148         };
 149
 150         hmtc-prog-hog {
 151                 gpio-hog;
 152                 gpios = <27 GPIO_ACTIVE_LOW>;
 153                 output-high;
 154                 line-name = "homematic_program";
 155         };
 156 };
 157
 158 &gpio3 {
 159         zgb-rst-hog {
 160                 gpio-hog;
 161                 gpios = <18 GPIO_ACTIVE_LOW>;
 162                 output-low;
 163                 line-name = "zigbee_reset";
 164         };
 165
 166         zgb-boot-hog {
 167                 gpio-hog;
 168                 gpios = <19 GPIO_ACTIVE_HIGH>;
 169                 output-high;
 170                 line-name = "zigbee_boot";
 171         };
 172 };
 173
 174 &i2c0 {
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&i2c0_pins>;
 177         status = "okay";
 178         clock-frequency = <400000>;
 179
 180         tps: tps@24 {
 181                 reg = <0x24>;
 182         };
 183
 184         at24@50 {
 185                 compatible = "atmel,24c32";
 186                 pagesize = <32>;
 187                 reg = <0x50>;
 188         };
 189
 190         pcf8563@51 {
 191                 compatible = "nxp,pcf8563";
 192                 reg = <0x51>;
 193         };
 194 };
 195
 196 &mac {
 197         pinctrl-names = "default", "sleep";
 198         pinctrl-0 = <&cpsw_default>;
 199         pinctrl-1 = <&cpsw_sleep>;
 200         status = "okay";
 201         slaves = <1>;
 202         cpsw_emac0: slave@200 {
 203                 phy-mode = "mii";
 204                 phy-handle = <&ethernetphy0>;
 205         };
 206 };
 207
 208 &mmc1 {
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&mmc1_pins>;
 211         bus-width = <0x4>;
 212         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 213         cd-inverted;
 214         max-frequency = <26000000>;
 215         vmmc-supply = <&vmmcsd_fixed>;
 216         status = "okay";
 217 };
 218
 219 &mmc2 {
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&emmc_pins>;
 222         bus-width = <8>;
 223         max-frequency = <26000000>;
 224         sd-uhs-sdr25;
 225         vmmc-supply = <&vmmcsd_fixed>;
 226         status = "okay";
 227 };
 228
 229 &mmc3 {
 230         pinctrl-names = "default";
 231         pinctrl-0 = <&mmc3_pins>;
 232         bus-width = <4>;
 233         cap-power-off-card;
 234         max-frequency = <26000000>;
 235         sd-uhs-sdr25;
 236         vmmc-supply = <&vmmcsd_fixed>;
 237         status = "okay";
 238 };
 239
 240 &rtc {
 241         ti,no-init;
 242 };
 243
 244 &sham {
 245         status = "okay";
 246 };
 247
 248 &tps {
 249         compatible = "ti,tps65217";
 250         ti,pmic-shutdown-controller;
 251
 252         regulators {
 253                 #address-cells = <1>;
 254                 #size-cells = <0>;
 255
 256                 dcdc1_reg: regulator@0 {
 257                         reg = <0>;
 258                         regulator-name = "vdds_dpr";
 259                         regulator-compatible = "dcdc1";
 260                         regulator-min-microvolt = <1300000>;
 261                         regulator-max-microvolt = <1450000>;
 262                         regulator-boot-on;
 263                         regulator-always-on;
 264                 };
 265
 266                 dcdc2_reg: regulator@1 {
 267                         reg = <1>;
 268                         /*
 269                          * VDD_MPU voltage limits 0.95V - 1.26V with
 270                          * +/-4% tolerance
 271                          */
 272                         regulator-compatible = "dcdc2";
 273                         regulator-name = "vdd_mpu";
 274                         regulator-min-microvolt = <925000>;
 275                         regulator-max-microvolt = <1375000>;
 276                         regulator-boot-on;
 277                         regulator-always-on;
 278                         regulator-ramp-delay = <70000>;
 279                 };
 280
 281                 dcdc3_reg: regulator@2 {
 282                         reg = <2>;
 283                         /*
 284                          * VDD_CORE voltage limits 0.95V - 1.1V with
 285                          * +/-4% tolerance
 286                          */
 287                         regulator-name = "vdd_core";
 288                         regulator-compatible = "dcdc3";
 289                         regulator-min-microvolt = <925000>;
 290                         regulator-max-microvolt = <1125000>;
 291                         regulator-boot-on;
 292                         regulator-always-on;
 293                 };
 294
 295                 ldo1_reg: regulator@3 {
 296                         reg = <3>;
 297                         regulator-name = "vio,vrtc,vdds";
 298                         regulator-compatible = "ldo1";
 299                         regulator-min-microvolt = <1000000>;
 300                         regulator-max-microvolt = <1800000>;
 301                         regulator-always-on;
 302                 };
 303
 304                 ldo2_reg: regulator@4 {
 305                         reg = <4>;
 306                         regulator-name = "vdd_3v3aux";
 307                         regulator-compatible = "ldo2";
 308                         regulator-min-microvolt = <900000>;
 309                         regulator-max-microvolt = <3300000>;
 310                         regulator-always-on;
 311                 };
 312
 313                 ldo3_reg: regulator@5 {
 314                         reg = <5>;
 315                         regulator-name = "vdd_1v8";
 316                         regulator-compatible = "ldo3";
 317                         regulator-min-microvolt = <900000>;
 318                         regulator-max-microvolt = <1800000>;
 319                         regulator-always-on;
 320                 };
 321
 322                 ldo4_reg: regulator@6 {
 323                         reg = <6>;
 324                         regulator-name = "vdd_3v3a";
 325                         regulator-compatible = "ldo4";
 326                         regulator-min-microvolt = <1800000>;
 327                         regulator-max-microvolt = <3300000>;
 328                         regulator-always-on;
 329                 };
 330         };
 331 };
 332
 333 &uart0 {
 334         pinctrl-names = "default";
 335         pinctrl-0 = <&uart0_pins>;
 336         status = "okay";
 337 };
 338
 339 &uart1 {
 340         pinctrl-names = "default";
 341         pinctrl-0 = <&uart1_pins>;
 342         status = "okay";
 343 };
 344
 345 &uart2 {
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&uart2_pins>;
 348         status = "okay";
 349 };
 350
 351 &uart4 {
 352         pinctrl-names = "default";
 353         pinctrl-0 = <&uart4_pins>;
 354         status = "okay";
 355 };
 356
 357 &usb1 {
 358         dr_mode = "host";
 359 };
 360
 361 &am33xx_pinmux {
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&clkout2_pin>;
 364
 365         clkout2_pin: pinmux_clkout2_pin {
 366                 pinctrl-single,pins = <
 367                         /* xdma_event_intr1.clkout2 */
 368                         AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6)
 369                 >;
 370         };
 371
 372         cpsw_default: cpsw_default {
 373                 pinctrl-single,pins = <
 374                         /* Slave 1 */
 375                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0)
 376                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 377                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0)
 378                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 379                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 380                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
 381                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
 382                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
 383                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
 384                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
 385                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
 386                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
 387                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
 388                 >;
 389         };
 390
 391         cpsw_sleep: cpsw_sleep {
 392                 pinctrl-single,pins = <
 393                         /* Slave 1 reset value */
 394                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
 395                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 396                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
 397                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
 398                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
 399                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 400                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 401                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 402                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 403                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
 404                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
 405                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 406                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 407                 >;
 408         };
 409
 410         davinci_mdio_default: davinci_mdio_default {
 411                 pinctrl-single,pins = <
 412                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
 413                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 414                 >;
 415         };
 416
 417         davinci_mdio_sleep: davinci_mdio_sleep {
 418                 pinctrl-single,pins = <
 419                         /* MDIO reset value */
 420                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
 421                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 422                 >;
 423         };
 424
 425         ehrpwm1_pins: pinmux_ehrpwm1 {
 426                 pinctrl-single,pins = <
 427                         AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */
 428                 >;
 429         };
 430
 431         emmc_pins: pinmux_emmc_pins {
 432                 pinctrl-single,pins = <
 433                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2)
 434                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)
 435                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)
 436                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)
 437                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)
 438                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)
 439                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)
 440                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)
 441                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)
 442                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)
 443                 >;
 444         };
 445
 446         i2c0_pins: pinmux_i2c0_pins {
 447                 pinctrl-single,pins = <
 448                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
 449                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
 450                 >;
 451         };
 452
 453         mmc1_pins: pinmux_mmc1_pins {
 454                 pinctrl-single,pins = <
 455                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5)
 456                 >;
 457         };
 458
 459         mmc3_pins: pinmux_mmc3_pins {
 460                 pinctrl-single,pins = <
 461                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3)
 462                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3)
 463                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3)
 464                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3)
 465                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3)
 466                         AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3)
 467                 >;
 468         };
 469
 470         uart0_pins: pinmux_uart0_pins {
 471                 pinctrl-single,pins = <
 472                         AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
 473                         AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0)
 474                         AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0)
 475                         AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)
 476                 >;
 477         };
 478
 479         uart1_pins: pinmux_uart1 {
 480                 pinctrl-single,pins = <
 481                         AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
 482                         AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0)
 483                         AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
 484                         AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
 485                 >;
 486         };
 487
 488         uart2_pins: pinmux_uart2_pins {
 489                 pinctrl-single,pins = <
 490                         AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)
 491                         AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)
 492                 >;
 493         };
 494
 495         uart4_pins: pinmux_uart4_pins {
 496                 pinctrl-single,pins = <
 497                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)
 498                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6)
 499                 >;
 500         };
 501
 502         user_leds_s0: user_leds_s0 {
 503                 pinctrl-single,pins = <
 504                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7)
 505                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7)
 506                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)
 507                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7)
 508                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7)
 509                         AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7)
 510                         AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7)
 511                         AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
 512                         AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)
 513                         AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)
 514                         AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7)
 515                         AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7)
 516                         AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7)
 517                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)
 518                         AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7)
 519                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7)
 520                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7)
 521                         AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7)
 522                         AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7)
 523                         AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)
 524                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7)
 525                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7)
 526                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7)
 527                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7)
 528                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7)
 529                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7)
 530                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7)
 531                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7)
 532                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7)
 533                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7)
 534                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7)
 535                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7)
 536                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7)
 537                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7)
 538                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7)
 539                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7)
 540                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7)
 541                         AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7)
 542                         AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7)
 543                         AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7)
 544                         AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7)
 545                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 546                         AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7)
 547                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7)
 548                         AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7)
 549                         AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
 550                         AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
 551                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 552                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7)
 553                 >;
 554         };
 555 };